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Fu Jen Catholic University, Dept of Computer Science and Information Engineering –CSIE 資訊工程系-輔仁大學
100-2 課程大綱 (2011 – 2012)
posted in Dec 2011 Department/Code(開課單位/課程代碼)
Dept. Of CSIE (Computer Science and Information Engineering) 資工系二甲/ D-5112-10418
Instructor:/ 教授 周賜福 教授 (Dr. Joseph Arul) Dept. of CSIE, Fu Jen Course Code/Day
(課程代碼/週日/教室)
Every Thursdays(週四) 15:40~17:30 (Hours 7&8) 每週星期四 15:40 ~ 17:30PM ~ SF551
Basic/必修 Dept/Year Course Name
(課程名稱)
Fund. of Digital Logic-Lab Exp.
數位系統導論實驗
Credits
(學分數) 1 學分 資工二甲
Course Objectives (課程目標)
1. This course covers the fundamental principles and techniques for designing and implementing digital hardware systems using Hardware descriptional Language such as VHDL or Verilog.
2. This course presents the basic tools for the design of synchronous sequential circuits and covers methods using Altera Board and implementing using Hardware Language.
3. A student who successfully fulfills the course requirements will learn to analyze and design digital, clocked sequential circuits on the Real Board such as DE2-70 in the laboratory.
Prerequisites (先修課程)
You should have written some high-level language programming such as C, C++ or Java, Introduction to Computer Science. Understanding of computers Basic Text Book
(課程教材)
Fundamentals of Logic Design, By Charles H. Roth, Jr, Larry L. Kinney, Six Edition,滄海書局-趙竣(業務員)台中市(04)27088787or 0932597322 Tsing Hua Publishing in Taiwan.
Fundamentals of Digital Logic with VHDL Design.
Other Reference Text(參考書目) Supporting Website.
1. Altera Quartus Software and compiler for VHDL language as well as the Web-page materials on Quartus software.
Evaluation Option (評量方式)
z Midterm Exam (期中紙筆考) 30％,
z Final Exam (期末上機考) 30％, Total 100%
z Lab Assignments (課當作業) 40%
Pedagogical Methods ( 教學方法)
■講授(Lecture) ■自主學習(Independent Study)
■個案教學(case study) □體驗教學(Project Adventure)
▓其他(Others) Programming in Assembly Course Web
(課程網頁)
Refer to Fu Jen- ICAN system for the course Materials, Home work Assignments and any announcements during the course and to contact me.
Course Outline (課程大綱進度)
1 Introduction to VHDL or Verilog
2. Introduction to Quartus software on Altera usage.
3. Latches and Flip-flops 4. Registers and Counters
5. Analysis of clocked sequential Circuits 6. Derivation of state Graphs and Tables
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7. VHDL for Sequential Logic.
10. State Machine Design With SM charts.
Contribution to Learning Goals (本課程能達成開 課單位的哪些目標 -院)
▓強調科技新的精神, 培養科學的放法與求真態度。
▓特別重視專業倫理之教導與培養, 因為科學研究的最終目的也是未造 福人群,服務社會。
▓培養學生關心科技發展的趨勢並具洞察環境變化的能力。
Grading Policy and Homework submission Guidelines
家庭作業： 全學期陸續會分配家庭作業。每份作業該在指定日，上課前繳交。遲交者 將扣減該作業總分的百分之二十。 在指定日後二周，不收作業。沒交的作業，以零分 計算。
繳交的規定：所有作業，必在上課前繳交給老師。你可以和同學研究討論，但作業一定 要自己用心做。 務必要遵守下列學術誠實的規則：
出缺席規定：準時出席上課。有效積極地參加課堂上的學習，對你的吸收和成果表現十 分重要，也是累積總分的一部分。萬一交作業當天，你有事不能來，你可以事前或上課 開始前，拜託同學幫忙你交遞給老師。並請遵守前文有關考試的規定，按步就班跟進，
不要臨時抱佛腳，否則是自找麻煩。
學術誠實的規定：務必遵守輔仁大學的校規。誠實、不舞弊 不抄襲。本教授將嚴守校 規，違者必罰。通常，凡作業未交、積分低差的，總成績也會失敗不及格，再加輔仁大 學校規的處分。除非另定或交待，所有作業應該是學生親自努力的成果，不該假手他人 代做。違規者必視為不誠實，而按規定受罰。在採用網路資訊時，請小心！不要忘記載 錄來源！
Homework Policy: Few home works will be assigned throughout the term.
Home works are due at the start of the class on the due date. (Kindly note very carefully) After two weeks of the due date, homework will not be accepted. If you pass the due date and the time, 20% will be detected.
Copying of the homework will be penalized resulting in failing of the course.
Turn in Policy: Turn in all the work to the instructor, preferably before class on the Due date. Make sure that the work is done on your own without discussing with other classmates. Refer to the Academic Honesty below.
Absence and Participating Policy: Class attendance and effective, constructive participation is important to your performance in the course and makes up a portion of the grade based on the instructor’s discretion. If you cannot make it to the class on the date something is due, please make arrangements to have someone else bring your assignment to me before or at the start of the class. Also note the exam absence policy mentioned earlier.
Don’t wait for the last day to cover up all the materials. It will be too hard.
Academic Honesty: Follow the University policy on academic honesty. The instructor’s academic honesty policy is very strict; instances of academic dishonesty will be penalized, ordinarily by at least a failure on the assignment and likely failure in the course (in addition to any University penalties).
Unless otherwise stated, all work is to be individual work. Violations of the individual work policy will be regarded as instances of academic dishonesty.
Beware of copying materials from the Internet (Don’t forget to cite the materials.)
Instructor Contacting:
(老師資料)
Name: 周賜福 - Dr. Joseph Arul [email protected]
Office: SF 615/聖言樓 615 Phone: Of: (02)2905-3896 Office Hour: Tuesdays 8:10AM to 9:00AM
Good Wishes (祝你)
最後！ 祝你快樂得高分!
Good Luck! Try to receive above 90pts in this course.
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