US007398410B2
(12) Ulllted States Patent (10) Patent N0.: US 7,398,410 B2
Lee et al. (45) Date of Patent: Jul. 8, 2008
(54) PROCESSOR EMPLOYINGA POWER 6,219,796 B1 * 4/2001 Bartley ... .. 713/320 MANAGING MECHANISM AND METHOD OF 6,795,781 B2 * 9/2004 Aldridge et a1. ... .. 702/60 SAVING POWER FOR THE SAME 6,924,999 B2 * 8/2005 Masui ... .. 365/145
_ 7,058,458 B2 * 6/2006 Munezane . .. . 700/12
(75) IIWBIIIOFSI Jellq-Klle_n LFe,Ta_1I1a_I1(TW); _ _ 7,107,471 B2 * 9/2006 Feierbach .... .. 713/324 Yullg-chlfl L111, TaIPeI (TW); YI'Pmg 2005/0283629 Al* 12/2005 Tanaka e161. ... .. 713/322 Y“, Wu Rlh T°WnSh1P> Talchung County 2007/0106914 A1 * 5/2007 Muthukumar et a1. ... .. 713/300
(TW); Chung-Wen Huang, Liu Chiao Township, Chia Yi County (TW)
(73) Assignee: National Tsing Hua University, * cited by examiner
Hsinchu (TW) _ _ . .
Primary ExammeriAbdelmomem Elamm ( * ) Notice: Subject to any disclaimer, the term of this (74) Attorney! Agent! 0'’ FirmiEgben Law Of?ces
patent is extended or adjusted under 35
U.S.C. 154(b) by 462 days. (57) ABSTRACT
21 A l.N .: 11/177 369
( ) pp 0 ’ Aprocessor includesaplurality of executionunits con?gured
(22) Filed: JUL 8, 2005 to execute instructions, a pre-decoder con?gured to sieve out a power-switching instruction from the instructions, and a (65) Prior Publication Data power controller con?gured to control the status of the execu
tion unit based on the power-switching instruction. The Us 2007/0011474 A1 Jan' 11’ 2007 power controller includes an identi?cation decoder con?g
ured to generate identi?cations respectively corresponding to
(51) Int‘ C1‘ the execution units from the power- switching instruction, and
G06F 1/32 (200601) a power manager con?gured to switch the execution unit (52) US. Cl. ... .. 713/324, 713/300, 713/310, Corresponding to the identi?cation‘ Particularly, the Power._
713620; 7136213 7136223 7136233 7136303 switching instruction includes a power-on instruction and a 713/340; 712/43 power-off instruction. The processor further includes a plu (58) Field of Classi?cation Search ... .. 713/300, rality Of reservation tables each Con?gured to Store the
713/310, 3207324, 330, 340; 712/43 instruction to be executed by one of the execution units, and See application ?le for Complete Search history a turn-off signal is not conveyed to the power manager until (56) References Cited the reservation table corresponding to the execution unit to be
turned off 1s empty.
U.S. PATENT DOCUMENTS
6,202,163 B1 * 3/2001 Gabzdyl et a1. ... .. 713/324 11 Claims, 3 Drawing Sheets
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US. Patent Jul. 8, 2008 Sheet 2 of3 US 7,398,410 B2
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US. Patent Jul. 8, 2008 Sheet 3 of3 US 7,398,410 B2
f 40 Rreceiving instructions
42 I 44
Checking if the . .
. . . Regular mstruction
instruction 1s a power 0 eration
switching instruction ‘? p
46 f 48
Generating an identi?cation corresponding to an execution
unit and a turn-on signal
Checking if the power
switching instruction is a ower-off instruction ‘.7
f 52
Generating an identi?cation
corresponding to an execution unit I 50
and a turn-off signal _ _ _
Turning on an execution un1t
corresponding to the identi?cation 54
Checking if a corresponding reservation table is empty ‘.7
56
Turning off an execution unit 3
corresponding to the identi?cation
US 7,398,410 B2 1
PROCESSOR EMPLOYING A POWER MANAGING MECHANISM AND METHOD OF
SAVING POWER FOR THE SAME RELATED U.S. APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
REFERENCE TO MICROFICHE APPENDIX
Not applicable.
FIELD OF THE INVENTION
The present invention relates to a processor employing a poWer managing mechanism and method of saving poWer for the same, and more particularly, to a processor employing a poWer managing mechanism by incorporating a poWer-on instruction and a poWer-off instruction and method of saving poWer for the same.
BACKGROUND OF THE INVENTION
The demands of poWer-constrained mobile and embedded
computing applications increase rapidly. Reducing poWer
consumption hence becomes a crucial challenge for today’s softWare and hardWare developers. While maximization of battery life is an obvious goal, the reduction of heat dissipa tion is important as Well. The reduction of poWer consump tion is an objective similar to the reduction of heat dissipation.Minimization of poWer dissipation can be considered at algo rithmic, architectural, logic and circuit levels. Studies on loW poWer design are abundant in the literature in Which various
techniques have been proposed to synthesiZe designs With
loW transitional activities. Recently, neW research directions in reducing poWer consumption have begun to address the issues on the aspect of architecture designs and on softWare arrangements at instruction-level to help reduce poWer con sumption. The architecture and softWare efforts to reduce energy consumption in recent attempts have been primarily on the dynamic component of poWer dissipation (also knoWn as dynamic poWer).Various techniques have been proposed to reduce the poWer consumption of processors. These techniques include
increasing the integration of circuitry and incorporation of improved circuitry and poWer management units (PMUs).
One speci?c poWer reduction technique employed in proces sors generally involves the capability of stopping clock sig nals that drive inactive circuit portions. A system employing such a technique typically includes a poWer management unit that detects or predicts inactive circuit portions and accord ingly stops the clock signals associated With the inactive
circuit portions. By turning off “unused” clock signals that
drive inactive circuit portions, overall poWer consumption of the system is decreased. A similar technique involves thecapability of reducing the frequency of clock signals that
drive circuit portions during operating modes, Which are not time critical, and another technique involves the capability of removing poWer from inactive circuit portions.15
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BRIEF SUMMARY OF THE INVENTION
The objective of the present invention is to provide a pro cessor employing a poWer managing mechanism by incorpo rating a poWer-on instruction and a poWer-off instruction and method of saving poWer for the same.
In order to achieve the above-mentioned objective and avoid the problems of the prior art, the present invention provides a processor employing a poWer managing mecha nism and method of saving poWer for the same. The processor comprises a plurality of execution units con?gured to execute instructions, a pre-decoder con?gured to sieve out a poWer sWitching instruction from the instructions, and a poWer con troller con?gured to control the on/ off status of the execution unit based on the poWer-sWitching instruction. The poWer controller includes an identi?cation decoder con?gured to generate an identi?cation corresponding to one of the execu tion units from the poWer-sWitching instruction, and a poWer manager con?gured to sWitch on/off status of the execution unit corresponding to the identi?cation. Moreover, in case the other identi?cations corresponding to other execution units can also be generated.
Particularly, the poWer-sWitching instruction includes a poWer-on instruction and a poWer-off instruction, and the identi?cation decoder includes a poWer-on decoder con?g ured to generate the identi?cation and a tum-on signal from the poWer-on instruction and a poWer-off decoder con?gured to generate the identi?cation and a tum-off signal from the poWer-off instruction. The processor further comprises a plu rality of reservation tables each con?gured to store the instruction to be executed by one of the execution units, and the power-off decoder conveys the turn-off signal to the poWer manager after the reservation table corresponding to the execution unit to be turned off is empty.
The present method for saving poWer comprises steps of (1) receiving an instruction; (2) checking if the instruction is a poWer-sWitching instruction, (3) checking if the poWer sWitching instruction is a poWer-off instruction; (4) generat ing at least one identi?cation and a control signal, in Which each identi?cation corresponds to an execution unit; and (5) sWitching the execution unit according to the control signal.
The method may further comprise a step of checking if a reservation table for the execution unit corresponding to the identi?cation is empty on condition that the poWer-sWitching instruction is a poWer-off instruction. The control signal includes a tum-off signal and a turn-on signal, and the tum-off signal is not executed until the reservation table for the execu tion unit corresponding to the identi?cation is empty, i.e., the turn-off signal is executed Whenever the reservation table for the execution unit corresponding to the identi?cation becomes empty.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
The objectives and advantages of the present invention Will
become apparent upon reading the folloWing description and
upon reference to the accompanying draWings.FIG. 1 illustrates a functional block diagram of a processor employing a poWer managing mechanism according to one embodiment of the present invention;
FIG. 2 is a schematic vieW illustrating instructions for a processor employing a poWer managing mechanism accord ing to one embodiment of the present invention.
FIG. 3 illustrates a How chart for a method of saving poWer for a processor employing a poWer managing mechanism according to one embodiment of the present invention.
US 7,398,410 B2 3
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 illustrates a functional block diagram of a processor 10 employing a power managing mechanism according to one embodiment of the present invention. The processor 10 comprises a plurality of execution units 30A-30D each con
?gured to execute instructions, a fetcher 12 con?gured to receive the instruction from a main memory system (not shoWn), a pre-decoder 16 con?gured to sieve out a poWer sWitching instruction from the instructions, and a poWer con troller 20 con?gured to control the poWer supply status, i.e., on/off, of the execution units 30A-30D based on the poWer sWitching instruction. The poWer controller 20 includes an identi?cation decoder 22 con?gured to generate a sWitching signal and at least one identi?cation corresponding to one of the execution units 30A-30D based on the poWer-sWitching instruction, and a poWer manager 28 con?gured to sWitch on/off status of the one of the execution units 30A-30D cor responding to the identi?cation according to the sWitching signal from the identi?cation decoder 22.
Particularly, the poWer-sWitching instruction includes a poWer-on instruction and a poWer-off instruction, and the identi?cation decoder 22 includes a poWer-on decoder 24 con?gured to be able to generate the identi?cation and a turn-on signal based on the poWer-on instruction and a poWer off decoder 26 con?gured to be able to generate the identi?
cation and a turn-off signal based on the poWer-off instruc tion. In other Words, the identi?cation is generated by either the poWer-on decoder 24 or the poWer-off decoder 26. The processor 10 further comprises a plurality of reservation tables including an integer reservation table (RT) 32A, an address reservation table 32B, and a ?oating point reservation table 32C, Wherein each reservation table is con?gured to store the instruction to be executed by one of the execution units 30A-30D. Further, the processor 10 comprises a decoder 16 con?gured to decode regular instructions from the pre-decoder 14 to generate operation signals, and a dispatcher 18 con?gured to convey the operation signals into the reser vation tables 32A-32C.
In addition, the tWo arithmetic-logic execution units (ALU) 30A, 30B are coupled to the integer reservation table 32A, the load/store execution unit (LSU) 32C is coupled to the address reservation table 32B, and the ?oating point execution unit (FPU) 30D is coupled to the ?oating point reservation table 32C. To avoid the execution units 30A-30D being turned off before it completed its operation stored in the reservation table 32A-32C, the poWer-off decoder 26 conveys the turn-off signal to the poWer manager 28 after one of the reservation tables 32A-32C corresponding to one of the execution units 30A-30D to be turned off is empty. For example, each of execution units 30A-30D includes a tran sistor, and the poWer manager 28 turns off the execution unit corresponding the identi?cation via the transistor When
receiving the turn-off signal.
FIG. 2 illustrates instructions of 32 bits for the processor 10 employing a poWer managing mechanism according to one embodiment of the present invention. The front three bits are used to indicate the regular instruction, the poWer-on instruc tion, and the poWer-instruction, and the other 29 bits can be used to represent the identi?cation of the execution unit, i.e., there are up to 229 identi?cations can be represented by the 29 bits. Once the pre-decoder 14 receives an instruction from the fetcher 12, the pre-decoder 14 can easily and quickly identify the type of the incoming instruction from the front three bits Without delay, and then deliver the instruction identi?ed as an regular instruction to the decoder 16, the one identi?ed as a
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poWer-on instruction to the poWer-on decoder 24, or the one identi?ed as a poWer-off instruction to the poWer-off decoder 26.
FIG. 3 illustrates a ?oW chart for a method of saving poWer for the processor 10 according to one embodiment of the present invention. In step 40, instructions are received. In step 42, a check is conducted to verify if the instruction is a poWer-sWitching instruction. If the incoming instruction is not a poWer sWitching instruction, i.e., it is a regular instruc tion, the present method goes forWard to the regular instruc tion operation as the prior skill does. If the incoming instruc tion is a poWer sWitching instruction, a check to verify if the poWer-sWitching instruction is a poWer-off instruction is con ducted as indicated in step 46. If the poWer-sWitching instruc tion is not a poWer-off instruction, i.e., it is a poWer-on instruction, an identi?cation corresponding to an execution unit and a turn-on signal from the poWer-on instruction are generated as indicated in step 48, and then an execution unit corresponding to the identi?cation is turned on as indicated in step 50.
If the poWer-sWitching instruction is a poWer-off instruc tion at the step 46, an identi?cation corresponding to an execution unit and a turn-off signal from the poWer-off instruction are generated as indicated in step 50. Subse quently, in step 54, a check is conducted to verify if a reser vation table corresponding to an execution unit of the identi
?cation is empty. The operation of the step 54 is not terminated until the reservation table is empty. In step 56, once the reservation table is empty, the turn-off signal is then conveyed. Accordingly, an execution unit corresponding to the identi?cation is turned off according to the turn-off signal.
Obviously, one of the execution units can be optionally turned on to perform a desired operation and optionally turned off When it completes its operation in accordance With the present invention. Thus, poWer can be saved because poWer supply can be optionally suspended When no operation to be executed.
The above-described embodiments of the present inven tion are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art With out departing from the scope of the folloWing claims.
We claim:
1. A processor employing a poWer managing mechanism
comprising:
a plurality of execution units con?gured to execute instruc
tions;
a precoder con?gured to sieve out a poWer-sWitching instruction from the executed instructions; and a poWer controller con?gured to control an on/ off status of
the execution unit based on the poWer-sWitching instruc tion, said poWer controller comprising:
an identi?cation decoder con?gured to generate an iden ti?cation corresponding to one of the execution units from the poWer-sWitching instruction; and
a poWer manager con?gured to sWitch on/off the execu tion unit corresponding to the identi?cation, said identi?cation decoder comprising:
a poWer-on decoder con?gured to generate the iden ti?cation and a turn-on signal based on a poWer-on
instruction of the poWer-sWitching instruction; and a poWer-off decoder con?gured to generate the iden
ti?cation and a turn-off signal based on a poWer-off instruction of the poWer-sWitching instruction.
2. The processor employing a poWer managing mechanism of claim 1, further comprising:
a plurality of reservation tables each con?gured to store the instruction to be executed by one of the execution units.
US 7,398,410 B2 5
3. The processor employing a power managing mechanism of claim 2, Wherein the poWer-off decoder con?gures the turn-off signal to the poWer manager When the reservation table corresponding to the execution unit to be turned off is
empty.
4. The processor employing a poWer managing mechanism of claim 3, further comprising:
a decoder con?gured to decode the instructions identi?ed as regular instructions from the precoder to generate
operation signals; and
a dispatcher con?gured to convey the operation signals into the reservation table.
5. The processor employing a poWer managing mechanism of claim 2, Wherein the reservation tables comprise an integer reservation table, an address reservation table and a ?oating point reservation table.
6. The processor employing a poWer managing mechanism of claim 5, Wherein the execution unit comprises:
at least one arithmetic-logic execution unit coupled to the
integer reservation table;
a load/ store execution unit coupled to the address reserva tion table; and
a ?oating point execution unit coupled to the ?oating point reservation table.
7. The processor employing a poWer managing mechanism of claim 1, Wherein the execution unit includes a transistor, Which turns off the execution unit When receiving a tum-off signal from the poWer manager.
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8. A method of saving poWer for a processor employing a
poWer managing mechanism, the method comprising steps
of:receiving an instruction;
checking if the instruction is a poWer-sWitching instruc
tion;
checking if the poWer-sWitching instruction is a poWer-off
instruction;
generating at least one identi?cation and a control signal, Wherein each identi?cation corresponds to an execution
unit;
checking if a reservation table for the execution unit cor responding to the identi?cation is empty on a condition that the poWer-sWitching instruction is a poWer-off instruction; and
sWitching on/off status of the execution unit according to the control signal.
9. The method of saving poWer for a processor employing a poWer managing mechanism of claim 8, Wherein the control signal includes a tum-off signal and a tum-on signal.
10. The method of saving poWer for a processor employing a poWer managing mechanism of claim 9, Wherein the turn off signal is generated When the reservation table for the execution unit corresponding to the identi?cation is empty.
11. The method of saving poWer for a processor employing a poWer managing mechanism of claim 9, Wherein the turn off signal is executed When the reservation table for the execu tion unit corresponding to the identi?cation is empty.
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