IA-32 Intel ® Architecture Software Developer’s Manual
Volume 1:
Basic Architecture
NOTE: The IA-32 Intel Architecture Software Developer’s Manual consists of four volumes: Basic Architecture, Order Number 253665;
Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; and the System Programming Guide, Order Number 253668. Refer to all four volumes when evaluating your design needs.
Order Number: 253665-017 September 2005
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Improper use of reserved or undefined features or instructions may cause unpredictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use.
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Copyright © 1997-2005 Intel Corporation
Vol. 1 iii
CONTENTS
PAGE CHAPTER 1
ABOUT THIS MANUAL
1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . 1-1 1.2 OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE. . . 1-1 1.3 NOTATIONAL CONVENTIONS . . . 1-3 1.3.1 Bit and Byte Order . . . .1-3 1.3.2 Reserved Bits and Software Compatibility . . . .1-4 1.3.3 Instruction Operands . . . .1-4 1.3.4 Hexadecimal and Binary Numbers . . . .1-5 1.3.5 Segmented Addressing . . . .1-5 1.3.6 A New Syntax for CPUID, CR, and MSR Values . . . .1-6 1.3.7 Exceptions . . . .1-7 1.4 RELATED LITERATURE . . . 1-8 CHAPTER 2
IA-32 INTEL® ARCHITECTURE
2.1 BRIEF HISTORY OF THE IA-32 ARCHITECTURE. . . 2-1 2.1.1 16-bit Processors and Segmentation (1978) . . . .2-1 2.1.2 The Intel® 286 Processor (1982). . . .2-2 2.1.3 The Intel386™ Processor (1985) . . . .2-2 2.1.4 The Intel486™ Processor (1989) . . . .2-2 2.1.5 The Intel® Pentium® Processor (1993) . . . .2-3 2.1.6 The P6 Family of Processors (1995-1999) . . . .2-3 2.1.7 The Intel Pentium 4 Processor Family (2000-2005) . . . .2-4 2.1.8 The Intel® Xeon Processor (2001-2005) . . . .2-4 2.1.9 The Intel® Pentium® M Processor (2003-2005) . . . .2-5 2.1.10 The Intel Pentium Processor Extreme Edition (2005) . . . .2-5 2.2 MORE ON SPECIFIC ADVANCES . . . 2-6 2.2.1 P6 Family Microarchitecture . . . .2-6 2.2.2 Intel NetBurst® Microarchitecture . . . .2-7 2.2.2.1 The Front End Pipeline . . . .2-9 2.2.2.2 Out-Of-Order Execution Core . . . .2-10 2.2.2.3 Retirement Unit. . . .2-10 2.2.3 SIMD Instructions . . . .2-11 2.2.4 Hyper-Threading Technology . . . .2-13 2.2.4.1 Some Implementation Notes . . . .2-14 2.2.5 Dual-Core Technology. . . .2-15 2.2.6 Intel® Extended Memory 64 Technology. . . .2-15 2.3 IA-32 PROCESSOR GENERATIONS . . . 2-16 CHAPTER 3
BASIC EXECUTION ENVIRONMENT
3.1 MODES OF OPERATION . . . 3-1 3.1.1 IA-32e Mode . . . .3-2 3.2 OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT . . . 3-3 3.2.1 64-Bit Mode Execution Environment . . . .3-6 3.3 MEMORY ORGANIZATION. . . 3-8 3.3.1 Three Memory Models. . . .3-8
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PAGE 3.3.2 Paging and Virtual Memory . . . .3-9 3.3.3 Memory Organization in 64-Bit Mode . . . .3-10 3.3.4 Modes of Operation vs. Memory Model. . . .3-10 3.3.5 32-Bit and 16-Bit Address and Operand Sizes . . . .3-11 3.3.6 Extended Physical Addressing in Protected Mode . . . .3-11 3.3.7 Address Calculations in 64-Bit Mode. . . .3-12 3.3.7.1 Canonical Addressing. . . .3-12 3.4 BASIC PROGRAM EXECUTION REGISTERS . . . 3-13 3.4.1 General-Purpose Registers . . . .3-13 3.4.1.1 General-Purpose Registers in 64-Bit Mode . . . .3-15 3.4.2 Segment Registers . . . .3-16 3.4.2.1 Segment Registers in 64-Bit Mode . . . .3-19 3.4.3 EFLAGS Register . . . .3-20 3.4.3.1 Status Flags . . . .3-21 3.4.3.2 DF Flag. . . .3-22 3.4.3.3 System Flags and IOPL Field . . . .3-23 3.4.3.4 RFLAGS Register in 64-Bit Mode. . . .3-23 3.5 INSTRUCTION POINTER . . . 3-24 3.5.1 Instruction Pointer in 64-Bit Mode . . . .3-24 3.6 OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES. . . 3-24 3.6.1 Operand Size and Address Size in 64-Bit Mode . . . .3-25 3.7 OPERAND ADDRESSING. . . 3-26 3.7.1 Immediate Operands . . . .3-26 3.7.2 Register Operands . . . .3-27 3.7.2.1 Register Operands in 64-Bit Mode . . . .3-28 3.7.3 Memory Operands. . . .3-28 3.7.3.1 Memory Operands in 64-Bit Mode . . . .3-29 3.7.4 Specifying a Segment Selector . . . .3-29 3.7.4.1 Segmentation in 64-Bit Mode . . . .3-30 3.7.5 Specifying an Offset . . . .3-30 3.7.5.1 Specifying an Offset in 64-Bit Mode . . . .3-32 3.7.6 Assembler and Compiler Addressing Modes . . . .3-33 3.7.7 I/O Port Addressing . . . .3-33 CHAPTER 4
DATA TYPES
4.1 FUNDAMENTAL DATA TYPES . . . 4-1 4.1.1 Alignment of Words, Doublewords, Quadwords, and Double Quadwords . . . .4-2 4.2 NUMERIC DATA TYPES . . . 4-3 4.2.1 Integers . . . .4-4 4.2.1.1 Unsigned Integers. . . .4-4 4.2.1.2 Signed Integers. . . .4-4 4.2.2 Floating-Point Data Types . . . .4-5 4.3 POINTER DATA TYPES . . . 4-7 4.3.1 Pointer Data Types in 64-Bit Mode . . . .4-7 4.4 BIT FIELD DATA TYPE . . . 4-8 4.5 STRING DATA TYPES . . . 4-8 4.6 PACKED SIMD DATA TYPES . . . 4-8 4.6.1 64-Bit SIMD Packed Data Types. . . .4-9 4.6.2 128-Bit Packed SIMD Data Types. . . .4-9 4.7 BCD AND PACKED BCD INTEGERS . . . 4-11 4.8 REAL NUMBERS AND FLOATING-POINT FORMATS. . . 4-12
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PAGE 4.8.1 Real Number System. . . 4-13 4.8.2 Floating-Point Format . . . 4-13 4.8.2.1 Normalized Numbers . . . 4-15 4.8.2.2 Biased Exponent. . . 4-15 4.8.3 Real Number and Non-number Encodings . . . 4-15 4.8.3.1 Signed Zeros. . . 4-17 4.8.3.2 Normalized and Denormalized Finite Numbers . . . 4-17 4.8.3.3 Signed Infinities. . . 4-18 4.8.3.4 NaNs . . . 4-18 4.8.3.5 Operating on SNaNs and QNaNs . . . 4-19 4.8.3.6 Using SNaNs and QNaNs in Applications . . . 4-20 4.8.3.7 QNaN Floating-Point Indefinite . . . 4-20 4.8.4 Rounding . . . 4-20 4.8.4.1 Rounding Control (RC) Fields . . . 4-22 4.8.4.2 Truncation with SSE and SSE2 Conversion Instructions . . . 4-22 4.9 OVERVIEW OF FLOATING-POINT EXCEPTIONS . . . 4-22 4.9.1 Floating-Point Exception Conditions . . . 4-24 4.9.1.1 Invalid Operation Exception (#I) . . . 4-24 4.9.1.2 Denormal Operand Exception (#D). . . 4-24 4.9.1.3 Divide-By-Zero Exception (#Z) . . . 4-25 4.9.1.4 Numeric Overflow Exception (#O) . . . 4-25 4.9.1.5 Numeric Underflow Exception (#U). . . 4-26 4.9.1.6 Inexact-Result (Precision) Exception (#P) . . . 4-27 4.9.2 Floating-Point Exception Priority . . . 4-28 4.9.3 Typical Actions of a Floating-Point Exception Handler . . . 4-29 CHAPTER 5
INSTRUCTION SET SUMMARY
5.1 GENERAL-PURPOSE INSTRUCTIONS . . . 5-2 5.1.1 Data Transfer Instructions . . . 5-2 5.1.2 Binary Arithmetic Instructions . . . 5-3 5.1.3 Decimal Arithmetic Instructions . . . 5-4 5.1.4 Logical Instructions . . . 5-4 5.1.5 Shift and Rotate Instructions . . . 5-5 5.1.6 Bit and Byte Instructions . . . 5-5 5.1.7 Control Transfer Instructions . . . 5-6 5.1.8 String Instructions . . . 5-7 5.1.9 I/O Instructions. . . 5-8 5.1.10 Enter and Leave Instructions . . . 5-8 5.1.11 Flag Control (EFLAG) Instructions. . . 5-8 5.1.12 Segment Register Instructions. . . 5-9 5.1.13 Miscellaneous Instructions. . . 5-9 5.2 X87 FPU INSTRUCTIONS . . . 5-9 5.2.1 x87 FPU Data Transfer Instructions . . . 5-10 5.2.2 x87 FPU Basic Arithmetic Instructions. . . 5-10 5.2.3 x87 FPU Comparison Instructions . . . 5-11 5.2.4 x87 FPU Transcendental Instructions . . . 5-12 5.2.5 x87 FPU Load Constants Instructions . . . 5-12 5.2.6 x87 FPU Control Instructions. . . 5-13 5.3 X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS . . . 5-13 5.4 MMX™ INSTRUCTIONS . . . 5-14 5.4.1 MMX Data Transfer Instructions . . . 5-14
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PAGE 5.4.2 MMX Conversion Instructions . . . .5-14 5.4.3 MMX Packed Arithmetic Instructions. . . .5-15 5.4.4 MMX Comparison Instructions . . . .5-15 5.4.5 MMX Logical Instructions . . . .5-16 5.4.6 MMX Shift and Rotate Instructions . . . .5-16 5.4.7 MMX State Management Instructions . . . .5-16 5.5 SSE INSTRUCTIONS . . . 5-17 5.5.1 SSE SIMD Single-Precision Floating-Point Instructions . . . .5-17 5.5.1.1 SSE Data Transfer Instructions . . . .5-17 5.5.1.2 SSE Packed Arithmetic Instructions . . . .5-18 5.5.1.3 SSE Comparison Instructions. . . .5-19 5.5.1.4 SSE Logical Instructions. . . .5-19 5.5.1.5 SSE Shuffle and Unpack Instructions. . . .5-19 5.5.1.6 SSE Conversion Instructions . . . .5-19 5.5.2 SSE MXCSR State Management Instructions. . . .5-20 5.5.3 SSE 64-Bit SIMD Integer Instructions . . . .5-20 5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions. . . . .5-21 5.6 SSE2 INSTRUCTIONS . . . 5-21 5.6.1 SSE2 Packed and Scalar Double-Precision Floating-Point Instructions . . . .5-22 5.6.1.1 SSE2 Data Movement Instructions. . . .5-22 5.6.1.2 SSE2 Packed Arithmetic Instructions . . . .5-22 5.6.1.3 SSE2 Logical Instructions. . . .5-23 5.6.1.4 SSE2 Compare Instructions . . . .5-23 5.6.1.5 SSE2 Shuffle and Unpack Instructions. . . .5-23 5.6.1.6 SSE2 Conversion Instructions . . . .5-24 5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions. . . .5-25 5.6.3 SSE2 128-Bit SIMD Integer Instructions . . . .5-25 5.6.4 SSE2 Cacheability Control and Ordering Instructions. . . .5-26 5.7 SSE3 INSTRUCTIONS . . . 5-26 5.7.1 SSE3 x87-FP Integer Conversion Instruction . . . .5-27 5.7.2 SSE3 Specialized 128-bit Unaligned Data Load Instruction . . . .5-27 5.7.3 SSE3 SIMD Floating-Point Packed ADD/SUB Instructions. . . .5-27 5.7.4 SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions. . . .5-27 5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions . . . .5-28 5.7.6 SSE3 Agent Synchronization Instructions . . . .5-28 5.8 SYSTEM INSTRUCTIONS. . . 5-28 5.9 64-BIT MODE INSTRUCTIONS. . . 5-29 CHAPTER 6
PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS
6.1 PROCEDURE CALL TYPES . . . 6-1 6.2 STACKS . . . 6-1 6.2.1 Setting Up a Stack. . . .6-2 6.2.2 Stack Alignment. . . .6-3 6.2.3 Address-Size Attributes for Stack Accesses . . . .6-3 6.2.4 Procedure Linking Information. . . .6-3 6.2.4.1 Stack-Frame Base Pointer . . . .6-4 6.2.4.2 Return Instruction Pointer . . . .6-4 6.2.5 Stack Behavior in 64-Bit Mode . . . .6-4 6.3 CALLING PROCEDURES USING CALL AND RET . . . 6-5 6.3.1 Near CALL and RET Operation. . . .6-5 6.3.2 Far CALL and RET Operation . . . .6-5
Vol. 1 vii CONTENTS
PAGE 6.3.3 Parameter Passing . . . 6-7 6.3.3.1 Passing Parameters Through the General-Purpose Registers. . . 6-7 6.3.3.2 Passing Parameters on the Stack. . . 6-7 6.3.3.3 Passing Parameters in an Argument List . . . 6-7 6.3.4 Saving Procedure State Information . . . 6-7 6.3.5 Calls to Other Privilege Levels. . . 6-8 6.3.6 CALL and RET Operation Between Privilege Levels. . . 6-9 6.3.7 Branch Functions in 64-Bit Mode. . . 6-11 6.4 INTERRUPTS AND EXCEPTIONS . . . 6-12 6.4.1 Call and Return Operation for Interrupt or Exception Handling Procedures . . . 6-13 6.4.2 Calls to Interrupt or Exception Handler Tasks . . . 6-17 6.4.3 Interrupt and Exception Handling in Real-Address Mode . . . 6-17 6.4.4 INT n, INTO, INT 3, and BOUND Instructions . . . 6-17 6.4.5 Handling Floating-Point Exceptions. . . 6-18 6.4.6 Interrupt and Exception Behavior in 64-Bit Mode . . . 6-18 6.5 PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES . . . 6-19 6.5.1 ENTER Instruction . . . 6-19 6.5.2 LEAVE Instruction . . . 6-26 CHAPTER 7
PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS
7.1 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS . . . 7-1
7.2 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE . . 7-2
7.3 SUMMARY OF GP INSTRUCTIONS . . . 7-3 7.3.1. Data Transfer Instructions . . . 7-3 7.3.1.1 General Data Movement Instructions . . . 7-4 7.3.1.2 Exchange Instructions . . . 7-5 7.3.1.3 Exchange Instructions in 64-Bit Mode . . . 7-7 7.3.1.4 Stack Manipulation Instructions . . . 7-7 7.3.1.5 Stack Manipulation Instructions in 64-Bit Mode . . . 7-9 7.3.1.6 Type Conversion Instructions . . . 7-9 7.3.1.7 Type Conversion Instructions in 64-Bit Mode . . . 7-10 7.3.2. Binary Arithmetic Instructions . . . 7-10 7.3.2.1 Addition and Subtraction Instructions . . . 7-10 7.3.2.2 Increment and Decrement Instructions . . . 7-11 7.3.2.3 Increment and Decrement Instructions in 64-Bit Mode. . . 7-11 7.3.2.4 Comparison and Sign Change Instruction . . . 7-11 7.3.2.5 Multiplication and Divide Instructions . . . 7-11 7.3.3. Decimal Arithmetic Instructions . . . 7-12 7.3.3.1 Packed BCD Adjustment Instructions . . . 7-12 7.3.3.2 Unpacked BCD Adjustment Instructions. . . 7-13 7.3.4. Decimal Arithmetic Instructions in 64-Bit Mode . . . 7-13 7.3.5. Logical Instructions . . . 7-13 7.3.6. Shift and Rotate Instructions . . . 7-14 7.3.6.1 Shift Instructions . . . 7-14 7.3.6.2 Double-Shift Instructions. . . 7-16 7.3.6.3 Rotate Instructions . . . 7-17 7.3.7. Bit and Byte Instructions . . . 7-19 7.3.7.1 Bit Test and Modify Instructions . . . 7-19 7.3.7.2 Bit Scan Instructions . . . 7-19 7.3.7.3 Byte Set on Condition Instructions . . . 7-19 7.3.7.4 Test Instruction . . . 7-20
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PAGE 7.3.8. Control Transfer Instructions . . . .7-20 7.3.8.1 Unconditional Transfer Instructions . . . .7-20 7.3.8.2 Conditional Transfer Instructions . . . .7-21 7.3.8.3 Control Transfer Instructions in 64-Bit Mode . . . .7-24 7.3.8.4 Software Interrupt Instructions . . . .7-24 7.3.8.5 Software Interrupt Instructions in 64-bit Mode and Compatibility Mode . . . . .7-25 7.3.9. String Operations. . . .7-25 7.3.9.1 Repeating String Operations . . . .7-26 7.3.10. String Operations in 64-Bit Mode . . . .7-27 7.3.10.1 Repeating String Operations in 64-bit Mode. . . .7-27 7.3.11. I/O Instructions . . . .7-27 7.3.12. I/O Instructions in 64-Bit Mode . . . .7-28 7.3.13. Enter and Leave Instructions. . . .7-28 7.3.14. Flag Control (EFLAG) Instructions . . . .7-28 7.3.14.1 Carry and Direction Flag Instructions . . . .7-28 7.3.14.2 EFLAGS Transfer Instructions . . . .7-29 7.3.14.3 Interrupt Flag Instructions . . . .7-29 7.3.15. Flag Control (RFLAG) Instructions in 64-Bit Mode . . . .7-30 7.3.16. Segment Register Instructions . . . .7-30 7.3.16.1 Segment-Register Load and Store Instructions . . . .7-30 7.3.16.2 Far Control Transfer Instructions . . . .7-30 7.3.16.3 Software Interrupt Instructions . . . .7-31 7.3.16.4 Load Far Pointer Instructions . . . .7-31 7.3.17. Miscellaneous Instructions . . . .7-31 7.3.17.1 Address Computation Instruction . . . .7-31 7.3.17.2 Table Lookup Instructions. . . .7-32 7.3.17.3 Processor Identification Instruction. . . .7-32 7.3.17.4 No-Operation and Undefined Instructions . . . .7-32 CHAPTER 8
PROGRAMMING WITH THE X87 FPU
8.1 X87 FPU EXECUTION ENVIRONMENT . . . 8-1 8.1.1 x87 FPU in 64-Bit Mode and Compatibility Mode . . . .8-2 8.1.2 x87 FPU Data Registers . . . .8-2 8.1.2.1 Parameter Passing With the x87 FPU Register Stack . . . .8-5 8.1.3 x87 FPU Status Register . . . .8-6 8.1.3.1 Top of Stack (TOP) Pointer . . . .8-6 8.1.3.2 Condition Code Flags . . . .8-6 8.1.3.3 x87 FPU Floating-Point Exception Flags . . . .8-7 8.1.3.4 Stack Fault Flag . . . .8-8 8.1.4 Branching and Conditional Moves on Condition Codes . . . .8-9 8.1.5 x87 FPU Control Word . . . .8-10 8.1.5.1 x87 FPU Floating-Point Exception Mask Bits . . . .8-11 8.1.5.2 Precision Control Field . . . .8-11 8.1.5.3 Rounding Control Field . . . .8-11 8.1.6 Infinity Control Flag . . . .8-12 8.1.7 x87 FPU Tag Word . . . .8-12 8.1.8 x87 FPU Instruction and Data (Operand) Pointers . . . .8-13 8.1.9 Last Instruction Opcode. . . .8-13 8.1.9.1 Fopcode Compatibility Sub-mode. . . .8-14 8.1.10 Saving the x87 FPU’s State with FSTENV/FNSTENV and FSAVE/FNSAVE . . .8-14 8.1.11 Saving the x87 FPU’s State with FXSAVE . . . .8-16
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PAGE 8.2 X87 FPU DATA TYPES . . . 8-16 8.2.1 Indefinites . . . 8-18 8.2.2 Unsupported Double Extended-Precision
Floating-Point Encodings and Pseudo-Denormals . . . 8-18 8.3 X86 FPU INSTRUCTION SET . . . 8-20 8.3.1 Escape (ESC) Instructions. . . 8-20 8.3.2 x87 FPU Instruction Operands . . . 8-20 8.3.3 Data Transfer Instructions . . . 8-21 8.3.4 Load Constant Instructions . . . 8-22 8.3.5 Basic Arithmetic Instructions . . . 8-23 8.3.6 Comparison and Classification Instructions . . . 8-24 8.3.6.1 Branching on the x87 FPU Condition Codes . . . 8-26 8.3.7 Trigonometric Instructions . . . 8-27 8.3.8 Pi . . . 8-27 8.3.9 Logarithmic, Exponential, and Scale . . . 8-29 8.3.10 Transcendental Instruction Accuracy. . . 8-29 8.3.11 x87 FPU Control Instructions. . . 8-30 8.3.12 Waiting vs. Non-waiting Instructions . . . 8-31 8.3.13 Unsupported x87 FPU Instructions . . . 8-31 8.4 X87 FPU FLOATING-POINT EXCEPTION HANDLING. . . 8-31 8.4.1 Arithmetic vs. Non-arithmetic Instructions . . . 8-32 8.5 X87 FPU FLOATING-POINT EXCEPTION CONDITIONS. . . 8-34 8.5.1 Invalid Operation Exception. . . 8-34 8.5.1.1 Stack Overflow or Underflow Exception (#IS). . . 8-34 8.5.1.2 Invalid Arithmetic Operand Exception (#IA) . . . 8-35 8.5.2 Denormal Operand Exception (#D) . . . 8-37 8.5.3 Divide-By-Zero Exception (#Z) . . . 8-37 8.5.4 Numeric Overflow Exception (#O) . . . 8-38 8.5.5 Numeric Underflow Exception (#U) . . . 8-39 8.5.6 Inexact-Result (Precision) Exception (#P) . . . 8-40 8.6 X87 FPU EXCEPTION SYNCHRONIZATION . . . 8-41 8.7 HANDLING X87 FPU EXCEPTIONS IN SOFTWARE . . . 8-42 8.7.1 Native Mode. . . 8-42 8.7.2 MS-DOS* Compatibility Sub-mode . . . 8-43 8.7.3 Handling x87 FPU Exceptions in Software . . . 8-44 CHAPTER 9
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.1 OVERVIEW OF MMX TECHNOLOGY. . . 9-1 9.2 THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT . . . 9-2 9.2.1 MMX Technology in 64-Bit Mode and Compatibility Mode . . . 9-2 9.2.2 MMX Registers . . . 9-3 9.2.3 MMX Data Types . . . 9-4 9.2.4 Memory Data Formats . . . 9-4 9.2.5 Single Instruction, Multiple Data (SIMD) Execution Model . . . 9-4 9.3 SATURATION AND WRAPAROUND MODES . . . 9-5 9.4 MMX INSTRUCTIONS . . . 9-6 9.4.1 Data Transfer Instructions . . . 9-8 9.4.2 Arithmetic Instructions . . . 9-8 9.4.3 Comparison Instructions . . . 9-8 9.4.4 Conversion Instructions . . . 9-9 9.4.5 Unpack Instructions . . . 9-9
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PAGE 9.4.6 Logical Instructions . . . .9-9 9.4.7 Shift Instructions . . . .9-9 9.4.8 EMMS Instruction . . . .9-10 9.5 COMPATIBILITY WITH X87 FPU ARCHITECTURE . . . 9-10 9.5.1 MMX Instructions and the x87 FPU Tag Word . . . .9-10 9.6 WRITING APPLICATIONS WITH MMX CODE . . . 9-10 9.6.1 Checking for MMX Technology Support . . . .9-10 9.6.2 Transitions Between x87 FPU and MMX Code . . . .9-11 9.6.3 Using the EMMS Instruction . . . .9-12 9.6.4 Mixing MMX and x87 FPU Instructions . . . .9-12 9.6.5 Interfacing with MMX Code . . . .9-13 9.6.6 Using MMX Code in a Multitasking Operating System Environment. . . .9-13 9.6.7 Exception Handling in MMX Code. . . .9-14 9.6.8 Register Mapping . . . .9-14 9.6.9 Effect of Instruction Prefixes on MMX Instructions . . . .9-14 CHAPTER 10
PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
10.1 OVERVIEW OF SSE EXTENSIONS . . . 10-1 10.2 SSE PROGRAMMING ENVIRONMENT . . . 10-3 10.2.1 SSE in 64-Bit Mode and Compatibility Mode. . . .10-4 10.2.2 XMM Registers . . . .10-4 10.2.3 MXCSR Control and Status Register . . . .10-5 10.2.3.1 SIMD Floating-Point Mask and Flag Bits . . . .10-6 10.2.3.2 SIMD Floating-Point Rounding Control Field . . . .10-6 10.2.3.3 Flush-To-Zero . . . .10-6 10.2.3.4 Denormals-Are-Zeros . . . .10-7 10.2.4 Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU . . . .10-7 10.3 SSE DATA TYPES. . . 10-8 10.4 SSE INSTRUCTION SET. . . 10-8 10.4.1 SSE Packed and Scalar Floating-Point Instructions . . . .10-9 10.4.1.1 SSE Data Movement Instructions. . . .10-10 10.4.1.2 SSE Arithmetic Instructions . . . .10-11 10.4.2 SSE Logical Instructions . . . .10-12 10.4.2.1 SSE Comparison Instructions. . . .10-13 10.4.2.2 SSE Shuffle and Unpack Instructions. . . .10-13 10.4.3 SSE Conversion Instructions. . . .10-15 10.4.4 SSE 64-Bit SIMD Integer Instructions . . . .10-16 10.4.5 MXCSR State Management Instructions. . . .10-17 10.4.6 Cacheability Control, Prefetch, and Memory Ordering Instructions. . . .10-17 10.4.6.1 Cacheability Control Instructions . . . .10-17 10.4.6.2 Caching of Temporal vs. Non-Temporal Data . . . .10-18 10.4.6.3 PREFETCHh Instructions . . . .10-19 10.4.6.4 SFENCE Instruction . . . .10-19 10.5 FXSAVE AND FXRSTOR INSTRUCTIONS . . . 10-20 10.6 HANDLING SSE INSTRUCTION EXCEPTIONS. . . 10-20 10.7 WRITING APPLICATIONS WITH THE SSE EXTENSIONS . . . 10-20 CHAPTER 11
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
11.1 OVERVIEW OF SSE2 EXTENSIONS . . . 11-1 11.2 SSE2 PROGRAMMING ENVIRONMENT . . . 11-3
Vol. 1 xi CONTENTS
PAGE 11.2.1 SSE2 in 64-Bit Mode and Compatibility Mode. . . 11-4 11.2.2 Compatibility of SSE2 Extensions with SSE, MMX
Technology and x87 FPU Programming Environment. . . 11-4 11.2.3 Denormals-Are-Zeros Flag . . . 11-4 11.3 SSE2 DATA TYPES . . . 11-5 11.4 SSE2 INSTRUCTIONS . . . 11-6 11.4.1 Packed and Scalar Double-Precision Floating-Point Instructions . . . 11-6 11.4.1.1 Data Movement Instructions . . . 11-8 11.4.1.2 SSE2 Arithmetic Instructions . . . 11-8 11.4.1.3 SSE2 Logical Instructions . . . 11-9 11.4.1.4 SSE2 Comparison Instructions . . . 11-10 11.4.1.5 SSE2 Shuffle and Unpack Instructions . . . 11-10 11.4.1.6 SSE2 Conversion Instructions . . . 11-12 11.4.2 SSE2 64-Bit and 128-Bit SIMD Integer Instructions . . . 11-15 11.4.3 128-Bit SIMD Integer Instruction Extensions . . . 11-16 11.4.4 Cacheability Control and Memory Ordering Instructions . . . 11-16 11.4.4.1 FLUSH Cache Line . . . 11-16 11.4.4.2 Cacheability Control Instructions . . . 11-17 11.4.4.3 Memory Ordering Instructions. . . 11-17 11.4.4.4 Pause . . . 11-17 11.4.5 Branch Hints . . . 11-18 11.5 SSE, SSE2, AND SSE3 EXCEPTIONS . . . 11-18 11.5.1 SIMD Floating-Point Exceptions . . . 11-18 11.5.2 SIMD Floating-Point Exception Conditions . . . 11-19 11.5.2.1 Invalid Operation Exception (#I) . . . 11-19 11.5.2.2 Denormal-Operand Exception (#D) . . . 11-21 11.5.2.3 Divide-By-Zero Exception (#Z) . . . 11-21 11.5.2.4 Numeric Overflow Exception (#O) . . . 11-21 11.5.2.5 Numeric Underflow Exception (#U). . . 11-22 11.5.2.6 Inexact-Result (Precision) Exception (#P) . . . 11-22 11.5.3 Generating SIMD Floating-Point Exceptions . . . 11-23 11.5.3.1 Handling Masked Exceptions . . . 11-23 11.5.3.2 Handling Unmasked Exceptions . . . 11-24 11.5.3.3 Handling Combinations of Masked and Unmasked Exceptions . . . 11-25 11.5.4 Handling SIMD Floating-Point Exceptions in Software . . . 11-25 11.5.5 Interaction of SIMD and x87 FPU Floating-Point Exceptions . . . 11-25 11.6 WRITING APPLICATIONS WITH SSE/SSE2 EXTENSIONS . . . 11-26 11.6.1 General Guidelines for Using SSE/SSE2 Extensions . . . 11-27 11.6.2 Checking for SSE/SSE2 Support. . . 11-27 11.6.3 Checking for the DAZ Flag in the MXCSR Register . . . 11-28 11.6.4 Initialization of SSE/SE2 Extensions . . . 11-28 11.6.5 Saving and Restoring the SSE/SSE2 State. . . 11-29 11.6.6 Guidelines for Writing to the MXCSR Register . . . 11-30 11.6.7 Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions . . 11-31 11.6.8 Compatibility of SIMD and x87 FPU Floating-Point Data Types . . . 11-31 11.6.9 Mixing Packed and Scalar Floating-Point and
128-Bit SIMD Integer Instructions and Data . . . 11-32 11.6.10 Interfacing with SSE/SSE2 Procedures and Functions . . . 11-33 11.6.10.1 Passing Parameters in XMM Registers . . . 11-33 11.6.10.2 Saving XMM Register State on a Procedure or Function Call . . . 11-33 11.6.10.3 Caller-Save Requirement for Procedure and Function Calls . . . 11-34
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xii Vol. 1
PAGE 11.6.11 Updating Existing MMX Technology Routines
Using 128-Bit SIMD Integer Instructions . . . .11-34 11.6.12 Branching on Arithmetic Operations . . . .11-35 11.6.13 Cacheability Hint Instructions . . . .11-35 11.6.14 Effect of Instruction Prefixes on the SSE/SSE2 Instructions . . . .11-36 CHAPTER 12
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 3 (SSE3)
12.1 OVERVIEW OF SSE3 INSTRUCTIONS . . . 12-1 12.2 SSE3 PROGRAMMING ENVIRONMENT AND DATA TYPES . . . 12-1 12.2.1 SSE3 in 64-Bit Mode and Compatibility Mode. . . .12-2 12.2.2 Compatibility of SSE3 Extensions with MMX Technology, the x87
FPU Environment, and SSE/SSE2 Extensions . . . .12-2 12.2.3 Horizontal and Asymmetric Processing. . . .12-2 12.3 SSE3 INSTRUCTIONS . . . 12-3 12.3.1 x87 FPU Instruction for Integer Conversion . . . .12-3 12.3.2 SIMD Integer Instruction for Specialized 128-bit Unaligned Data Load . . . .12-4 12.3.3 SIMD Floating-Point Instructions That Enhance LOAD/MOVE/DUPLICATE
Performance . . . .12-4 12.3.4 SIMD Floating-Point Instructions Provide Packed Addition/Subtraction . . . .12-5 12.3.5 SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction . . . . .12-5 12.3.6 Two Thread Synchronization Instructions . . . .12-6 12.4 SSE3 EXCEPTIONS . . . 12-6 12.4.1 Device Not Available (DNA) Exceptions . . . .12-7 12.4.2 Numeric Error flag and IGNNE# . . . .12-7 12.4.3 Emulation. . . .12-7 12.5 WRITING APPLICATIONS WITH SSE3 EXTENSIONS . . . 12-7 12.5.1 General Guidelines for Using SSE3 Extensions . . . .12-7 12.5.2 Checking for SSE3 Support. . . .12-8 12.5.3 Enable FTZ and DAZ for SIMD Floating-Point Computation. . . .12-9 12.5.4 Programming SSE3 with SSE/SSE2 Extensions . . . .12-9 CHAPTER 13
INPUT/OUTPUT
13.1 I/O PORT ADDRESSING. . . 13-1 13.2 I/O PORT HARDWARE . . . 13-1 13.3 I/O ADDRESS SPACE . . . 13-2 13.3.1 Memory-Mapped I/O . . . .13-2 13.4 I/O INSTRUCTIONS. . . 13-3 13.5 PROTECTED-MODE I/O . . . 13-4 13.5.1 I/O Privilege Level . . . .13-4 13.5.2 I/O Permission Bit Map . . . .13-5 13.6 ORDERING I/O . . . 13-6 CHAPTER 14
PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
14.1 USING THE CPUID INSTRUCTION . . . 14-1 14.1.1 Notes on Where to Start . . . .14-1 14.1.2 Identification of Earlier IA-32 Processors . . . .14-2
Vol. 1 xiii CONTENTS
PAGE APPENDIX A
EFLAGS CROSS-REFERENCE
A.1 EFLAGS AND INSTRUCTIONS . . . A-1 APPENDIX B
EFLAGS CONDITION CODES
B.1 CONDITION CODES . . . B-1 APPENDIX C
FLOATING-POINT EXCEPTIONS SUMMARY
C.1 OVERVIEW . . . C-1 C.2 X87 FPU INSTRUCTIONS . . . C-2 C.3 SSE INSTRUCTIONS . . . C-4 C.4 SSE2 INSTRUCTIONS . . . C-6 C.5 SSE3 INSTRUCTIONS . . . C-10 APPENDIX D
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
D.1 ORIGIN OF THE MS-DOS COMPATIBILITY SUB-MODE
FOR HANDLING X87 FPU EXCEPTIONS. . . D-2
D.2 IMPLEMENTATION OF THE MS-DOS COMPATIBILITY
SUB-MODE IN THE INTEL486, PENTIUM, AND P6
PROCESSOR FAMILY, AND PENTIUM 4 PROCESSORS. . . D-3 D.2.1 MS-DOS Compatibility Sub-mode in the Intel486 and Pentium Processors . . . . D-3 D.2.1.1 Basic Rules: When FERR# Is Generated . . . D-4 D.2.1.2 Recommended External Hardware to Support the
MS-DOS Compatibility Sub-mode . . . D-5 D.2.1.3 No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window . . . D-7 D.2.2 MS-DOS Compatibility Sub-mode in the P6 Family
and Pentium 4 Processors. . . D-9
D.3 RECOMMENDED PROTOCOL FOR MS-DOS*
COMPATIBILITY HANDLERS . . . D-10 D.3.1 Floating-Point Exceptions and Their Defaults . . . D-11 D.3.2 Two Options for Handling Numeric Exceptions . . . D-11 D.3.2.1 Automatic Exception Handling: Using Masked Exceptions. . . D-11 D.3.2.2 Software Exception Handling . . . D-13 D.3.3 Synchronization Required for Use of x87 FPU Exception Handlers . . . D-14 D.3.3.1 Exception Synchronization: What, Why and When. . . D-14 D.3.3.2 Exception Synchronization Examples. . . D-16 D.3.3.3 Proper Exception Synchronization . . . D-16 D.3.4 x87 FPU Exception Handling Examples . . . D-17 D.3.5 Need for Storing State of IGNNE# Circuit
If Using x87 FPU and SMM . . . D-22 D.3.6 Considerations When x87 FPU Shared Between Tasks . . . D-23 D.3.6.1 Speculatively Deferring x87 FPU Saves, General Overview . . . D-23 D.3.6.2 Tracking x87 FPU Ownership . . . D-24 D.3.6.3 Interaction of x87 FPU State Saves and Floating-Point Exception
Association . . . D-25 D.3.6.4 Interrupt Routing From the Kernel . . . D-27 D.3.6.5 Special Considerations for Operating Systems that Support
Streaming SIMD Extensions . . . D-28
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xiv Vol. 1
PAGE D.4 DIFFERENCES FOR HANDLERS USING NATIVE MODE. . . D-28 D.4.1 Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387
Processors. . . D-29 D.4.2 Changes with Intel486, Pentium and Pentium Pro Processors with
CR0.NE[bit 5] = 1 . . . D-29 D.4.3 Considerations When x87 FPU Shared Between Tasks Using Native Mode . . D-30 APPENDIX E
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
E.1 TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS . . . E-1 E.2 SOFTWARE EXCEPTION HANDLING . . . E-1 E.3 EXCEPTION SYNCHRONIZATION. . . E-3 E.4 SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754 . . . E-4 E.4.1 Floating-Point Emulation . . . E-4 E.4.2 SSE/SSE2/SSE3 Response To Floating-Point Exceptions. . . E-6 E.4.2.1 Numeric Exceptions . . . E-7 E.4.2.2 Results of Operations with NaN Operands or a NaN Result for
SSE/SSE2/SSE3 Numeric Instructions . . . E-7 E.4.2.3 Condition Codes, Exception Flags, and Response for Masked
and Unmasked Numeric Exceptions. . . E-12 E.4.3 Example SIMD Floating-Point Emulation Implementation. . . E-19
FIGURES
Figure 1-1. Bit and Byte Order . . . .1-4 Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation . . . .1-7 Figure 2-1. The P6 Processor Microarchitecture with Advanced Transfer
Cache Enhancement . . . .2-6 Figure 2-2. The Intel NetBurst Microarchitecture . . . .2-9 Figure 2-3. SIMD Extensions, Register Layouts, and Data Types . . . .2-12 Figure 2-4. Comparison of an IA-32 Processor Supporting Hyper-Threading
Technology and a Traditional Dual Processor System. . . .2-13 Figure 2-5. IA-32 Processors that Support Dual-Core . . . .2-15 Figure 3-1. IA-32 Basic Execution Environment for Non-64-bit Modes. . . .3-4 Figure 3-2. 64-Bit Mode Execution Environment . . . .3-7 Figure 3-3. Three Memory Management Models . . . .3-9 Figure 3-4. General System and Application Programming Registers . . . .3-14 Figure 3-5. Alternate General-Purpose Register Names . . . .3-15 Figure 3-6. Use of Segment Registers for Flat Memory Model. . . .3-17 Figure 3-7. Use of Segment Registers in Segmented Memory Model . . . .3-18 Figure 3-8. EFLAGS Register . . . .3-21 Figure 3-9. Memory Operand Address . . . .3-28 Figure 3-10. Memory Operand Address in 64-Bit Mode . . . .3-29 Figure 3-11. Offset (or Effective Address) Computation . . . .3-31 Figure 4-1. Fundamental Data Types . . . .4-1 Figure 4-2. Bytes, Words, Doublewords, Quadwords, and Double Quadwords
in Memory . . . .4-2 Figure 4-3. Numeric Data Types . . . .4-3
Vol. 1 xv CONTENTS
PAGE Figure 4-4. Pointer Data Types . . . 4-7 Figure 4-5. Pointers in 64-Bit Mode. . . 4-8 Figure 4-6. Bit Field Data Type . . . 4-8 Figure 4-7. 64-Bit Packed SIMD Data Types . . . 4-9 Figure 4-8. 128-Bit Packed SIMD Data Types . . . 4-10 Figure 4-9. BCD Data Types . . . 4-11 Figure 4-10. Binary Real Number System. . . 4-14 Figure 4-11. Binary Floating-Point Format . . . 4-14 Figure 4-12. Real Numbers and NaNs . . . 4-16 Figure 6-1. Stack Structure . . . 6-2 Figure 6-2. Stack on Near and Far Calls. . . 6-6 Figure 6-3. Protection Rings . . . 6-8 Figure 6-4. Stack Switch on a Call to a Different Privilege Level . . . 6-10 Figure 6-5. Stack Usage on Transfers to Interrupt and Exception Handling Routines . . 6-15 Figure 6-6. Nested Procedures . . . 6-21 Figure 6-7. Stack Frame After Entering the MAIN Procedure . . . 6-22 Figure 6-8. Stack Frame After Entering Procedure A . . . 6-23 Figure 6-9. Stack Frame After Entering Procedure B . . . 6-24 Figure 6-10. Stack Frame After Entering Procedure C . . . 6-25 Figure 7-1. Operation of the PUSH Instruction . . . 7-7 Figure 7-2. Operation of the PUSHA Instruction . . . 7-8 Figure 7-3. Operation of the POP Instruction . . . 7-8 Figure 7-4. Operation of the POPA Instruction . . . 7-9 Figure 7-5. Sign Extension . . . 7-9 Figure 7-6. SHL/SAL Instruction Operation. . . 7-14 Figure 7-7. SHR Instruction Operation . . . 7-15 Figure 7-8. SAR Instruction Operation . . . 7-16 Figure 7-9. SHLD and SHRD Instruction Operations . . . 7-17 Figure 7-10. ROL, ROR, RCL, and RCR Instruction Operations. . . 7-18 Figure 7-11. Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD Instructions . 7-29 Figure 8-1. x87 FPU Execution Environment . . . 8-3 Figure 8-2. x87 FPU Data Register Stack . . . 8-4 Figure 8-3. Example x87 FPU Dot Product Computation . . . 8-5 Figure 8-4. x87 FPU Status Word . . . 8-6 Figure 8-5. Moving the Condition Codes to the EFLAGS Register . . . 8-9 Figure 8-6. x87 FPU Control Word . . . 8-10 Figure 8-7. x87 FPU Tag Word . . . 8-12 Figure 8-8. Contents of x87 FPU Opcode Registers. . . 8-14 Figure 8-9. Protected Mode x87 FPU State Image in Memory, 32-Bit Format . . . 8-15 Figure 8-10. Real Mode x87 FPU State Image in Memory, 32-Bit Format . . . 8-15 Figure 8-11. Protected Mode x87 FPU State Image in Memory, 16-Bit Format . . . 8-16 Figure 8-12. Real Mode x87 FPU State Image in Memory, 16-Bit Format . . . 8-16 Figure 8-13. x87 FPU Data Type Formats . . . 8-17 Figure 9-1. MMX Technology Execution Environment . . . 9-2 Figure 9-2. MMX Register Set. . . 9-3 Figure 9-3. Data Types Introduced with the MMX Technology . . . 9-4 Figure 9-4. SIMD Execution Model . . . 9-5 Figure 10-1. SSE Execution Environment. . . 10-3 Figure 10-2. XMM Registers . . . 10-4 Figure 10-3. MXCSR Control/Status Register. . . 10-5 Figure 10-4. 128-Bit Packed Single-Precision Floating-Point Data Type . . . 10-8 Figure 10-5. Packed Single-Precision Floating-Point Operation . . . 10-9
CONTENTS
xvi Vol. 1
PAGE Figure 10-6. Scalar Single-Precision Floating-Point Operation. . . .10-10 Figure 10-7. SHUFPS Instruction, Packed Shuffle Operation. . . .10-14 Figure 10-8. UNPCKHPS Instruction, High Unpack and Interleave Operation . . . .10-14 Figure 10-9. UNPCKLPS Instruction, Low Unpack and Interleave Operation . . . .10-15 Figure 11-1. Steaming SIMD Extensions 2 Execution Environment . . . .11-3 Figure 11-2. Data Types Introduced with the SSE2 Extensions . . . .11-5 Figure 11-3. Packed Double-Precision Floating-Point Operations . . . .11-7 Figure 11-4. Scalar Double-Precision Floating-Point Operations . . . .11-7 Figure 11-5. SHUFPD Instruction, Packed Shuffle Operation . . . .11-11 Figure 11-6. UNPCKHPD Instruction, High Unpack and Interleave Operation. . . .11-11 Figure 11-7. UNPCKLPD Instruction, Low Unpack and Interleave Operation . . . .11-12 Figure 11-8. SSE and SSE2 Conversion Instructions. . . .11-13 Figure 11-9. Example Masked Response for Packed Operations . . . .11-24 Figure 12-1. Asymmetric Processing in ADDSUBPD . . . .12-2 Figure 12-2. Horizontal Data Movement in ADDSUBPD . . . .12-3 Figure 13-1. Memory-Mapped I/O. . . .13-3 Figure 13-2. I/O Permission Bit Map . . . .13-5 Figure D-1. Recommended Circuit for MS-DOS* Compatibility x87 FPU
Exception Handling. . . D-6 Figure D-2. Behavior of Signals During x87 FPU Exception Handling . . . D-7 Figure D-3. Timing of Receipt of External Interrupt . . . D-8 Figure D-4. Arithmetic Example Using Infinity . . . D-12 Figure D-5. General Program Flow for DNA Exception Handler . . . D-26 Figure D-6. Program Flow for a Numeric Exception Dispatch Routine . . . D-26 Figure E-1. Control Flow for Handling Unmasked Floating-Point Exceptions . . . E-6
TABLES
Table 2-1. Key Features of Most Recent IA-32 Processors. . . .2-16 Table 2-2. Key Features of Previous Generations of IA-32 Processors . . . .2-19 Table 3-1. Instruction Pointer Sizes . . . .3-12 Table 3-2. Addressable General Purpose Registers . . . .3-16 Table 3-3. Effective Operand- and Address-Size Attributes . . . .3-25 Table 3-4. Effective Operand- and Address-Size Attributes in 64-Bit Mode . . . .3-26 Table 3-5. Default Segment Selection Rules . . . .3-29 Table 4-1. Signed Integer Encodings. . . .4-4 Table 4-2. Length, Precision, and Range of Floating-Point Data Types . . . .4-5 Table 4-3. Floating-Point Number and NaN Encodings. . . .4-6 Table 4-4. Packed Decimal Integer Encodings . . . .4-12 Table 4-5. Real and Floating-Point Number Notation . . . .4-15 Table 4-6. Denormalization Process . . . .4-17 Table 4-7. Rules for Handling NaNs . . . .4-19 Table 4-8. Rounding Modes and Encoding of Rounding Control (RC) Field . . . .4-21 Table 4-9. Numeric Overflow Thresholds . . . .4-25 Table 4-10. Masked Responses to Numeric Overflow. . . .4-26 Table 4-11. Numeric Underflow (Normalized) Thresholds. . . .4-26 Table 5-1. Instruction Groups and IA-32 Processors. . . .5-1 Table 6-1. Exceptions and Interrupts . . . .6-14 Table 7-1. Move Instruction Operations. . . .7-4
Vol. 1 xvii CONTENTS
PAGE Table 7-2. Conditional Move Instructions . . . 7-5 Table 7-3. Bit Test and Modify Instructions . . . 7-19 Table 7-4. Conditional Jump Instructions. . . 7-22 Table 8-1. Condition Code Interpretation . . . 8-8 Table 8-2. Precision Control Field (PC) . . . 8-11 Table 8-3. Unsupported Double Extended-Precision Floating-Point Encodings
and Pseudo-Denormals . . . 8-19 Table 8-4. Data Transfer Instructions. . . 8-21 Table 8-5. Floating-Point Conditional Move Instructions . . . 8-22 Table 8-6. Setting of x87 FPU Condition Code Flags for Floating-Point Number
Comparisons. . . 8-25 Table 8-7. Setting of EFLAGS Status Flags for Floating-Point Number Comparisons . 8-26 Table 8-8. TEST Instruction Constants for Conditional Branching. . . 8-26 Table 8-9. Arithmetic and Non-arithmetic Instructions . . . 8-32 Table 8-10. Invalid Arithmetic Operations and the Masked Responses to Them . . . 8-36 Table 8-11. Divide-By-Zero Conditions and the Masked Responses to Them . . . 8-37 Table 9-1. Data Range Limits for Saturation . . . 9-6 Table 9-2. MMX Instruction Set Summary . . . 9-7 Table 9-3. Effect of Prefixes on MMX Instructions . . . 9-14 Table 10-1. PREFETCHh Instructions Caching Hints . . . 10-19 Table 11-1. Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid
Arithmetic Operations . . . 11-20 Table 11-2. SSE and SSE2 State Following a Power-up/Reset or INIT . . . 11-29 Table 11-3. Effect of Prefixes on SSE, SSE2, and SSE3 Instructions. . . 11-37 Table 13-1. I/O Instruction Serialization . . . 13-7 Table A-1. Codes Describing Flags . . . A-1 Table A-2. EFLAGS Cross-Reference . . . A-1 Table B-1. EFLAGS Condition Codes . . . B-1 Table C-1. x87 FPU and SIMD Floating-Point Exceptions . . . C-1 Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions . . . C-2 Table C-3. Exceptions Generated with SSE Instructions . . . C-4 Table C-4. Exceptions Generated with SSE2 Instructions . . . C-6 Table C-5. Exceptions Generated with SSE3 Instructions . . . C-10 Table E-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS,
ADDPD, ADDSD, SUBPD, SUBSD, MULPD, MULSD, DIVPD, DIVSD,
ADDSUBPS, ADDSUBPD, HADDPS, HADDPD, HSUBPS, HSUBPD . . . E-8
Table E-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD,
CMPPD.EQ, CMPSD.EQ, CMPPD.ORD, CMPSD.ORD . . . E-8
Table E-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD,
CMPPD.NEQ, CMPSD.NEQ, CMPPD.UNORD, CMPSD.UNORD . . . E-9
Table E-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT,
CMPSD.LT, CMPPD.LE, CMPSD.LE . . . E-9
Table E-5. CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT,
CMPSD.NLT, CMPPD.NLE, CMPSD.NLE . . . E-9 Table E-6. COMISS, COMISD . . . E-10 Table E-7. UCOMISS, UCOMISD . . . E-10 Table E-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI,
CVTSD2SI, CVTTPD2PI, CVTTSD2SI, CVTPS2DQ, CVTTPS2DQ,
CVTPD2DQ, CVTTPD2DQ. . . E-10 Table E-9. MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSD . . . . E-10 Table E-10. SQRTPS, SQRTSS, SQRTPD, SQRTSD. . . E-11 Table E-11. CVTPS2PD, CVTSS2SD . . . E-11
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PAGE Table E-12. CVTPD2PS, CVTSD2SS . . . E-11 Table E-13. #I - Invalid Operations. . . E-12 Table E-14. #Z - Divide-by-Zero. . . E-14 Table E-15. #D - Denormal Operand . . . E-15 Table E-16. #O - Numeric Overflow . . . E-16 Table E-17. #U - Numeric Underflow . . . E-17 Table E-18. #P - Inexact Result (Precision) . . . E-18
1
About This Manual
Vol. 1 1-1 ABOUT THIS MANUAL
CHAPTER 1 ABOUT THIS MANUAL
The IA-32 Intel® Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 253665) is part of a set that describes the architecture and programming envi- ronment of IA-32 Intel architecture processors. Other volumes in this set are:
•
The IA-32 Intel Architecture Software Developer’s Manual, Volumes 2A & 2B: Instruction Set Reference (Order Numbers 253666 and 253667).•
The IA-32 Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 253668).The IA-32 Intel Architecture Software Developer’s Manual, Volume 1, describes the basic archi- tecture and programming environment of an IA-32 processor. The IA-32 Intel Architecture Soft- ware Developer’s Manual, Volumes 2A & 2B describe the instruction set of the processor and the opcode structure. These volumes target application programmers who are writing programs to run under existing operating systems or executives. The IA-32 Intel Architecture Software Developer’s Manual, Volume 3 describes the operating-system support environment of an IA-32 processor and IA-32 processor compatibility information. This volume is aimed at operating- system and BIOS designers.
1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL
This manual set includes information pertaining primarily to the most recent IA-32 processors, which include: Pentium® processors, P6 family processors, Pentium 4 processors, Pentium M processors, Intel® Xeon™ processors, the Pentium D processors, and the Pentium processor Extreme Editions.
P6 family processors are IA-32 processors based on the P6 family microarchitecture, which include the Pentium Pro, Pentium II, and Pentium III processors. The Pentium 4, Intel Xeon processors, the Pentium D processors, and the Pentium processor Extreme Editions are based on the Intel NetBurst® microarchitecture.
1.2 OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE
A description of this manual’s content follows:
Chapter 1 — About This Manual. Gives an overview of all three volumes of the IA-32 Intel Architecture Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hard- ware designers.
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Chapter 2 — IA-32 Intel® Architecture. Introduces the IA-32 architecture and the families of Intel processors that are based on this architecture. It also gives an overview of the common features found in these processors and brief history of the IA-32 architecture.
Chapter 3 — Basic Execution Environment. Introduces the models of memory organization and describes the register set used by applications.
Chapter 4 — Data Types. Describes the data types and addressing modes recognized by the processor; provides an overview of real numbers and floating-point formats and of floating- point exceptions.
Chapter 5 — Instruction Set Summary. Lists all IA-32 architecture instructions, divided into technology groups.
Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack and mechanisms provided for making procedure calls and for servicing interrupts and exceptions.
Chapter 7 — Programming with General-Purpose Instructions. Describes basic load and store, program control, arithmetic, and string instructions that operate on basic data types, general-purpose and segment registers; also describes system instructions that are executed in protected mode.
Chapter 8 — Programming with the x87 FPU. Describes the x87 floating-point unit (FPU), including floating-point registers and data types; gives an overview of the floating-point instruc- tion set and describes the processor's floating-point exception conditions.
Chapter 9 — Programming with Intel® MMX™ Technology. Describes Intel MMX tech- nology, including MMX registers and data types; also provides an overview of the MMX instruction set.
Chapter 10 — Programming with Streaming SIMD Extensions (SSE). Describes SSE extensions, including XMM registers, the MXCSR register, and packed single-precision floating-point data types; provides an overview of the SSE instruction set and gives guidelines for writing code that accesses the SSE extensions.
Chapter 11 — Programming with Streaming SIMD Extensions 2 (SSE2). Describes SSE2 extensions, including XMM registers and packed double-precision floating-point data types;
provides an overview of the SSE2 instruction set and gives guidelines for writing code that accesses SSE2 extensions. This chapter also describes SIMD floating-point exceptions that can be generated with SSE and SSE2 instructions. It also provides general guidelines for incorpo- rating support for SSE and SSE2 extensions into operating system and applications code.
Chapter 12 — Programming with Streaming SIMD Extensions 3 (SSE3). Describes SSE3 extensions; provides an overview of the SSE3 instruction set and guidelines for writing code that accesses SSE3 extensions.
Chapter 13 — Input/Output. Describes the processor’s I/O mechanism, including I/O port addressing, I/O instructions, and I/O protection mechanisms.
Chapter 14 — Processor Identification and Feature Determination. Describes how to deter- mine the CPU type and features available in the processor.
Vol. 1 1-3 ABOUT THIS MANUAL
Appendix A — EFLAGS Cross-Reference. Summarizes how the IA-32 instructions affect the flags in the EFLAGS register.
Appendix B — EFLAGS Condition Codes. Summarizes how conditional jump, move, and
‘byte set on condition code’ instructions use condition code flags (OF, CF, ZF, SF, and PF) in the EFLAGS register.
Appendix C — Floating-Point Exceptions Summary. Summarizes exceptions raised by the x87 FPU floating-point and SSE/SSE2/SSE3 floating-point instructions.
Appendix D — Guidelines for Writing x87 FPU Exception Handlers. Describes how to design and write MS-DOS* compatible exception handling facilities for FPU exceptions (includes software and hardware requirements and assembly-language code examples). This appendix also describes general techniques for writing robust FPU exception handlers.
Appendix E — Guidelines for Writing SIMD Floating-Point Exception Handlers. Gives guidelines for writing exception handlers for exceptions generated by SSE/SSE2/SSE3 floating- point instructions.
1.3 NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. This notation is described below.
1.3.1 Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. IA-32 proces- sors are “little endian” machines; this means the bytes of a word are numbered starting from the least significant byte. See Figure 1-1.
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1.3.2 Reserved Bits and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable.
Software should follow these guidelines in dealing with reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of registers that contain such bits. Mask out the reserved bits before testing.•
Do not depend on the states of any reserved bits when storing to memory or to a register.•
Do not depend on the ability to retain information written into any reserved bits.•
When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register.NOTE
Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompat- ibility with future processors.
1.3.3 Instruction Operands
When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset, an instruction has the following format,
Figure 1-1. Bit and Byte Order Byte 3
Data Structure
Byte 1
Byte 2 Byte 0
31 24 23 16 15 8 7 0
Lowest Bit offset 28
24 20 16 12 8 4 0
Address Byte Offset Highest
Address
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label: mnemonic argument1, argument2, argument3 where:
•
A label is an identifier which is followed by a colon.•
A mnemonic is a reserved name for a class of instruction opcodes which have the same function.•
The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the opcode. When present, they take the form of either literals or identifiers for data items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items declared in another part of the program (which may not be shown in the example).When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left operand is the destination.
For example:
LOADREG: MOV EAX, SUBTOTAL
In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
1.3.4 Hexadecimal and Binary Numbers
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for example, 0F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.
Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 1010B). The “B” designation is only used in situations where confu- sion as to the type of number might arise.
1.3.5 Segmented Addressing
The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The range of memory that can be addressed is called an address space.
The processor also supports segmented addressing. This is a form of addressing where a program may have many independent address spaces, called segments. For example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space. The following notation is used to specify a byte address within a segment:
Segment-register:Byte-address
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For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS register:
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the code segment and the EIP register contains the address of the instruction.
CS:EIP
1.3.6 A New Syntax for CPUID, CR, and MSR Values
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information. See Figure 1-2.
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1.3.7 Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to divide by zero generates an exception. However, some exceptions, such as break- points, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the error. An example of the notation used to show an exception and error code is shown below.
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is reported. Under some conditions, exceptions that produce error codes may not
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation Control Register Values
Model-Specific Register Values Input value for EAX register
CPUID.01H:ECX.SSE [bit 25] = 1
Value (or range) of output CPUID Input and Output
Output register and feature flag or field name with bit position(s)
CR4.OSFXSR[bit 9] = 1
Feature flag or field name with bit position(s) Value (or range) of output Example CR name
Feature flag or field name with bit position(s) IA32_MISC_ENABLES.ENABLEFOPCODE[bit 2] = 1
Value (or range) of output Example MSR name
OM17732
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be able to report an accurate code. In this case, the error code is zero, as shown below for a general-protection exception.
#GP(0)
1.4 RELATED LITERATURE
Literature related to IA-32 processors is listed on-line at this link:
http://developer.intel.com/design/processor/
Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature available is listed by Intel processor and then by the following literature types: appli- cations notes, data sheets, manuals, papers, and specification updates.
See also:
•
The data sheet for a particular Intel IA-32 processor•
The specification update for a particular Intel IA-32 processor•
AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618•
IA-32 Intel® Architecture Optimization Reference Manual, Order Number 2489662
IA-32 Intel ®
Architecture
Vol. 1 2-1
CHAPTER 2 IA-32 INTEL
®ARCHITECTURE
The exponential growth of computing power and ownership has made the computer one of the most important forces shaping business and society in the second half of the twentieth century.
Computers continue to play crucial roles in the growth of technology, business, and new arenas.
IA-32 Intel Architecture has been at the forefront of the computer revolution and is today the preferred computer architecture, as measured by computers in use and the total computing power available in the world.
2.1 BRIEF HISTORY OF THE IA-32 ARCHITECTURE
The following sections provide a summary of the major technical steps toward the current IA-32 architecture, from the Intel 8086 processor to the latest Pentium 4 and Intel Xeon processors.
For detailed historical data, go to the following link:
http://www.intel.com/intel/intelis/museum/
Object code created for processors released as early as 1978 still executes on the latest proces- sors in the IA-32 architecture family.
2.1.1 16-bit Processors and Segmentation (1978)
The IA-32 architecture family was preceded by 16-bit processors, the 8086 and 8088. The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit addressing giving a 1-MByte address space. The 8088 is similar to the 8086 except it has an 8-bit external data bus.
The 8086/8088 introduced segmentation to the IA-32 architecture. With segmentation, a 16-bit segment register contains a pointer to a memory segment of up to 64 KBytes. Using four segment registers at a time, 8086/8088 processors are able to address up to 256 KBytes without switching between segments. The 20-bit addresses that can be formed using a segment register and an additional 16-bit pointer provide a total address range of 1 MByte.
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2.1.2 The Intel
®286 Processor (1982)
The Intel 286 processor introduced protected mode operation into the IA-32 architecture.
Protected mode uses the segment register content as selectors or pointers into descriptor tables.
Descriptors provide 24-bit base addresses with a physical memory size of up to 16 MBytes, support for virtual memory management on a segment swapping basis, and a number of protec- tion mechanisms. These mechanisms include:
•
Segment limit checking•
Read-only and execute-only segment options•
Four privilege levels2.1.3 The Intel386™ Processor (1985)
The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It intro- duced 32-bit registers for use both to hold operands and for addressing. The lower half of each 32-bit Intel386 register retains the properties of the 16-bit registers of earlier generations, permitting backward compatibility. The processor also provides a virtual-8086 mode that allows for even greater efficiency when executing programs created for 8086/8088 processors.
In addition, the Intel386 processor has support for:
•
A 32-bit address bus that supports up to 4-GBytes of physical memory•
A segmented-memory model and a flat memory model•
Paging, with a fixed 4-KByte page size providing a method for virtual memory management•
Support for parallel stages2.1.4 The Intel486™ Processor (1989)
The Intel486™ processor added more parallel execution capability by expanding the Intel386 processor’s instruction decode and execution units into five pipelined stages. Each each stage operates in parallel with the others on up to five instructions in different stages of execution.
In addition, the processor added:
•
An 8-KByte on-chip first-level cache that increased the percent of instructions that could execute at the scalar rate of one per clock•
An integrated x87 FPU•
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2.1.5 The Intel
®Pentium
®Processor (1993)
The introduction of the Intel Pentium processor added a second execution pipeline to achieve superscalar performance (two pipelines, known as u and v, together can execute two instructions per clock). The on-chip first-level cache doubled, with 8 KBytes devoted to code and another 8 KBytes devoted to data. The data cache uses the MESI protocol to support more efficient write-back cache in addition to the write-through cache previously used by the Intel486 processor. Branch prediction with an on-chip branch table was added to increase performance in looping constructs.
In addition, the processor added:
•
Extensions to make the virtual-8086 mode more efficient and allow for 4-MByte as well as 4-KByte pages•
Internal data paths of 128 and 256 bits add speed to internal data transfers•
Burstable external data bus was increased to 64 bits•
An APIC to support systems with multiple processors•
A dual processor mode to support glueless two processor systemsA subsequent stepping of the Pentium family introduced Intel MMX™ technology (the Pentium Processor with MMX technology). Intel MMX technology uses the single-instruction, multiple- data (SIMD) execution model to perform parallel computations on packed integer data contained in 64-bit registers. See Section 2.2.3, “SIMD Instructions”.
2.1.6 The P6 Family of Processors (1995-1999)
The P6 family of processors was based on a superscalar microarchitecture that set new perfor- mance standards; see also Section 2.2.1, “P6 Family Microarchitecture”. One of the goals in the design of the P6 family microarchitecture was to exceed the performance of the Pentium processor significantly while using the same 0.6-micrometer, four-layer, metal BICMOS manu- facturing process. Members of this family include the following:
•
The Intel Pentium Pro processor is three-way superscalar. Using parallel processing techniques, the processor is able on average to decode, dispatch, and complete execution of (retire) three instructions per clock cycle. The Pentium Pro introduced the dynamic execution (micro-data flow analysis, out-of-order execution, superior branch prediction, and speculative execution) in a superscalar implementation. The processor was further enhanced by its caches. It has the same two on-chip 8-KByte 1st-Level caches as the Pentium processor and an additional 256-KByte Level 2 cache in the same package as the processor.2-4 Vol. 1
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•
The Intel Pentium II processor added Intel MMX Technology to the P6 family processors along with new packaging and several hardware enhancements. The processor core is packaged in the single edge contact cartridge (SECC). The Level l data and instruction caches were enlarged to 16 KBytes each, and Level 2 cache sizes of 256 KBytes, 512 KBytes, and 1 MByte are supported. A half-clock speed backside bus connects the Level 2 cache to the processor. Multiple low-power states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep are supported to conserve power when idling.•
The Pentium II Xeon processor combined the premium characteristics of previous generations of Intel processors. This includes: 4-way, 8-way (and up) scalability and a 2 MByte 2nd-Level cache running on a full-clock speed backside bus.•
The Intel Celeron processor family focused the IA-32 architecture on the value PC market segment. It offers an integrated 128 KBytes of Level 2 cache and a plastic pin grid array (P.P.G.A.) form factor to lower system design cost.•
The Intel Pentium III processor introduced the Streaming SIMD Extensions (SSE) to the IA-32 architecture. SSE extensions expand the SIMD execution model introduced with the Intel MMX technology by providing a new set of 128-bit registers and the ability to perform SIMD operations on packed single-precision floating-point values. See Section 2.2.3,“SIMD Instructions”.
•
The Pentium III Xeon processor extended the performance levels of the IA-32 processors with the enhancement of a full-speed, on-die, and Advanced Transfer Cache.2.1.7 The Intel Pentium 4 Processor Family (2000-2005)
The Intel Pentium 4 processor family is based on Intel NetBurst® microarchitecture; see Section 2.2.2, “Intel NetBurst® Microarchitecture”.
The Intel Pentium 4 processor introduced Streaming SIMD Extensions 2 (SSE2); see Section 2.2.3, “SIMD Instructions”. The Intel Pentium 4 processor 3.40 GHz, supporting Hyper- Threading Technology introduced Streaming SIMD Extensions 3 (SSE3); see Section 2.2.3,
“SIMD Instructions”.
Intel® Extended Memory 64 Technology is available first in Intel Pentium 4 Processor Extreme Edition supporting Hyper-Threading Technology and Intel Pentium 4 Processor 6xx series.
2.1.8 The Intel
®Xeon Processor (2001-2005)
The Intel Xeon processor is also based on the Intel NetBurst microarchitecture; see Section 2.2.2,
“Intel NetBurst® Microarchitecture”. As a family, this group of IA-32 processors is designed for use in multi-processor server systems and high-performance workstations.
The Intel Xeon processor MP introduced support for Hyper-Threading Technology; see Section 2.2.4, “Hyper-Threading Technology”.
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The 64-bit Intel Xeon processor 3.60 GHz with 800 MHz System Bus introduced Intel® Extended Memory 64 Technology. See Section 2.2.6, “Intel® Extended Memory 64 Technology”.
2.1.9 The Intel
®Pentium
®M Processor (2003-2005)
The Intel Pentium M processor family is a high performance, low power mobile processor family with microarchitectural enhancements over previous generations of Intel mobile proces- sors. This family is designed for extending battery life and seamless integration with platform innovations that enable new usage models (such as extended mobility, ultra thin form-factors, and integrated wireless networking).
Its enhanced microarchitecture includes:
•
Support for Intel Architecture with Dynamic Execution•
A high performance, low-power core manufactured using Intel’s advanced process technology with copper interconnect•
On-die, primary 32-KByte instruction cache and 32-KByte write-back data cache On-die, second-level cache (up to 2 MByte) with Advanced Transfer Cache Architecture•
Advanced Branch Prediction and Data Prefetch Logic•
Support for MMX™ Technology, Streaming SIMD instructions, and the SSE2 instruction set•
A 400 or 533 MHz, Source-Synchronous Processor System Bus•
Advanced power management using Enhanced Intel® SpeedStep® Technology2.1.10 The Intel Pentium Processor Extreme Edition (2005)
The Intel Pentium processor Extreme Edition introduced dual-core technology. This technology provides advanced hardware multi-threading support. The processor is based on Intel NetBurst® microarchitecture and supports SSE, SSE2, SSE3, Hyper-Threading Technology, and Intel® Extended Memory 64 Technology.
See also:
