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XMM registers — See Chapter 10, “Programming with Streaming SIMD Extensions (SSE)”, Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2)”, and Chapter 12, “Programming with Streaming SIMD Extensions 3 (SSE3)”.•
Stack implementation and procedure calls — See Chapter 6, “Procedure Calls, Interrupts, and Exceptions”.Vol. 1 3-7 BASIC EXECUTION ENVIRONMENT
Figure 3-2. 64-Bit Mode Execution Environment 0 264 -1 Sixteen 64-bit
64-bits 64-bits
General-Purpose Registers
Segment Registers
RFLAGS Register
RIP (Instruction Pointer Register)
Address Space
Six 16-bit Registers Registers
Eight 80-bit
Registers Floating-Point
Data Registers
Eight 64-bit
Registers MMX Registers
XMM Registers Sixteen 128-bit
Registers
16 bits Control Register 16 bits Status Register
64 bits FPU Instruction Pointer Register 64 bits FPU Data (Operand) Pointer Register FPU Registers
MMX Registers
XMM Registers
32-bits MXCSR Register Opcode Register (11-bits) Basic Program Execution Registers
16 bits Tag Register
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3.3 MEMORY ORGANIZATION
The memory that the processor addresses on its bus is called physical memory. Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address. The physical address space ranges from zero to a maximum of 236 −1 (64 GBytes) if the processor does not support Intel EM64T. Intel EM64T introduces a few changes in physical and linear address space, they are described in Section 3.3.3, Section 3.3.4, and Section 3.3.7.
Virtually any operating system or executive designed to work with an IA-32 processor will use the processor’s memory management facilities to access memory. These facilities provide features such as segmentation and paging, which allow memory to be managed efficiently and reliably. Memory management is described in detail in Chapter 3, Protected-Mode Memory Management, in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3. The following paragraphs describe the basic methods of addressing memory when memory manage-ment is used.
3.3.1 Three Memory Models
When employing the processor’s memory management facilities, programs do not directly address physical memory. Instead, they access memory using one of three memory models: flat, segmented, or real address mode:
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Flat memory model — Memory appears to a program as a single, continuous address space (Figure 3-3). This space is called a linear address space. Code, data, and stacks are all contained in this address space. Linear address space is byte addressable, with addresses running contiguously from 0 to 232 - 1 (if not in 64-bit mode). An address for any byte in linear address space is called a linear address.•
Segmented memory model — Memory appears to a program as a group of independent address spaces called segments. Code, data, and stacks are typically contained in separate segments. To address a byte in a segment, a program issues a logical address. This consists of a segment selector and an offset (logical addresses are often referred to as far pointers).The segment selector identifies the segment to be accessed and the offset identifies a byte in the address space of the segment. Programs running on an IA-32 processor can address up to 16,383 segments of different sizes and types, and each segment can be as large as 232 bytes.
Internally, all the segments that are defined for a system are mapped into the processor’s linear address space. To access a memory location, the processor thus translates each logical address into a linear address. This translation is transparent to the application program.
The primary reason for using segmented memory is to increase the reliability of programs and systems. For example, placing a program’s stack in a separate segment prevents the stack from growing into the code or data space and overwriting instructions or data, respectively.
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Real-address mode memory model — This is the memory model for the Intel 8086 processor. It is supported to provide compatibility with existing programs written to run onVol. 1 3-9 BASIC EXECUTION ENVIRONMENT
the Intel 8086 processor. The real-address mode uses a specific implementation of segmented memory in which the linear address space for the program and the operating system/executive consists of an array of segments of up to 64 KBytes in size each. The maximum size of the linear address space in real-address mode is 220 bytes.
See also: Chapter 16, 8086 Emulation, IA-32 Intel Architecture Software Developer’s Manual, Volume 3
3.3.2 Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is mapped into the processor’s physical address space either directly or through paging. When using direct mapping (paging disabled), each linear address has a one-to-one correspondence with a physical address.
Linear addresses are sent out on the processor’s address lines without translation.
When using the IA-32 architecture’s paging mechanism (paging enabled), linear address space is divided into pages which are mapped to virtual memory. The pages of virtual memory are then
Figure 3-3. Three Memory Management Models Linear Address
Flat Model
Linear Address Space*
Segment Selector
Offset
Segment Selector
Segmented Model
Real-Address Mode Model
Linear Address
Logical
Offset (effective address)
Space Divided Into Equal Sized Segments Address
Logical Address
Linear Address Space*
Segments
* The linear address space can be paged when using the flat or segmented model.
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mapped as needed into physical memory. When an operating system or executive uses paging, the paging mechanism is transparent to an application program. All that the application sees is linear address space.
In addition, IA-32 architecture’s paging mechanism includes extensions that support:
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Page Address Extensions (PAE) to address physical address space greater than 4 GBytes.•
Page Size Extensions (PSE) to map linear address to physical address in 4-MBytes pages.See also: Chapter 3, Protected-Mode Memory Management, in the IA-32 Intel Architecture Soft-ware Developer’s Manual, Volume 3.
3.3.3 Memory Organization in 64-Bit Mode
Intel EM64T supports physical address space greater than 64 GBytes; the actual physical address size of IA-32 processors is implementation specific. In 64-bit mode, there is architec-tural support for 64-bit linear address space. However, processors supporting Intel EM64T may implement less than 64-bits (see Section 3.3.7.1). The linear address space is mapped into the processor physical address space through the PAE paging mechanism.
3.3.4 Modes of Operation vs. Memory Model
When writing code for an IA-32 processor, a programmer needs to know the operating mode the processor is going to be in when executing the code and the memory model being used. The rela-tionship between operating modes and memory models is as follows:
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Protected mode — When in protected mode, the processor can use any of the memory models described in this section. (The real-addressing mode memory model is ordinarily used only when the processor is in the virtual-8086 mode.) The memory model used depends on the design of the operating system or executive. When multitasking is imple-mented, individual tasks can use different memory models.•
Real-address mode — When in address mode, the processor only supports the real-address mode memory model.•
System management mode — When in SMM, the processor switches to a separate address space, called the system management RAM (SMRAM). The memory model used to address bytes in this address space is similar to the real-address mode model. See Chapter 13, System Management Mode (SMM), in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3, for more information on the memory model used in SMM.•
Compatibility mode — Software that needs to run in compatibility mode should observe the same memory model as those targeted to run in 32-bit protected mode. The effect of segmentation is the same as it is in 32-bit protected mode semantics.Vol. 1 3-11 BASIC EXECUTION ENVIRONMENT
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64-bit mode — Segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address space. Specifically, the processor treats the segment base of CS, DS, ES, and SS as zero in 64-bit mode (this makes a linear address equal an effective address).Segmented and real address modes are not available in 64-bit mode.