Basic Execution Environment
CHAPTER 3 BASIC EXECUTION ENVIRONMENT
This chapter describes the basic execution environment of an IA-32 processor as seen by assembly-language programmers. It describes how the processor executes instructions and how it stores and manipulates data. The execution environment described here includes memory (the address space), general-purpose data registers, segment registers, the flag register, and the instruction pointer register.
3.1 MODES OF OPERATION
The IA-32 architecture supports three basic operating modes: protected mode, real-address mode, and system management mode. The operating mode determines which instructions and architectural features are accessible:
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Protected mode — This mode is the native state of the processor. Among the capabilities of protected mode is the ability to directly execute “real-address mode” 8086 software in a protected, multi-tasking environment. This feature is called virtual-8086 mode, although it is not actually a processor mode. Virtual-8086 mode is actually a protected mode attribute that can be enabled for any task.•
Real-address mode — This mode implements the programming environment of the Intel 8086 processor with extensions (such as the ability to switch to protected or system management mode). The processor is placed in real-address mode following power-up or a reset.•
System management mode (SMM) — This mode provides an operating system or executive with a transparent mechanism for implementing platform-specific functions such as power management and system security. The processor enters SMM when the external SMM interrupt pin (SMI#) is activated or an SMI is received from the advanced programmable interrupt controller (APIC).In SMM, the processor switches to a separate address space while saving the basic context of the currently running program or task. SMM-specific code may then be executed trans-parently. Upon returning from SMM, the processor is placed back into its state prior to the system management interrupt. SMM was introduced with the Intel386™ SL and Intel486™ SL processors and became a standard IA-32 feature with the Pentium processor family.
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3.1.1 IA-32e Mode
The Intel® Extended Memory 64 Technology (Intel® EM64T) extends the IA-32 architecture’s basic operating modes and adds a new mode of operation: IA-32e mode. IA-32e mode has two sub-modes. These are:
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Compatibility mode (sub-mode of IA-32e mode) — Compatibility mode permits most legacy 16-bit and 32-bit applications to run without re-compilation under a 64-bit operating system. For brevity, the compatibility sub-mode is referred to as compatibility mode in IA-32 architecture. The execution environment of compatibility mode is the same as described in Section 3.2. Legacy applications that run in Virtual 8086 mode or use hardware task management will not work in this mode.Compatibility mode is enabled by the operating system (OS) on a code segment basis. This means that a single 64-bit OS can support 64-bit applications running in 64-bit mode and support legacy 32-bit applications (not recompiled for 64-bits) running in compatibility mode.
Compatibility mode is similar to 32-bit protected mode. Applications access only the first 4 GByte of linear-address space. Compatibility mode uses 16-bit and 32-bit address and operand sizes. Like protected mode, this mode allows applications to access physical memory greater than 4 GByte using PAE (Physical Address Extensions).
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64-bit mode (sub-mode of IA-32e mode) — This mode enables a 64-bit operating system to run applications written to access 64-bit linear address space. For brevity, the 64-bit sub-mode is referred to as 64-bit sub-mode in IA-32 architecture.64-bit mode extends the number of general purpose registers and SIMD extension registers from 8 to 16. General purpose registers are widened to 64 bits. The mode also introduces a new opcode prefix (REX) to access the register extensions. See Section 3.2.1 for a detailed description.
64-bit mode is enabled by the operating system on a code-segment basis. Its default address size is 64 bits and its default operand size is 32 bits. The default operand size can be overridden on an instruction-by-instruction basis using a REX opcode prefix in conjunction with an operand size override prefix.
REX prefixes allow a 64-bit operand to be specified when operating in 64-bit mode. By using this mechanism, many existing instructions have been promoted to allow the use of 64-bit registers and 64-bit addresses.
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3.2 OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT
Any program or task running on an IA-32 processor is given a set of resources for executing instructions and for storing code, data, and state information. These resources (described briefly in the following paragraphs and shown in Figure 3-1) make up the basic execution environment for an IA-32 processor. The basic execution environment is used jointly by the application programs and the operating system or executive running on the processor.
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Address space — Any task or program running on an IA-32 processor can address a linear address space of up to 4 GBytes (232 bytes) and a physical address space of up to 64 GBytes (236 bytes). See Section 3.3.6, “Extended Physical Addressing in Protected Mode” for more information about addressing an address space greater than 4 GBytes.•
Basic program execution registers — The eight general-purpose registers, the six segment registers, the EFLAGS register, and the EIP (instruction pointer) register comprise a basic execution environment in which to execute a set of general-purpose instructions. These instructions perform basic integer arithmetic on byte, word, and doubleword integers, handle program flow control, operate on bit and byte strings, and address memory. See Section 3.4, “Basic Program Execution Registers”, for more information about these registers.•
x87 FPU registers — The eight x87 FPU data registers, the x87 FPU control register, the status register, the x87 FPU instruction pointer register, the x87 FPU operand (data) pointer register, the x87 FPU tag register, and the x87 FPU opcode register provide an execution environment for operating on single-precision, double-precision, and double extended-precision floating-point values, word integers, doubleword integers, quadword integers, and binary coded decimal (BCD) values. See Section 8.1, “x87 FPU Execution Environment”, for more information about these registers.•
MMX™ registers — The eight MMX registers support execution of single-instruction, multiple-data (SIMD) operations on 64-bit packed byte, word, and doubleword integers.See Section 9.2, “The MMX Technology Programming Environment”, for more information about these registers.
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XMM registers — The eight XMM data registers and the MXCSR register support execution of SIMD operations on 128-bit packed single-precision and double-precision floating-point values and on 128-bit packed byte, word, doubleword, and quadword integers. See Section 10.2, “SSE Programming Environment”, for more information about these registers.•
Stack — To support procedure or subroutine calls and the passing of parameters between procedures or subroutines, a stack and stack management resources are included in the execution environment. The stack (not shown in Figure 3-1) is located in memory. See Section 6.2, “Stacks”, for more information about stack structure.3-4 Vol. 1
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Figure 3-1. IA-32 Basic Execution Environment for Non-64-bit Modes 0
232 -1 Eight 32-bit
32-bits 32-bits
General-Purpose Registers
Segment Registers
EFLAGS Register
EIP (Instruction Pointer Register)
Address Space*
*The address space can be Six 16-bit
Registers Registers
Eight 80-bit
Registers Floating-Point
Data Registers
Eight 64-bit
Registers MMX Registers
flat or segmented. Using
XMM Registers Eight 128-bit
Registers
16 bits Control Register 16 bits Status Register
48 bits FPU Instruction Pointer Register 48 bits FPU Data (Operand) Pointer Register FPU Registers
MMX Registers
XMM Registers
32-bits MXCSR Register Opcode Register (11-bits) Basic Program Execution Registers
16 bits Tag Register
the physical address extension mechanism, a physical address space of 236 − 1 can be addressed.
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In addition to the resources provided in the basic execution environment, the IA-32 architecture provides the following resources as part of its system-level architecture. They provide extensive support for operating-system and system-development software. Except for the I/O ports, the system resources are described in detail in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide.
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I/O ports — The IA-32 architecture supports a transfers of data to and from input/output (I/O) ports. See Chapter 13, “Input/Output”, in this volume.•
Control registers — The five control registers (CR0 through CR4) determine the operating mode of the processor and the characteristics of the currently executing task. See the section titled “Control Registers” of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3.•
Memory management registers — The GDTR, IDTR, task register, and LDTR specify the locations of data structures used in protected mode memory management. See the section titled “Memory-Management Registers” in Chapter 2 of the IA-32 Intel Archi-tecture Software Developer’s Manual, Volume 3.•
Debug registers — The debug registers (DR0 through DR7) control and allow monitoring of the processor’s debugging operations. See the section titled “Debug Registers” in Chapter 15 of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3.•
Memory type range registers (MTRRs) — The MTRRs are used to assign memory types to regions of memory. See the section titled “Memory Type Range Registers (MTRRs)” in Chapter 10 of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3.•
Machine specific registers (MSRs) — The processor provides a variety of machine specific registers that are used to control and report on processor performance. Virtually all MSRs handle system related functions and are not accessible to an application program.One exception to this rule is the time-stamp counter. The MSRs are described in Appendix B, Model-Specific Registers (MSRs) of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3).
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Machine check registers — The machine check registers consist of a set of control, status, and error-reporting MSRs that are used to detect and report on hardware (machine) errors.See the section titled “Machine-Check MSRs” in Chapter 14 of the IA-32 Intel Archi-tecture Software Developer’s Manual, Volume 3.
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Performance monitoring counters — The performance monitoring counters allow processor performance events to be monitored. See the section titled “Performance Monitoring Overview” in Chapter 15 of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3.The remainder of this chapter describes the organization of memory and the address space, the basic program execution registers, and addressing modes. Refer to the following chapters in this volume for descriptions of the other program execution resources shown in Figure 3-1:
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x87 FPU registers — See Chapter 8, “Programming with the x87 FPU”.•
MMX Registers — See Chapter 9, “Programming with Intel® MMX™ Technology”.3-6 Vol. 1
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