4.6.2 128-Bit Packed SIMD Data Types
4.9 OVERVIEW OF FLOATING-POINT EXCEPTIONS
4.9.1 Floating-Point Exception Conditions
The following sections describe the various conditions that cause a floating-point exception to be generated and the masked response of the processor when these conditions are detected.
Chapter 3, Instruction Set Reference A-M and Chapter 4, Instruction Set Reference N-Z of the IA-32 Intel Architecture Software Developer’s Manual, Volumes 2A & 2B list the floating-point exceptions that can be signaled for each floating-point instruction.
4.9.1.1 Invalid Operation Exception (#I)
The processor reports an invalid operation exception in response to one or more invalid arith-metic operands. If the invalid operation exception is masked, the processor sets the IE flag and returns an indefinite value or a QNaN. This value overwrites the destination register specified by the instruction. If the invalid operation exception is not masked, the IE flag is set, a software exception handler is invoked, and the operands remain unaltered.
See Section 4.8.3.6, “Using SNaNs and QNaNs in Applications” information about the result returned when an exception is caused by an SNaN.
The processor can detect a variety of invalid arithmetic operations that can be coded in a program. These operations generally indicate a programming error, such as dividing ∞ by ∞ . See the following sections for information regarding the invalid-operation exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:
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x87 FPU; Section 8.5.1, “Invalid Operation Exception”•
SIMD floating-point exceptions; Section 11.5.2.1, “Invalid Operation Exception (#I)”4.9.1.2 Denormal Operand Exception (#D)
The processor reports the denormal-operand exception if an arithmetic instruction attempts to operate on a denormal operand (see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”). When the exception is masked, the processor sets the DE flag and proceeds with the instruction. Operating on denormal numbers will produce results at least as good as, and often better than, what can be obtained when denormal numbers are flushed to zero. Programmers can mask this exception so that a computation may proceed, then analyze any loss of accuracy when the final result is delivered.
When a denormal-operand exception is not masked, the DE flag is set, a software exception handler is invoked, and the operands remain unaltered. When denormal operands have reduced significance due to loss of low-order bits, it may be advisable to not operate on them. Precluding denormal operands from computations can be accomplished by an exception handler that responds to unmasked denormal-operand exceptions.
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See the following sections for information regarding the denormal-operand exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions:
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x87 FPU; Section 8.5.2, “Denormal Operand Exception (#D)”•
SIMD floating-point exceptions; Section 11.5.2.2, “Denormal-Operand Exception (#D)”4.9.1.3 Divide-By-Zero Exception (#Z)
The processor reports the floating-point divide-by-zero exception whenever an instruction attempts to divide a finite non-zero operand by 0. The masked response for the divide-by-zero exception is to set the ZE flag and return an infinity signed with the exclusive OR of the sign of the operands. If the divide-by-zero exception is not masked, the ZE flag is set, a software excep-tion handler is invoked, and the operands remain unaltered.
See the following sections for information regarding the divide-by-zero exception when detected while executing x87 FPU or SSE/SSE2 instructions:
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x87 FPU; Section 8.5.3, “Divide-By-Zero Exception (#Z)”•
SIMD floating-point exceptions; Section 11.5.2.3, “Divide-By-Zero Exception (#Z)”4.9.1.4 Numeric Overflow Exception (#O)
The processor reports a floating-point numeric overflow exception whenever the rounded result of an instruction exceeds the largest allowable finite value that will fit into the destination operand. Table 4-9 shows the threshold range for numeric overflow for each of the floating-point formats; overflow occurs when a rounded result falls at or outside this threshold range.
When a numeric-overflow exception occurs and the exception is masked, the processor sets the OE flag and returns one of the values shown in Table 4-10, according to the current rounding mode. See Section 4.8.4, “Rounding”.
When numeric overflow occurs and the numeric-overflow exception is not masked, the OE flag is set, a software exception handler is invoked, and the source and destination operands either remain unchanged or a biased result is stored in the destination operand (depending whether the overflow exception was generated during an SSE/SSE2/SSE3 floating-point operation or an x87 FPU operation).
Table 4-9. Numeric Overflow Thresholds
Floating-Point Format Overflow Thresholds
Single Precision | x | ≥ 1.0 ∗ 2128
Double Precision | x | ≥ 1.0 ∗ 21024
Double Extended Precision | x | ≥ 1.0 ∗ 216384
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See the following sections for information regarding the numeric overflow exception when detected while executing x87 FPU instructions or while executing SSE/SSE2/SSE3 instructions:
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x87 FPU; Section 8.5.4, “Numeric Overflow Exception (#O)”•
SIMD floating-point exceptions; Section 11.5.2.4, “Numeric Overflow Exception (#O)”4.9.1.5 Numeric Underflow Exception (#U)
The processor detects a floating-point numeric underflow condition whenever the result of rounding with unbounded exponent (taking into account precision control for x87) is tiny; that is, less than the smallest possible normalized, finite value that will fit into the destination operand. Table 4-11 shows the threshold range for numeric underflow for each of the floating-point formats (assuming normalized results); underflow occurs when a rounded result falls strictly within the threshold range. The ability to detect and handle underflow is provided to prevent a vary small result from propagating through a computation and causing another excep-tion (such as overflow during division) to be generated at a later time.
How the processor handles an underflow condition, depends on two related conditions:
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creation of a tiny result•
creation of an inexact result; that is, a result that cannot be represented exactly in the destination formatTable 4-10. Masked Responses to Numeric Overflow Rounding Mode Sign of True Result Result
To nearest + +∞
– –∞
Toward –∞ + Largest finite positive number
– –∞
Toward +∞ + +∞
– Largest finite negative number
Toward zero + Largest finite positive number
– Largest finite negative number
Table 4-11. Numeric Underflow (Normalized) Thresholds
Floating-Point Format Underflow Thresholds*
Single Precision | x | < 1.0 ∗ 2−126
Double Precision | x | < 1.0 ∗ 2−1022
Double Extended Precision | x | < 1.0 ∗ 2−16382
* Where ‘x’ is the result rounded to destination precision with an unbounded exponent range.
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Which of these events causes an underflow exception to be reported and how the processor responds to the exception condition depends on whether the underflow exception is masked:
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Underflow exception masked — The underflow exception is reported (the UE flag is set) only when the result is both tiny and inexact. The processor returns a denormalized result to the destination operand, regardless of inexactness.•
Underflow exception not masked — The underflow exception is reported when the result is tiny, regardless of inexactness. The processor leaves the source and destination operands unaltered or stores a biased result in the designating operand (depending whether the underflow exception was generated during an SSE/SSE2/SSE3 floating-point operation or an x87 FPU operation) and invokes a software exception handler.See the following sections for information regarding the numeric underflow exception when detected while executing x87 FPU instructions or while executing SSE/SSE2/SSE3 instructions:
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x87 FPU; Section 8.5.5, “Numeric Underflow Exception (#U)”•
SIMD floating-point exceptions; Section 11.5.2.5, “Numeric Underflow Exception (#U)”4.9.1.6 Inexact-Result (Precision) Exception (#P)
The inexact-result exception (also called the precision exception) occurs if the result of an oper-ation is not exactly representable in the destinoper-ation format. For example, the fraction 1/3 cannot be precisely represented in binary floating-point form. This exception occurs frequently and indicates that some (normally acceptable) accuracy will be lost due to rounding. The exception is supported for applications that need to perform exact arithmetic only. Because the rounded result is generally satisfactory for most applications, this exception is commonly masked.
If the inexact-result exception is masked when an inexact-result condition occurs and a numeric overflow or underflow condition has not occurred, the processor sets the PE flag and stores the rounded result in the destination operand. The current rounding mode determines the method used to round the result. See Section 4.8.4, “Rounding”.
If the inexact-result exception is not masked when an inexact result occurs and numeric over-flow or underover-flow has not occurred, the PE flag is set, the rounded result is stored in the desti-nation operand, and a software exception handler is invoked.
If an inexact result occurs in conjunction with numeric overflow or underflow, one of the following operations is carried out:
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If an inexact result occurs along with masked overflow or underflow, the OE flag or UE flag and the PE flag are set and the result is stored as described for the overflow or underflow exceptions; see Section 4.9.1.4, “Numeric Overflow Exception (#O)” or Section 4.9.1.5, “Numeric Underflow Exception (#U)”. If the inexact result exception is unmasked, the processor also invokes a software exception handler.•
If an inexact result occurs along with unmasked overflow or underflow and the destination operand is a register, the OE or UE flag and the PE flag are set, the result is stored as described for the overflow or underflow exceptions, and a software exception handler is invoked.4-28 Vol. 1 DATA TYPES
If an unmasked numeric overflow or underflow exception occurs and the destination operand is a memory location (which can happen only for a floating-point store), the inexact-result condi-tion is not reported and the C1 flag is cleared.
See the following sections for information regarding the inexact-result exception when detected while executing x87 FPU or SSE/SSE2/SSE3 instructions: