Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique

Characterization of Programmed Charge Lateral

Distribution in a Two-Bit Storage Nitride Flash

Memory Cell by Using a Charge-Pumping Technique

Shaw-Hung Gu, Tahui Wang, Senior Member, IEEE, Wen-Pin Lu, Wenchi Ting, Yen-Hui Joseph Ku, and

Chih-Yuan Lu, Fellow, IEEE

Abstract—In this paper, we use a modified charge pumping

tech-nique to characterize the programmed charge lateral distribution

in a hot electron program/hot hole erase, two-bit storage nitride

Flash memory cell. The stored charge distribution of each bit over

the source/drain junctions can be profiled separately. Our result

shows that the second programmed bit has a broader stored charge

distribution than the first programmed bit. The reason is that a

large channel field exists under the first programmed bit during

the second bit programming. Such a large field accelerates channel

electrons and causes earlier electron injection into the nitride. In

addition, we find that programmed charges spread further into the

channel as program/erase cycle number increases.

Index Terms—Charge pumping (CP), cycling stress,

pro-grammed charge distribution, two-bit storage nitride Flash cell.

I. I

N

ITRIDE-BASED trapping storage Flash memory has

re-ceived much interest recently for its smaller bit size,

sim-pler manufacturing process, and no drain-induced turnon [1],

[2]. In a conventional SONOS cell, programmed charges are

stored uniformly in a nitride layer. This SONOS concept has

recently evolved into a localized trapping and two-bit storage

cell, such as NROM [3] and Nbit [4] technologies. These

spe-cial-type nitride Flash cells resemble a standard MOS transistor

except that the gate oxide is replaced by an oxide-nitride-oxide

gate dielectric stack. Two bits operation can be achieved by

placing programmed charges in the nitride layer locally above

the source or the drain junction by channel hot electron

pro-gram and band-to-band hot hole erase. A reverse read scheme

is employed to maximize the effect of the stored charge on

the threshold voltage window [3]. Because of a symmetrical

cell structure and a nonconductive storage element, the Nbit

technology has been engineered to take advantage of a higher

packing density memory array without compromising device

endurance, performance and reliability.

In two-bit operation, the control of programmed charge

lat-eral distribution of each bit is a major concern for the scalability

Manuscript received May 4, 2005; revised July 27, 2005. This work was sup-ported by the National Science Center, Taiwan, R.O.C., under Contract NSC 92-2215-E-009-056. The review of this paper was arranged by Editor S. Kimuro. S.-H. Gu and T. Wang are with the Department of Electronics Engi-neering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).

W.-P. Lu, W. Ting, Y.-H. J. Ku and C.-Y. Lu are with the Macronix Interna-tional Company Ltd., Hsinchu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/TED.2005.860632

Fig. 1. (a) Schematic diagram of a two-bit storage nitride Flash cell and (b) CP measurement waveform. The dashed line in the substrate represents the depletion region caused byV . The thickness of the ONO gate stack is 9 (top oxide), 6, and 6 nm, respectively.

of this memory cell. The stored electrons at the first bit will

af-fect the threshold voltage of the second bit in reverse read and

vice versa. This phenomenon is referred to as the second bit

effect [5] and is closely related to programmed charge lateral

spread. Furthermore, the lateral spread of stored charges in

ni-tride will result in the degradation of erase capability or erase

speed due to a spatial mismatch between stored electrons and

injected holes during erase [6]. For these reasons,

comprehen-sive understanding of programmed charge spatial distribution is

operation bias.

Attempts have been made in the past to characterize the

trapped charge distribution in a NROM cell [7], [8]. Larcher et

al. used an inverse modeling approach to extract programmed

charge distribution from measured current–voltage ( – )

characteristics [7]. This method, however, suffers from some

drawbacks, such as lack of precise information on device

doping profile and extensive numerical calculation to reach

a consistent solution between stored charge distribution and

measurement result.

In this paper, we will use a modified charge-pumping (CP)

technique [9] to probe the lateral distribution of programmed

charges at the source and drain junctions separately without

using computer simulation. The devices and measurement

setup throughout this study will be described in Section II. The

CP current for single bit storage and two-bit storage will be

shown in Section III. Program/erase cycling stress effect on

stored charge distribution will be also examined.

II. E

The nitride Flash cells used in this paper have a gate length

of 0.5

m and a gate width of 1.0

m. The thickness of each

ONO layer is 9 nm (top oxide), 6 nm (nitride) and 6 nm (bottom

oxide). The cell intrinsic threshold voltage (

) is about 1.6 V

where

is defined as the gate voltage when the drain current

is 1

A at a reverse read voltage of 1.6 V. Channel hot

elec-tron program and band-to-band hot hole erase accompanied by

a reverse read scheme are adopted to achieve two-bit per cell

operation.

In CP measurement, the voltage waveforms at gate and drain

terminals supplied by a two-channel pulse generator are

illus-trated in Fig. 1. The employment of a dual-channel pulse

gener-ator can circumvent the misalignment of gate and drain signal.

The gate pulse has a fixed high level (

) and a variable low

level (

). The

is sufficiently high (

V here) to

en-sure that the entire channel at program state is inverted.

The CP current, named hereafter

, is measured at the

substrate. To probe the lateral extent of programmed charge

in the drain side (or the source side),

(or

) is adjusted to

modulate the drain (or source) depletion width while

(or

) is left floating. In this way, there is no channel current

and thus no impact ionization induced substrate current in

CP measurement. Besides, the

is 180 phase-shifted with

respect to

so that the drain signal is applied only during

the interface-trap (

) electron emptying period. Because

the length of the channel hot electron injection region (i.e.,

programmed region) is only about a few nanometers [9],

contributed by interface traps in the programmed region is

very low and close to the measurement limit of the current

setup. Therefore, a higher frequency of 2.5 MHz with 50%

duty cycle and rise/fall times of 15 ns each is selected in CP

measurement. To make sure the measured

is still reliable

at this frequency, the frequency dependence of normalized

CP current at program state is shown in Fig. 2. The constant

confirms the validity of the CP measurement.

Fig. 2. Dependence of normalized CP current (I =f ) on measurement frequency. In CP measurement, theV window (1V ) is 2.7 V and I is measured atV = 2:5 V.

Fig. 3. I versusV in a fresh cell, in program state and in erase state, respectively. TheV window (1V ) is 2 V. V in CP measurement is 0 V.

III. M

R

D

A. Single-Bit Storage

Fig. 3 shows the

versus

curves in a virgin cell, after

programming only, and after one P/E cycle, respectively. Only

the first bit (drain side) is P/E cycled and the

in CP

mea-surement is 0 V. The threshold voltage window (

) is 2 V.

The

in a virgin cell and in erase state are almost identical,

whereas a noticeable

bump at program state is noticed. This

bump is attributed to a local increase of channel threshold

voltage due to negative nitride charge trapping. To verify the

nitride charge storage effect, the

characteristics for two

dif-ferent threshold voltage windows,

V and 2.7 V, are

compared in Fig. 4. As expected, the larger threshold voltage

window exhibits a larger

bump due to more stored

elec-trons. The dependence of the program-state

bump on

in

charge pumping measurement is shown in Fig. 5. The

bump

is suppressed as

increases. The reason is that the drain

deple-tion region increases with

. At a sufficiently large

(in this

Fig. 1.8 V), interface traps underneath the program charges are

completely “masked” by the drain depletion region. Thus, these

interface traps can no longer go through

inversion-accumula-tion cycles in CP measurement and do not contribute to

. As

a result, the program-state

bump is totally suppressed. Our

Fig. 4. I versus V for different V window. The program state I bump increases withV window due to more injected charges.

Fig. 5. I versus V with different V in CP measurement. The program-stateI bump decreases with V . The V window is 2 V.

result here implies that a

about 1.8 V is necessary in reverse

read to avoid completely the second bit effect.

B. Two-Bit Storage

The Nbit cell stores two bits at different locations (drain-side

and source-side). Each bit within a cell serves as binary unit

of data that is totally mapped to four states in a memory cell.

The

of the four states corresponding to “11,” “10,” “01” and

“00” are shown in Fig. 6. “00” denotes both bits in program

state. “10” (or “01”) denotes the drain-side bit in erase state (or

in program state) and the source-side bit in program state (or

in erase state). To explore the influence of the programming

se-quence on trapped charge spatial profile, the CP measurement is

performed after each bit is programmed. Fig. 7 shows the

of

the first programmed bit and the second programmed bit,

respec-tively. Here, the

of the second programmed bit is obtained

in two ways. One is to measure

after the first bit is erased.

The second approach is to subtract the fist bit

from the “00”

state

. Fig. 8 compares the second bit

from the above two

approaches and the result is almost the same. It should be

em-phasized that a crossover of the first bit and the second bit

in

Fig. 7 is observed. This suggests that the second programmed bit

has a wider charge distribution but a smaller peak density. The

reason will be discussed later. To profile the nitride stored charge

lateral distribution, a technique similar to [9] is performed. In

Fig. 6. I versus V of the four states of two-bit storage. “11” represents both bits in erase-state and “10” represents one bit in erase-state and one bit in program-state.

Fig. 7. Comparison of theI versus V of the first programmed bit and the secondly programmed bit. The second bitI is measured with the first bit erased.

Fig. 8. Comparison of the second bitI -V from two approaches. One is to measureI after the first bit is erased. The second approach is to subtract the fist bitI from the “00” state I .

profiling, we make the following assumptions. First, we assume

that a fresh cell has uniform interface trap density (

) along

the channel [9]. The CP current thus should have a linear

depen-dence on channel position

Fig. 9. Lateral profiling of the programmed charge distribution of the first programmed bit and the secondly programmed bit. A uniform interface trap distribution along the channel is assumed.I in (1) is 195 pA.

Fig. 10. Simulated channel field distribution in second bit programming from 2-D device simulation.x = 0 is at the n source edge and x = 0:4 is at the n drain edge.V = 6:5 V and V = 11 in second bit programming.

where

is defined at the edge of the source or drain

junc-tion.

is the channel length and

denotes the saturated

CP current. The second assumption is that

generation after

one program/erase (P/E) cycle is negligible. Based on these

as-sumptions, the nitride charge distribution is deduced as follows:

(2)

where

is the nitride charge density at the position

,

and

stands for the threshold voltage of a fresh device. Fig. 9

depicts the extracted stored charge distribution of the first

pro-grammed bit and the second propro-grammed bit versus a distance

from the source/drain junction. The stored charges extend into

the channel about tens of nanometers. This result is in agreement

with the simulation in [7]. In addition, the CP measurement

re-sult shows that the second programmed bit exhibits a broader

distribution but a smaller peak density. To explain this result, a

two-dimensional device simulation is performed. A rectangular

charge distribution with a width of 30 nm and a charge density

of 1.6

cm

is used. Fig. 10 shows the lateral channel

electric field distribution in the second bit programming. A large

channel field exists not only in the programmed region but also

in the first bit region (drain side). Such a large field in the first bit

region will accelerate channel electrons from the drain and cause

Fig. 11. Difference inI between program-state and erase-state as a function of drain bias for the first bit and source bias for the second bit. The1I is obtained from Figs. 6 and 7 atV = 1:6 V.

Fig. 12. Difference inI between program state and erase state as a function ofV in CP measurement at various P/E cycle numbers. 1I is measured at V = 1:6 V and is normalized to its value at V = 0 V to take into account interface trap creation in cycling.

earlier hot electron injection into the nitride, thus resulting in a

broader second bit distribution. Finally, we would like to remark

that (2) and consequently Fig. 9 are derived from a simplified

one-dimensional model. For a narrow charge distribution by hot

electron programming, (2) only serves as a first-order

approx-imation. Accurate profiling of programmed charge distribution

requires a more complicated 2-D model.

The programmed charge lateral extent can be also probed by

varying

(or

) in CP measurement. Fig. 11 shows the

dif-ference in

between program state and erase state versus

(or

).

is measured at

V. The second

grammed bit needs a larger junction bias to “mask” the

pro-grammed charge. The same conclusion that the second bit has a

broader charge distribution is obtained.

C. P/E Cycling Stress Effect

The P/E cycling stress effect on programmed charge

distri-bution is examined in Fig. 12 by using the variable

method.

The

window keeps the same during cycling. Again, the

is measured at

V and is normalized to its value at

V to compensate for interface trap creation effect for

dif-ferent cycling stress. It has been reported that hot-carrier stress

Fig. 13. Threshold voltage versus reverse readV for different cycle numbers.

created oxide traps spread toward the channel with stress time

[10], [11]. Such traps, especially positively charged traps, can

effectively lower the Si/

injection barrier [12], [13] and

enhance the electron injection probability. Therefore, as cycle

number (stress time) increases, the hot electron injection region

expands toward the channel due to the spread of the bottom

oxide damaged region. A larger

in CP measurement is

neces-sary to screen programmed charge at a larger cycle number. The

consequence of the broadening of programmed charge

distribu-tion is the degradadistribu-tion of the second bit effect. Fig. 13 shows the

threshold voltage versus

in reverse read for different cycle

numbers. The second bit effect is apparently worsened with

in-creasing cycle number.

IV. C

We have characterized the programmed charge lateral

dis-tribution in a two-bit storage nitride Flash cell by a channel

hot electron program. The CP measurement reveals that the

charge distribution of each bit extends into the channel for tens

of nanometers. This suggests the possibility of further scaling

down the nitride Flash cell with respect to the overlap of two bit

charges. Our paper also shows that the charge distribution of the

second programmed bit is influenced by the stored charge of the

first bit. A broader second bit charge distribution is obtained.

A

The authors would like to thank MXIC, Taiwan, R.O.C. for

providing technical support.

R

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Shaw-Hung Gu was born in Taipei, Taiwan, R.O.C.

on August 11, 1977. He received the B.S. degree from Chang-Gung University, Taoyuan, Taiwan, R.O.C., in 1999, and the M.S. degree in electronics engineering from the National Chiao-Tung Univer-sity, Hsinchu, Taiwan, R.O.C., in 2001. Currently, he is pursuing the Ph.D. degree at the same university.

His research interest focuses on the physics and characterization of nonvolatile memory, especially in nitride-based storage memory and thin oxide relia-bility.

Tahui Wang (S’85–M’86–SM’94) was born in

Tao-Yuan, Taiwan, R.O.C., on May 3, 1958. He received the B.S.E.E. degree from the National Taiwan Uni-versity, Taipei, Taiwan, R.O.C. and the Ph.D. degree in electrical engineering from the University of Illi-nois, Urbana-Champaign, in 1980 and 1985, respec-tively.

From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., where he is currently a Professor. His research interests include hot carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices, and nonvolatile semiconductor devices.

Dr. Wang was granted the Best Teacher Award by the Ministry of Education, Taiwan, R.O.C. He has served as technical committee member of many inter-national conferences, among them IEDM, IRPS, and VLSI-TSA. He was an invited speaker at the 2003 IEDM on the topic of nitride Flash reliability.

cember 20, 1967. He received the B.S. degree in elec-tronics engineering from National Chiao-Tung Uni-versity, Hsinchu, Taiwan, R.O.C. and the M.S. degree in electrical engineering from National Taiwan Uni-versity, Taipei, Taiwan, R.O.C. in 1990 and 1992, re-spectively.

He joined Macronix International Company, Ltd., Hsinchu, Taiwan, R.O.C. in 1994 as a Device Engineer. From 1994 to 1999, he worked on de-vice analysis of nonvolatile memory, especially in floating-gate Flash memory. Since 2000, he has been engaged in the develop-ment of PACAND Flash memory technology, and has accomplished a 0.18 and 0.15m method of delivering. He is presently responsible for the nitrite-based Nbit technology integration at Macronix.

Wenchi Ting received the Ph.D. degree in electrical engineering from the

Uni-versity of Texas at Austin.

He has been involved with developing SRAM, EPROM, EEPROM, Flash, and embedded Flash technologies. He is currently a Senior Director at Macronix International Company, Ltd., Hsinchu, Taiwan, R.O.C., focusing on developing silicon-nitride trapping based nonvolatile memory processes.

Yen-Hui Joseph Ku received the B.S. degree in

electrical engineering from National Cheng-Kung University, Tainan, Taiwan, in 1979, and the M.S. and Ph.D. degrees in electrical and computer engi-neering from the University of Texas at Austin in 1983 and 1988, respectively. His research was on the self-aligned silicide and shallow junction formation for deep submicrometer device application.

In 1987, he joined Rapro Technology, Fremont, CA, as a cofounder with responsibility for RTPCVD reactor design and process development. From 1991 to 1992, he was with Paradigm Technology, San Jose, CA, where he worked on 0.35-m 4-Mb SRAM technology development. In 1992, he joined LSI Logic, Santa Clara, CA, where he worked on advanced logic technology development and served as Integration Manager of the R&D Division until 1997. He later joined the Technology Development Division of Macronix International Company, Ltd., Hsinchu, Taiwan, R.O.C. He currently leads the Technology Development Center and is responsible for the development of advanced nonvolatile memory and embedded SOC technologies. He has published more than 30 papers in technical journals and conferences.

B.S. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1972, and the Ph.D. degree in physics from Columbia University, New York, in 1977.

From 1978 to 1983, he was an Associate Professor and was promoted to Full Professor, National Chiao-Tung University, Hsinchu, Taiwan. In 1983, he was with North Carolina State University, Raleigh, as a Visiting Associate Professor and Adjunct Research Staff Member of the Microelectronic Center of North Carolina (MCNC), Research Triangle Park. In 1984, he joined AT&T Bell Lab-oratories, where he was engaged in very high voltage bipolar-CMOS-DMOS (BCDMOS) IC technology for telecommunication applications, CMOS DRAM technology, laser programmable redundancy, and submicron CMOS ULSI tech-nology. He joined the Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, (ERSO/ITRI) in late 1989 as a Deputy General Director responsible for semiconductor and integrated circuit operation, especially the Grand Submicron Project. This project later successfully devel-oped Taiwan’s first 8-in CMOS submicrometer manufacturing technology with high-density DRAM/SRAM as technology vehicles. In late 1994, he was the Co-founder of Vanguard International Semiconductor Corporation, Hsinchu, which is a spinoff memory IC company from ITRI’s Submicrometer Project. He was the Vice President of Operations, Vice President of Research and Development, and later President from 1994 to 1999. He brought Vanguard from a research and development laboratory to a U.S. $400 million sales company that went IPO in 1998. He is currently Chairman and CEO of Ardentec Corporation, Hsinchu, a VLSI testing service company, and also serves Macronix International Com-pany (MXIC), Ltd., Hsinchu, as a Senior Vice President/CTO. He led MXIC’s technology development team to successfully achieve the state-of-the-art non-volatile memory technology and embedded SoC technology, now, MXIC is the top nonvolatile semiconductor company in Taiwan. He has published more than 100 technical papers and has been granted 123 international patents. He also au-thored more than 30 articles in science education and R&D policy in magazines and newspapers. He served as the President of Science Monthly from 1978 to 1983.

Dr. Lu was the Executive Secretary and Managing Director of the Board and Board Director since 1998 for the Physical Society of Taiwan. from 1981 to 1984. He has been Vice-Chairman and then Chairman of IEEE Electron De-vices Society, Taipei Chapter, from 1991 to 1996, and Board Director and Su-pervisor of IEEE Section since 1996. He is a member of many honor societies, including Sigma Pi Sigma, Phi Tau Phi, and Phi Lambda. He is a life member of the American Physical Society, the Physical Society of ROC, the Chinese Institute of Engineers, and CIE-USA. He received the National Science and Technology Achievement Award from the Prime Minister of Taiwan in 1994. In 1995, he was awarded the National Invention Award, and in 2002, he was awarded the most prestigious semiconductor award in Taiwan—the Pan Wen Yuan Award.