Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold
voltage controllability
Uio-Pu Chiou, Jia-Min Shieh, Chih-Chao Yang, Wen-Hsien Huang, Yo-Tsung Kao, and Fu-Ming Pan
Citation: Applied Physics Letters 103, 203501 (2013); doi: 10.1063/1.4832072 View online: http://dx.doi.org/10.1063/1.4832072
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/103/20?ver=pdfcov Published by the AIP Publishing
Articles you may be interested in
Bonded hydrogen in nanocrystalline silicon photovoltaic materials: Impact on structure and defect density J. Appl. Phys. 110, 064315 (2011); 10.1063/1.3638712
Non-ohmic contact resistance and field-effect mobility in nanocrystalline silicon thin film transistors Appl. Phys. Lett. 93, 163503 (2008); 10.1063/1.2999590
Leakage current mechanisms in top-gate nanocrystalline silicon thin film transistors Appl. Phys. Lett. 92, 083509 (2008); 10.1063/1.2887882
Directly deposited nanocrystalline silicon thin-film transistors with ultra high mobilities Appl. Phys. Lett. 89, 252101 (2006); 10.1063/1.2408630
Microwave thin-film transistors using Si nanomembranes on flexible polymer substrate Appl. Phys. Lett. 89, 212105 (2006); 10.1063/1.2397038
threshold voltage controllability
Uio-Pu Chiou,1Jia-Min Shieh,2,3,a)Chih-Chao Yang,2Wen-Hsien Huang,1,2Yo-Tsung Kao,3 and Fu-Ming Pan1,b)
1
Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan
2
National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan
3
Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan
(Received 18 September 2013; accepted 4 November 2013; published online 14 November 2013) We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (lFE) and adjustable threshold voltages (Vth). The
nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high lFE of 370 cm2/V-s, a steep subthreshold slope of
90 mV/decade, and a low Vthof 0.64 V. When biased with the double-gate driving mode, the
device shows a tunable Vthvalue extending from1 V up to 2.7 V.VC 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4832072]
Power consumption is one of the limiting factors for real-izing high-performance ultimately scaled integrated circuits. Much effort has been done to address this limitation, and in-dependently switched double-gate transistors are considered as one of the most promising solutions for the obstacle.1–3 The double-gate transistor with the independent gate-driving capability can offer flexible controllability in the threshold voltage (Vth) and can achieve a low off-state leakage current
(Ioff) and a high on-state current (Ion) in a single transistor.
Because of the advantages, the double-gate transistor structure has also been implemented in the thin film transistor (TFT) technology to improve the electrical performance of the tran-sistors. For example, Kandoussiet al. demonstrated that the dual-gate hydrogenated microcrystalline silicon (lc-Si:H) TFT structure had an efficient control of Vth.
4
However, the TFT device had poor electrical characteristics, such as field effect mobility (lFE) and subthreshold slope (S.S). To
fabri-cate TFTs with a steep S.S and a high lFE, it is essential to
form the channel layer of low defect density. Therefore, the channel layer should have a high crystallinity for the improve-ment in the device performance of TFTs. Nano-crystalline Si (nc-Si:H) has been widely studied as the channel layer of high performance TFTs because of its tunable crystallinity,5–7high in-situ doping efficiency,8,9 and simple fabrication pro-cess.10,11 Lee et al. reported that nc-Si:H TFTs with the 300 nm-thick channel layer had an ultra-high mobility when the crystallinity of the channel layer reached 85%.12Our pre-vious work used the continuous-wave laser-crystallization (CLC) technique to prepare a highly crystalline channel with a low tail-state density of 3 1019eV1cm3.13 In addition to the high crystallinity of the channel, heavily doped source/ drain (S/D) regions are also important to the device perform-ance of nc-Si:H TFTs. For fabrication of the S/D contacts, ion
implantation is commonly implemented for impurity doping. Metal silicides have also been used as S/D contacts of TFTs to achieve good electrical characteristics.14 However, these fabrication methods require complex processes and, therefore, are not suitable for applications of large-area devices. Moreover, ion implantation can cause lattice damage in the S/D regions, and the succeeding activation process requires a high thermal budget. For applications of flexible or stackable three-dimensional (3D) electronics, low-temperature-pro-cessed TFT technology is desirable. It has been shown that high S/D conductivity and low contact resistance could be realized byin-situ doping in the nc-Si:H thin film with a low thermal budget.9 Our previous study has shown that induc-tively coupled-plasma chemical vapor deposition (ICP-CVD) can produce Si thin films with a defect density as low as 3 1015cm3 as a result of the high density plasma, which enhances the dissociation of reaction precursors.15 Although defects are inevitably formed during the ICP plasma process, the crystallinity of Si thin films can be improved by the intro-duction of inert gases, such as Ar and Kr, in the precursor gas mixture as the diluting gas.16–18The inert gas in the SiH4/H2
plasma can enhance dissociation and ionization of SiH4and
H2, thereby increasing the density of H and SiHn (n¼ 1–3)
radicals and ions.6The ionized inert gas atoms produced in the high density plasma can moderately bombard and thus modify the growing Si thin film, resulting in a better crystal-linity of nc-Si:H grains. In this study, we fabricated in-situ doped nþnc-Si:H TFT devices using ICP-CVD, and integrate the devices into a double-metal-gate structure. During the nc-Si:H deposition, Ar gas was added in the precursor gas mixture to improve the crystallinity of nc-Si:H grains. The double-metal-gate nc-Si:H TFT exhibits a tunable Vthranging
from 1 V up to 2.7 V when it was biased with the double-gate driving mode.
We first fabricated nþnc-Si:H TFTs with a single gate to study the effect of the Ar dilution on the electrical per-formance of the TFT device. The fabrication of the TFT started with the deposition of the in-situ doped nþ nc-Si:H a)
E-mail: [email protected] (or [email protected]). Tel.: 886-3-5726100-7617. Fax: 886-3-5722715.
b)E-mail: [email protected]. Tel.: 886-3-5712121-31322. Fax:
886-3-5724727.
0003-6951/2013/103(20)/203501/5/$30.00 103, 203501-1 VC2013 AIP Publishing LLC
S/D regions on the glass substrate by ICP-CVD using the SiH4/H2/PH3gas mixture as the precursor, which was diluted
by Ar gas with a dilution ratio (RAr¼ [Ar]/[H2]) from 0.15 to
0.5. After the S/D regions were patterned by photolithogra-phy, the intrinsic nc-Si:H channel layer of 100 nm in thick-ness was deposited on the glass plate using the same RAras
the nþnc-Si:H S/D layers and subsequently patterned. The 100 nm-thick SiO2gate dielectric layer was then deposited
on the channel layer, followed by the e-gun evaporation dep-osition and the pattering of a 200 nm-thick Al thin film for the gate electrode. A 300 nm-thick SiO2thin film was used
as the passivation layer to prevent the TFT device from con-tamination, humidity, or degradation. The final process step was to fabricate Al metal pads on the SiO2-passivated TFT
for electrical measurements. For fabrication of the double-metal-gate nc-Si:H TFT, a 150 nm-thick TaN metal layer and a 25 nm-thick SiO2gate dielectric layer were first
depos-ited on the glass substrate, followed by the same fabrication process described above for the single-gate TFT device.
Figure1shows the transfer and output characteristics of the nc-Si:H TFTs with the channel length (L) and width (W) both of 60 lm. Some of the device performance of the TFTs prepared with different RAr values are listed in Table I.
Figure1(a)represents the drain current-gate voltage (Id-Vg)
curves of the TFT operated at the drain voltage (Vd) of 0.1 V.
The S.S becomes steeper and the Vthis lower when the RAris
increased. The device with RAr¼ 0.5 shows better
perform-ance as compared with other devices with other dilution ratios, including a high turn-on current, very low Vth
(0.64 V), a high lFE(370 cm2/V-s), and an extremely low
S.S (90 mV/decade). Figure1(b)shows the output character-istics of the TFTs as a function of the RArat different gate
voltages. It can be clearly seen that the TFT with RAr¼ 0.5
has the largest driving current for all gate voltages. The better performance of the TFT with RAr¼ 0.5 may result from a
higher lFEof charge carriers and the smaller Vth. In general,
better electrical characteristics can be obtained for nc-Si:H TFTs when the crystallinity of the channel layer is improved and the series resistance between the S/D regions and the channel layer is reduced. As described later, the better per-formance of the nc-Si:H TFT with RAr¼ 0.5 can be ascribed
to the low defect density and the low ohmic contact as a result of the efficient in-situ doping during the S/D deposition.
Figure2(a)shows the cross-sectional transmission elec-tron micrograph (TEM) of the double-metal-gate nc-Si:H TFT. For clarity, only part of the nc-Si:H channel layer was shown in the figure. The high resolution TEM (HRTEM) image of a selected area in the channel layer is shown in Fig.
2(b). The marked lattice spacing indicates the presence of crystalline Si nanograins. The HRTEM image clearly shows that, in the channel layer, nanometer-sized Si grains are em-bedded in the amorphous Si (a-Si:H) matrix. Figure 2(c)
shows X-ray diffraction (XRD) spectra of the nc-Si:H chan-nel layer for different RArvalues. The three peaks situated at
28.4, 47.2, and 56 correspond to the (111), (220), and (311) lattice planes of Si, respectively. The Si nano-grains
FIG. 1. (a) Transfer and (b) output characteristics of the top gatein-situ doped nþnc-Si:H TFTs with different Ar dilution ratios. The drain current (Id) versus the gate voltage (Vg) is
plotted at a drain voltage (Vd) of 0.1 V.
Both the channel length (L) and the width (W) are 60 lm.
TABLE I. The device performance of the top gatein-situ doped nþnc-Si:H TFT with different Ar dilution ratios for the deposition of nþand i-nc-Si:H layers.
½Ar=½H2 VthðVÞ S:SðV=decadeÞ lFEðcm2=V sÞ Rc WðMX lmÞ
0.15 1.66 0.18 152 10.7
0.25 1.43 0.11 280 3.62
0.5 0.64 0.09 370 1.07
FIG. 2. (a) Cross-sectional TEM image of the double-metal-gate nc-Si:H TFT; (b) the high resolution TEM image of a selected area of the channel layer shown in (a); (c) XRD spectra of the nc-Si:H channel layer with differ-ent RArratios. (d) Raman spectra of nc-Si:H channel layer for the RAr¼ 0.5.
embedded in the nc-Si:H thin film are about 33 to 43 nm according to Scherer’s formula.19The peak intensity changes insignificantly when RAris increased from 0.15 to 0.5,
indi-cating that the crystallinity of the Si nanograins has a trivial dependence on the Ar dilution ratio.
Figure 2(d)shows the Raman spectrum of the nc-Si:H channel layer prepared with RAr¼ 0.5. The Raman spectrum
can be decomposed into three Gaussian peaks by curve fit-ting.20These three peaks are assigned to the transverse opti-cal (TO) mode of crystalline silicon (520 cm1), defects in the crystalline phase (510 cm1), such as bond dilation at grain boundaries,21 and the a-Si:H phase (480 cm1).22 The crystallinity (Xc) of an nc-Si:H thin film can be estimated in
terms of the intensity of the three Raman peaks. The Xcis
defined by the ratio of the intensity sum of the two peaks at 520 cm1 and at 510 cm1 to the sum of the three peaks.22 From the curve-fitted Raman spectrum, the ICP-CVD depos-ited nc-Si:H channel layer has a crystallinity of 69.3%. The high crystallinity of the channel layer results in a low bulk defect density, reducing carrier scattering and thus promot-ing the lFE. In addition, because the S.S can be decreased by
reducing the bulk defect density of the channel,23 the high crystallinity of the nc-Si:H layer should yield a small S.S for the TFT device. According to Raman spectra of nc-Si:H layers prepared with a RAr< 0.5 (not shown), the change in
RArhas a little effect on the crystallinity of nc-Si:H grains in
the channel layer.
to extract the density of states (DOS) of the nc-Si:H TFT with various Ar dilution ratios. From Fig.3, when the RArincreases
from 0.15 to 0.5, the tail-state density at EEF¼ 0.52 eV
decreases from 6.9 1019to 2.6 1019eV1cm3, where EF
is the midgap energy. The low tail-state density of the nc-Si:H layer is nearly the same as that of our previously reported pol-ycrystalline silicon (poly-Si) TFTs fabricated by CLC method.13 The deep-state density at EEF¼ 0.22 eV also
reduces from 5.69 1017 to 3.57 1016eV1cm3. The tail-state density and the deep-state density of nc-Si:H TFTs are associated with intra-grain defects (Dintra) and grain
boun-daries defects (DGB) in the nc-Si:H layer, respectively.
26
The Dintraof the channel layer is defects present in nc-Si:H grains,
and the DGBis defects formed at the grain boundary between
the a-Si:H matrix and the nc-Si:H. The lower Dintraand DGB
in the nc-Si:H channel layer with a larger RArindicate that the
Ar gas in the plasma during nc-Si:H deposition is beneficial to the reduction of the defect density of the channel layer. A lower tail-state density can enhance the lFE, and a lower
deep-state density can decrease the Vth and the S.S.
26,27
Therefore, the high lFE of 370 cm 2
/V-s and steep S.S of 90 mV/decade of the nc-Si:H TFTs with RAr¼ 0.5 can be
ascribed to the low Dintra and DGB densities, respectively.
Moreover, the hydrogen plasma is useful to passivate the tail--state.26,27During the deposition of the nc-Si:H thin film, the high-density ICP plasma enhances a high dissociation rate of hydrogen gas, resulting in efficient passivation of dangling bonds at grain boundaries.
According to four point probe resistivity measurements, the resistivity of the nþnc-Si:H layer decreases with increas-ing RAr, and the resistivity is as low as 0.09 X-cm for
RAr¼ 0.5. The low resistivity of the nþnc-Si:H layer is due
to the high doping efficiency of the in-situ doping tech-nique.8,9The total resistance (Rtot) from the source to drain
is the series resistance of the channel resistance (RCH) and
the contact resistance (RC).
9,28
Decreasing the Rtot can
improve the carrier mobility. From the output characteristics of the Id-Vdplot, Rtotcan be determined by @Vd/@Idin the
linear regime. The transmission line method28 is used to extract RCH and RC from the plot of Rtot W versus the
channel length at different gate voltages as shown in Fig.
4(a). The RCHis the slope of the plot, and RCis determined
from the intercept with the Y-axis. Figure 4(b) shows the RCH and RC W for the device with a channel length of FIG. 3. The energy distribution of the density of states for the top gate
in-situ doped nþnc-Si:H TFTs with RAr¼ 0.15 and 0.5. For comparison, the
DOS distribution of a CLC-fabricated poly-Si TFT device is also presented.
FIG. 4. (a) The plot of Rtot W versus
the channel length (from 10 to 60 lm) at different gate voltages (from 4 to 10 V); (b) the RCHand RC W for the
nþ nc-Si:H TFT with RAr¼ 0.5 as a
function of the gate voltage. The de-vice had a channel length of 60 lm and was operated at Vd¼ 0.1 V. The inset
shows the RCHand RCof the nc-Si:H
TFT (measured at Vg¼ 10 V) as a
function of RAr.
60 lm and the RAr¼ 0.5 at various gate voltages. The RCH
decreases from 80 to 20 kX and the RC W decreases from
1.39 to 1.07 MX-lm when Vgis increased from 4 to 10 V.
The inset in Fig.4(b) presents the dependence of the RCH
and RCof the nc-Si:H TFT (measured at Vg¼ 10 V) on RAr.
Both the RCHand RC greatly decrease when RAr increases.
When RArincreases from 0.15 to 0.5, RCHdeclines from 90
to 20 kX, and RC W decreases from 10.7 to 1.07 MX-lm.
The low RCHand RCof the nc-Si:H TFT can be ascribed to
the low defect density of the nc-Si:H channel and the S/D layer as revealed by the density of states discussed above. Because of the low channel and S/D contact resistances, both the driving current and the S.S of the nþ nc-Si:H TFT are significantly improved. In combination with the above dis-cussions about the crystallinity determination, defect analy-sis, and resistance measurement, we believe that the better nþ nc-Si:H TFT performance with increasing RAr results
from the lower Rtot, which is a result of a smaller DGB
density.
The nþ nc-Si:H TFT of this work can be further inte-grated into the double-metal-gate stack scheme for additional flexibility in the Vth control. As shown in Fig. 5(a), the
nc-Si:H channel of the double-metal-gate TFT is sandwiched between the bottom and top gate oxides to form the TFT structure with double-gate electrodes. The double-metal-gate structure consists of a sputter-deposited TaN bottom gate (g2) and a top E-gun-evaporation-deposited Al gate (g1). The g1 and g2 are used as the driving gate and the Vth-control gate,
respectively. The use of metal as the gate material has advan-tages of avoiding poly-Si depletion effect and improving the drive current when the device is scaled down beyond 45 nm node. In addition, the fabrication process of metal gates gen-erally requires a thermal budget lower than that of poly-Si gates. The low temperature nc-Si:H channel technology is therefore compatible with the fabrication of the metal gates for the double-metal-gate nc-Si:H TFT. Figure 5(b) shows the Id-Vg1 characteristics of the double-metal-gate nc-Si:H
TFT as a function of the back gate voltage (Vg2). The Id
ver-sus Vg1curves were measured at Vd¼ 0.1 V and the Vg2
var-ied from1 to 4 V. Figure 5(c) shows that the Vth of the
device can be adjusted more positively or negatively by changing the bottom gate bias Vg2. Therefore, the
double-me-tal-gate TFT can be free from the floating body effect. Also shown in Fig.5(c)is the back-gate-effect factor c,1,29which is defined byjDVthðg1Þ=DVg2j. The calculated c values of the double-metal-gate nc-Si:H TFT are in the range between 0.35 and 0.9. These values are comparable to the double-gate
MOSFET that has a poly-Si channel.1,30 This indicates that the Vthof the g1 of the device can be effectively modulated
by the back gate bias Vg2. Masaharaet al. have proposed a
linear potential distribution model to explain the back-gate effect on the Vthmodulation for double-gate devices.
1
In the case of the double-metal-gate nc-Si:H TFT, when the back gate is biased negatively, the nc-Si:H channel surface near the g2 is essentially depleted. As the device is turned on by Vg1, conducting carriers are mainly induced near the g1 side;
the narrow conduction path results in a low channel current. When inversion occurs near the side of the positively biased g2, a larger Vg2leads to a lower Vthvalue and a higher
chan-nel current. A small change in the Vg2 will cause a large
potential change at the g1 side,1resulting in a higher c and the better Vth-controllability by the back gate bias Vg2.
Because of the merits described above, the double-metal-gate nc-Si:H TFT technology with the tunable Vth capability is
very promising for applications in low power circuits.1,29For example, in the standby mode, a lower leakage current can be achieved by raising the Vth of the transistors. While in the
active mode, the Vthcan be adjusted to a lower value to
pro-vide sufficient driving current. Moreover, due to the very low process temperature, the double-metal-gate nc-Si:H TFT technology is suitable for future 3D electronics.31
In conclusion, we have fabricated a top gatein-situ dop-ing nþnc-Si:H TFT on the glass substrate using ICP-CVD. By varying the Ar dilution ratio, we can prepare nc-Si:H channel layers of low grain boundary defect density. In com-bination with thein-situ doped nc-Si:H S/D layer of low re-sistivity, the device exhibits a high lFE of 370 cm
2
/V-s and an extremely low S.S of 90 mV/decade. We also integrated the nc-Si:H TFT technology with the double-metal-gate structure to obtain additional flexibility in the Vth control.
The double-metal-gate nc-Si:H TFT exhibits tunable Vth
varying from 1.0 V up to 2.7 V with the back-gate-effect factor c in the range between 0.35 and 0.9. This technique is suitable for the application of future 3D electronics, which require transistors of high efficiency, low cost, and low oper-ation voltage.
The authors thank the National Science Council of the Republic of China for the financial support.
1M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T.
Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki,IEEE Trans. Electron Devices52, 2046 (2005).
FIG. 5. (a) The schematic structure of the double-metal-gate nc-Si:H TFT; (b) transfer characteristics of the de-vice. Vg1is the driving gate and Vg2is
the Vth-control gate; (c) the extracted
Vthof g1 and the back-gate-effect
fac-tor c as a function of Vg2.
Takashima, H. Yamauchi, and E. Suzuki, Tech. Dig.-Int. Electron Devices Meet. 2003, 986.
4
K. Kandoussi, E. Jacques, N. Coulon, C. Simon, and T. M. Brahim, Solid-State Electron.63, 140 (2011).
5D. Raha and D. Das,Sol. Energy Mater. Sol. Cells95, 3181 (2011). 6
H. P. Zhou, D. Y. Wei, S. Xu, S. Q. Xiao, L. X. Xu, S. Y. Huang, Y. N. Guo, W. S. Yan, and M. Xu,J. Appl. Phys.110, 023517 (2011).
7
M. Moreno, R. Boubekri, and P. R. i Cabarrocas,Sol. Energy Mater. Sol. Cells100, 16 (2012).
8C. H. Lee, D. Striakhilev, and A. Nathan,J. Vac. Sci. Technol. A
22, 991 (2004).
9
I. C. Cheng, S. Wanger, and E. V. Sauvain,IEEE Trans. Electron Devices
55, 973 (2008).
10M. Marinkovic, E. Hashem, K. Y. Chan, A. Gordijn, H. Stiebig, and D.
Knipp,Appl. Phys. Lett.97, 073502 (2010).
11
S. M. Han, S. J. Kim, J. H. Park, S. H. Choi, and M. K. Han,J. Non-Cryst. Solids354, 2268 (2008).
12C. H. Lee, A. Sazonov, A. Nathan, and J. Robertson,Appl. Phys. Lett.
89, 252101 (2006).
13
Y. T. Lin, C. Chen, J. M. Shieh, Y. J. Lee, C. L. Pan, C. W. Cheng, J. T. Peng, and C. W. Chao,Appl. Phys. Lett.88, 233511 (2006).
14X. Zhang, Ivana, H. X. Guo, X. Gong, Q. Zhou, and Y.-C. Yeo, J. Electrochem. Soc.159, H511 (2012).
15
C. H. Shen, J. M. Shieh, J. Y. Huang, H. C. Kuo, C. W. Hsu, B. T. Dai, C. T. Lee, C. L. Pan, and F. L. Yang,Appl. Phys. Lett.99, 033510 (2011).
16K. Bhattacharya and D. Das,Nanotechnology
18, 415704 (2007).
91, 111501 (2007).
19H. P. Klug and L. E. Alexander, X-Ray Diffraction Procedures: For
Polycrystalline and Amorphous Materials, 2nd ed. (Wiley-Interscience, 1974).
20C. Smit, R. A. C. M. M. van Swaaij, H. Donker, A. M. H. N. Petit, W. M.
M. Kessels, and M. C. M. van de Sanden,J. Appl. Phys.94, 3582 (2003).
21
S. Veprek, F. A. Sarott, and Z. Iqbal,Phys. Rev. B36, 3344 (1987).
22
S. Q. Xiao, S. Xu, D. Y. Wei, S. Y. Huang, H. P. Zhou, and Y. Xu,
J. Appl. Phys.108, 113520 (2010).
23D. W. Greve,Field Effect Devices and Applications: Devices for Portable,
Low-Power, and Imaging Systems, 1st ed. (Prentice-Hall, 1998).
24
T. Suzuki, Y. Osaka, and M. Hirose,Jpn. J. Appl. Phys., Part 221, L159 (1982).
25G. Fortunato and P. Migliorato,Appl. Phys. Lett.
49, 1025 (1986).
26
K. Y. Choi, J. S. Yoo, M. K. Han, and Y. S. Kim,Jpn. J. Appl. Phys., Part 135, 915 (1996).
27I. W. Wu, T. Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang,IEEE Electron Device Lett.12, 181 (1991).
28
S. Luan and G. W. Neudeck,J. Appl. Phys.72, 766 (1992).
29
T. Ohtou, T. Nagumo, and T. Hiramoto,Jpn. J. Appl. Phys., Part 143, 3311 (2004).
30S. Zhang, R. Han, J. K. O. Sin, and M. Chan, IEEE Trans. Electron Devices49, 718 (2002).
31
Y. C. Lien, J. M. Shieh, W. H. Huang, W. S. Hsieh, C. H. Tu, C. Wang, C. H. Shen, T. H. Chou, M. C. Chen, J. Y. Huang, C. L. Pan, Y. C. Lai, C. Hu, and F. L. Yang, Tech. Dig.-Int. Electron Devices Meet. 2012, 801.
