IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 2, FEBRUARY 2005 81
Germanium pMOSFETs With Schottky-Barrier
Germanide S/D, High-
Gate Dielectric
and Metal Gate
Shiyang Zhu, Member, IEEE, Rui Li, S. J. Lee, Member, IEEE, M. F. Li, Senior Member, IEEE, Anyan Du, Jagar Singh,
Chunxiang Zhu, Member, IEEE, Albert Chin, Senior Member, IEEE, and D. L. Kwong, Senior Member, IEEE
Abstract—Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN–TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as 5 times due to the lower hole Schottky barrier of the NiGe–Ge contact than that of PtSi–Si contact as well as the higher mobility of Ge channel than that of Si. Index Terms—Germanium, high- , metal gate, MOSFET, Schottky.
I. INTRODUCTION
G
ERMANIUM is an attractive channel material due to its high low-field carrier mobility. Germanium p-channel MOSFETs with enhanced mobility have been demonstrated using germanium oxynitride, ZrO , Al O and HfO as the gate dielectric [1]–[4]. Another technology bottleneck for future scaling of MOSFET is the fabrication of ultra-shallow source/drain (S/D) with low series resistance [5]. A Schottky-barrier S/D transistor (SSDT) structure has been proposed to solve this problem [6], [7]. However, an SSDT is difficult to use to achieve high drive current due to the relatively high potential barrier (Schottky barrier) between the source and the channel [8]. This problem may be overcome, or at least alleviated, by using a Ge substrate because of the low Schottky-barrier height of germanide–Ge contact and the high carrier mobility of Ge. In this letter, p-channel SSDTs with HfAlO gate dielectrics, HfN–TaN metal gates, and NiGe S/Ds are demonstrated for the first time using a simplifiedManuscript received October 26, 2004; revised November 17, 2004. The re-view of this letter was arranged by Editor B. Yu.
S. Zhu is with the Silicon Nano Device Laboratory, Department of Elec-trical and Computer Engineering, National University of Singapore, Singapore 119260, and also with the Department of Microelectronics, Fudan University, Shanghai 200433, China.
R. Lui, S. J. Lee, and C. Zhu are with the Silicon Nano Device Laboratory, De-partment of Electrical and Computer Engineering, National University of Sin-gapore, Singapore 119260.
M. F. Li is with the Silicon Nano Device Laboratory, Department of Elec-trical and Computer Engineering, National University of Singapore, Singapore 119260, and also with the Institute of Microelectronics, Singapore 117685 (e-mail: [email protected]).
A. Du and J. Singh are with the Institute of Microelectronics, Singapore 117685.
A. Chin is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
D. L. Kwong is with the Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712 USA.
Digital Object Identifier 10.1109/LED.2004.841462
low-temperature process. The highest temperature in the entire fabrication process was 600 C.
II. MOS DEVICEFABRICATION
The starting substrates are N-type Ge (100) wafers with a re-sistivity of cm. After cleaning in a diluted HNO solu-tion and dipping in a diluted HF (DHF) solusolu-tion, the wafers were loaded in a metal–organic chemical vapor deposition system and annealed in pure NH ambient at 600 C for 30 s for surface nitridation. Then 6 nm HfAlO was deposited at 400 C, fol-lowed by an in situ annealing in N ambient at 600 C for 1 min. The wafers were transferred into a sputtering system with a base pressure of torr. HfN ( 50 nm) and TaN ( 100 nm) were deposited sequentially at room temperature as a metal gate electrode [9]. The deposited wafers were patterned using conventional photolithography and reactive ion etching procedures. Immediately after dipping in the DHF solution to re-move the remaining HfAlO film in the S/D region, the patterned wafers were loaded in the sputtering system again and a Ni film of 100 nm was deposited. Because HfN can be etched by DHF, but TaN cannot, a “hole” between S/D and gate was formed due to the lateral etching of the HfN layer of the HfN–TaN gate stack during the DHF dipping, which acts as a spacer to separate the gate and S/D [10], [11]. Each transistor was surrounded by a guard ring, thus can be electrically separated from other de-vices, as shown in the inset of Fig. 4. The Ni germanidation was performed by rapid thermal annealing (RTA) at 600 C for 1 min. Then, unreacted Ni was removed by wet etching in RCA1 (NH OH : H O : H O : 2 : 5) solution. Because both the NiGe and Ge substrates will be attacked by the RCA1 solution slowly, the selective etching time should be carefully optimized.
III. DEVICECHARACTERIZATION ANDDISCUSSION
Fig. 1 shows the gate capacitance–voltage (C–V) char-acteristics measured at 1 MHz as well as the cross-sec-tional transmission electron microscope (TEM) image of the TaN–HfN–HfAlO–n-Ge(100) gate stack of the final PSSDT. The TEM picture shows smooth interface between HfAlO and Ge substrate and the physical thickness of the amorphous HfAlO film is 5 nm. However, the equivalent SiO thickness (EOT) extracted from the accumulation capacitances is 3.8 nm. The well-behaved C–V with small hysteresis of 18 mV was observed with no significant frequency dispersion, implying that HfAlO is a potential gate dielectric for Ge MOSFETs.
82 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 2, FEBRUARY 2005
Fig. 1. Capacitance measured at 1 MHz on the fully processed Ge-PSSDT. Inset shows the cross-sectional TEM image of the TaN–HfN-HfAlO =n–Ge(100) stack.
Fig. 2 shows the measured current–voltage (I–V) curve of the Schottky diode with NiGe–n-Ge(100) contact and its cross-sec-tional TEM image. The tradicross-sec-tional thermionic emission (TE) model [12] was used to fit the experimental forward current I–V data, from which apparent Schottky-barrier height , ide-ality factor (n) and series resistance were extracted to be 0.50 eV, 1.49 and 110 , respectively. The corresponding hole barrier height can be calculated to be 0.16 eV, assuming that the sum of electron and hole barrier heights approximately equals to the Ge gap energy ( 0.66 eV). The reverse leakage current of the Schottky diode at 1 V is . The value is reasonable in view of germanide–Ge Schottky con-tact [13]. The NiGe layer has a thickness of 140 nm, thinner than the expected thickness of 250 nm if the deposited Ni (100 nm) is completely reacted with Ge to form NiGe due to the par-tially etching of NiGe by the RCA1 solution during the selective etching process. The TEM image shows that there is an interme-diate layer between NiGe and Ge substrate with a quite rough interface between the intermediate layer and Ge substrate. En-ergy dispersive X-ray (EDX) analysis shows that this interme-diate layer is a Ge-rich NiGe layer. This may be the main reason for the significantly large ideality factor, the relatively high re-verse leakage current and the low apparent barrier height of the NiGe–n-Ge diode compared with the reported value [13]. It is expected that the rectifying property of the NiGe–Ge contact can be improved by reducing this intermediate layer.
Fig. 3 shows the – curves of Ge-PSSDT with channel width/length m. The threshold voltage is 0.41 V from the linear fitting of the curve at V. The drain current of the device at – V is
m. For comparison, control silicon PSSDTs with PtSi S/D were also fabricated using the similar process and same de-vice size [10], [11], their – curves are also shown in Fig. 3. For the control Si PSSDT, EOT nm, V and the drain current at – V is m. Therefore, the Ge device has larger drain drivability
Fig. 2. I–V curves of the NiGe–n-Ge(100) diode, the solid line is a fitting curve based on the TE model. Inset is the cross-sectional TEM image of the NiGe–n-Ge(100) contact.
Fig. 3. I –V curves of the Ge-PSSDT with NiGe S/D. The channel width and length are 400 and 8m, EOT = 3:8 nm, V = 00:41 V. For comparison, theI –V curves of corresponding Si-PSSDT with PtSi S/D are also shown (dotted lines), which has the same size and EOT= 2:0 nm, V = 00:50 V.
than the Si counterpart if they are scaled to the same EOT. Al-though the drive current improvement can be partly attributed to the fact that Ge has higher hole mobility than Si, the main reason is believed due to the smaller hole barrier between source and channel of Ge-PSSDT ( 0.16 eV) than that of Si-PSSDT ( for PtSi/Si [11], [14]). In the case of Si-PSSDT, it is probably difficult to reach the hole barrier height as low as that of Ge [15] because of the large hole band-offset (0.4 eV) or difference of valence electron ionization energy (0.2 eV) between Ge and Si [16]. This is one of the major motivations of Ge-PSSDT. Fig. 4 shows the – curves of Ge-PSSDT. It shows relatively large off-state current, . The ratio is , about five orders of magnitude smaller than that of Si-PSSDT. The large is mainly caused by the relatively low electron barrier height ( , 0.5 eV in our experiment) at the drain/substrate contact that forms a reverse-biased NiGe–n-Ge
ZHU et al.: GERMANIUM p-MOSFETs WITH SCHOTTKY-BARRIER GERMANIDE S/D 83
Fig. 4. I –V curves of the Ge-PSSDT with NiGe S/D, V are 00.1, 00.2, and01 V, respectively. The I =I ratio reaches10 10 . The inset shows schematics of the device layer and cross-sectional structure.
diode. The reverse saturation current of the contact with an area of cm is calculated to be , close to the value of in Fig. 4. Conventional Ge MOSFET with p–n junc-tion S/D suffers from the same problem because the narrow gap energy of Ge also results in large p–n junction leakage [1]–[4]. The large can be effectively reduced by using ultrathin ger-manium on insulator substrate [3] because the contact area can be dramatically reduced.
It has been pointed out that Schottky-barrier heights of metals and germanides on n-Ge are pinned at between 0.54 and 0.61 eV over a wide range of metal work function [13]. Erbium ger-manide (ErGe) was also used to fabricate Ge-PSSDTs in our experiment and show similar electrical characteristics as dis-played in Figs. 3 and 4. The quality of the NiGe film and the NiGe–Ge interface is sensitive to the annealing condition. Fur-nace annealing at 420 C results in poorer rectifying property than that after RTA. However, very few data have been reported in the literature about the formation of germanide by solid-state reaction as well as the Schottky-barrier properties of various metal–Ge or germanide–Ge contacts. Systematically studies are still on-going in order to improve the quality of germanide–Ge contact by optimizing the fabrication parameters.
In conclusion, the first germanium PSSDT with HfAlO gate dielectric, HfN/TaN metal gate and NiGe S/D was fabricated using a simplified low temperature process. The drive current is about 4.8 larger than that of the silicon counterpart due to
the high hole mobility of Ge and the low hole Schottky-barrier height of the germanide–Ge contact.
REFERENCES
[1] S. C. Martin, L. M. Hitt, and J. J. Rosenberg, “P-channel germanium MOSFETs with high channel mobility,” IEEE Electron Device Lett., vol. 10, no. 7, pp. 325–326, Jul. 1989.
[2] C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400 C germanium MOSFET technology with high- dielectric and metal gate,” in IEDM Tech. Dig., 2002, pp. 437–440. [3] D. S. Yu, C. H. Huang, A. Chin, C. Zhu, M. F. Li, B. J. Cho, and D.
L. Kwong, “Al O –Ge-on-insulator n- and p-MOSFETs with filly NiSi and NiGe dual gates,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 138–140, Mar. 2004.
[4] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO gate dielectrics and TaN gate electrode,” in IEDM Tech. Dig., 2003, pp. 433–436.
[5] C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, “Activation and diffusion studies of ion-implanted p and n dopants in germanium,” Appl. Phys. Lett., vol. 83, pp. 3275–3277, 2003. [6] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect transistor using Schottky-barrier contacts for source and drain,” Proc. IEEE, vol. 56, pp. 1400–1401, 1968.
[7] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. J. King, and C. H. Hu, “Complementary silicide source/drain thin-body MOSFETs for the 20-nm gate length regime,” in IEDM Tech. Dig., 2000, pp. 57–60. [8] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of
short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstra-tion of sub-50-nm n-type devices with metal gate,” Jpn. J. Appl. Phys., vol. 38, pp. 6226–6231, 1999.
[9] H. Y. Yu, J. F. Kang, J. D. Chen, C. Ren, Y. T. Hou, S. J. Whang, M. F. Li, D. S. H. Chan, K. L. Bera, C. H. Tung, A. Du, and D. L. Kwong, “Robust high qualityHfN=HfO gate stack for advanced CMOS devices,” IEEE Electron Device Lett., vol. 25, no. 2, pp. 70–72, Feb. 2004.
[10] S. Y. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, “Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode,” IEEE Electron Device Lett., vol. 25, no. 5, pp. 268–270, May 2004.
[11] S. Y. Zhu, H. Y. Yu, J. D. Chen, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, “Low temperature MOSFET technology with Schottky-barrier source/drain, high- gate dielectric and metal gate elec-trode,” Solid State Electron., vol. 48, pp. 1987–1992, 2004.
[12] S. Y. Zhu, R. L. Van Meirhaeghe, S. Forment, G. P. Ru, and B. Z. Li, “Effects of the annealing temperature on Ni silicide–n-Si(100) Schottky contacts,” Solid State Electron., vol. 48, pp. 29–35, 2004.
[13] C. C. Han, E. D. Marshall, F. Fang, L. C. Wang, S. S. Lau, and D. Voreades, “Barrier height modification of metal/germanium Schottky diodes,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 6, no. 6, pp. 1662–1666, 1988.
[14] V. W. L. Chin, M. A. Green, and J. W. V. Storey, “Current transport mechanisms studied by I–V-T and IR photoemission measurements on a p-doped PtSi Schottky diode,” Solid State Electron., vol. 36, no. 8, pp. 1107–1116, 1993.
[15] E. H. Rhoderick and R. H. Williams, Metal-Semiconductor Contacts, 2nd ed. Oxford, U.K.: Clarendon, 1988.
[16] W. A. Harrison, Electronic Structure and the Properties of Solids. San Francisco, CA: Freeman, 1980.
