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2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.
Low Distortion and Swing Suppression Sigma-Delta Modulator with Extended Dynamic
Range Scheme
JEN-SHIUN CHIANG1, TENG-HUNG CHANG2 AND PAO-CHU CHOU1
1Department of Electrical Engineering, Tamkang University, Tamsui, Taipei, Taiwan 2Department of Electrical and Control Engineering, National Chiao Tung University, Taiwan
E-mail: chiang@ee.tku.edu.tw; thchang.ece91g@nctu.edu.tw; pcchou@ee.tku.edu.tw
Received July 25, 2003; Revised February 20, 2004; Accepted October 19, 2004
Abstract. This work presents a new low distortion and swing suppression second order sigma-delta modulator with extended dynamic range scheme. The proposed modulator is based on the dual-quantizer architecture and can effectively extend the dynamic range by only adding two simple digital filters in the digital circuit. The techniques of low distortion and swing suppression integrator designs are also employed in the new architecture. Accordingly, this new architecture can improve the circuitry nonlinearity, and the in-band noise can be significantly suppressed to achieve a high resolution in mid or wide bandwidth applications. A second order SDM for Bluetooth application with bandwidth of 500 KHz and sampling frequency of 40 MHz was designed and implemented. The peak SNDR of the experimental SDM is 78 dB.
Key Words: analog-to-digital converter, blind on-line calibration, dual-quantizer, dynamic range, low distortion, sigma-delta modulator, swing suppression, wide bandwidth
1. Introduction
The oversampling sigma-delta analog-to-digital con-verters (ADCs) have significantly impacted appli-cations in communiappli-cations, measurement, and data-acquisition, due to their ability to deliver high res-olution from untrimmed analog circuits with mod-est complexity [1]. Importantly, sigma-delta modula-tor (SDM) ADCs can achieve high-resolution signal conversion without high precision component match-ing, as required by the conventional signal converters such as flash type A/D converters or those A/D convert-ers based on sub-ranging or successive approximation techniques [1]. However, the sigma-delta modulators are normally limited to low or mid bandwidth appli-cations due to their over-sampling nature. Sigma-delta modulation can be designed by several types of archi-tectures such as single-loop, cascaded, feed-forward summation [2], distributed feedback, . . . , etc. [1].
With the improvement of VLSI technologies, SDM is becoming attractive for use in mid or wide bandwidth applications, such as xDSL modems and wireless wide-band transceivers. However, at the low oversampling
ratio (OSR) required for such applications, the SDMs are increasingly sensitive to circuit imperfections, and thus require high-order or multi-bit architectures [1]. In this work, a new second order sigma-delta mod-ulator with extended dynamic range (DR) scheme is proposed. This architecture is accomplished by a dual-quantizer approach [3]. The dual-quantizers are in multi-bit architecture, but the feedback of the SDM is a single bit DAC (digital-to-analog converter). The analog cir-cuit complexity and imperfections of this architecture can be effectively improved to the same performance as that of the multi-bit architecture. The technique is applicable even for low OSR SDMs and can simplify the circuit implementation. Moreover, the techniques of low-distortion and swing-suppression integrator de-sign are also proposed. According to the simulation re-sults, this new SDM architecture is well suited for wide bandwidth applications such as Bluetooth, xDSL and others. A SDM for Bluetooth application with band-width of 500 KHz and sampling frequency of 40 MHz was designed and implemented to verify the proposed architecture. The performance of the designed SDM is as expected.
2 1 1 1 − − −z z 1 1 1 − − −z z E(z) I1(z) I2(z) Y(z) U(z) Q1(z)
Fig. 1. The conventional topology of a second-order SDM.
The rest of this paper is organized as follows. Section 2 describes the conventional SDM architec-ture. Section 3 introduces the proposed SDM archi-tecture. Section 4 then presents the circuit design of the proposed SDM architecture. Section 5 presents the comparisons and simulation results. Conclusions are fi-nally made in Section 6. The digital correction method, digital blind on-line calibration technique, is described in Appendix A.
2. Conventional Sigma-Delta Modulators
2.1. Distortion in the Conventional Topology Figure 1 shows the topology of a conventional second-order SDM. In this architecture, the linear model of the SDM includes two inputs. One is the actual input U (z), and the other is the quantization noise, Q1(z). Two
transfer functions, the signal transfer function (STF) and the noise transfer function (NTF), are given by
Y (z)= U(z)STF + Q1(z)NTF, (1)
where STF= z−2and NTF= (1 − z−1)2. However, in
practice, the transfer function of the integrator is differ-ent from (1) due to the influence of the non-idealities of the electrical implementation. Considering the imple-mentation by the leaky integrators, the transfer function with finite amplifier dc gain is given by
H (z)= 1
1− (1 − µ)z−1, (2)
whereµ = 1/Avand Avis the finite amplifier dc gain. For this case the transfer function of the output of the second-order sigma-delta modulator becomes
approx-imately
Y (z) ∼= z−2X (z)+ [(1 − z−1)2+ 2µz−1(1− z−1)
+ µ2z−2]Q
1(z). (3)
In the bracket, the first term is an ideal second-order shaped function; the second term is the first order shaped error, and the third term is the unshaped quan-tization error. The second and third terms are extra quantization errors, and the extra quantization power,
PQ(µ), is injected into the SDM. The resulting
base-band quantization noise power can be expressed as
PQ(µ) = PQ+ PQ(µ) ∼ = 2 12 π4 5(OSR)5 + 2µ2π2 3(OSR)3 + µ4 (OSR) . (4) The factor, OSR, is oversampling ratio, and equals the difference between the two adjacent quantization levels. The extra error term,PQ(µ), depends on µ and
grows with the order of the modulator. In order to re-duce the nonlinearity distortion, a high OSR is usually applied in this architecture to minimize the PQ(µ)
effects, and therefore the input signal bandwidth is re-stricted to low or mid bandwidth applications. 2.2. Integrator Output Swing in the Conventional
Topology
A large amplitude signal, which is the sum of the input signal and quantization noise, is usually integrated into the integrator of the oversampling SDM. The large out-put swings of the integrator may not only cause the non-linearity of the opamp but also limit the power supply
Fig. 2. The proposed topology of a second-order SDM.
voltage of the analog circuit. Scaling techniques have been proposed to overcome this problem [1], but these techniques also reduce the dynamic range of the mod-ulator. In this work, a swing suppression topology is proposed to improve these problems.
2.3. Wideband Architecture in the Conventional Topology
By the continuing advancement of the VLSI tech-nology, the SDM is attempted to be applied in wide bandwidth applications [4–7]. Due to the low OSR requirement of the wideband applications, both the order of the modulator and the bit number of the in-ternal quantizer have to be increased to achieve the desired resolution in the desired frequency band. The architectures of high-order single-bit, low-order multi-bit, or MASH may solve this problem [1]. However, the complexity of the analog circuit and the stabil-ity problems limit the performance of the high-order single-loop architecture. In the low-order multi-bit ar-chitecture, the DAC mismatch seriously degrades the overall performance and the dynamic element match-ing technique is applied to improve this degradation. The MASH architecture can cascade several low-order stages to achieve high-order performance, but the im-perfect cancellation between analog and digital circuits may cause the leakage noise to degrade the perfor-mance. In this work, a dual quantizer architecture is proposed. By our approach, a one-bit DAC is used in the feedback loop, and thus the multi-bit DAC mis-match problems are avoided but the performance is still good enough. The details are discussed in next section.
3. Proposed Topology
Figure 2 shows the proposed second-order dual quan-tizer SDM and it is similar to the architecture proposed by Silva and Temes [8]. In this SDM, the transfer func-tions of the two integrators are different. The first in-tegrator is a conventional inin-tegrator, but the transfer function of the second integrator is1−z1−1. In this topol-ogy, the gains of the forward paths are unity, and there-fore the value of capacitors is less than Silva’s topol-ogy in [8]. Besides the two integrators, there are two quantizers, the low-bit quantizer Q1(z) and the
high-bit quantizer Q2(z). H1(z) and H2(z) are digital filters,
H1(z) = z−1 and H2(z) = (1 − z−1)2, and they are
used to extend the dynamic range. The details of Q1(z),
Q2(z), H1(z), and H2(z) are discussed in the following
subsections.
3.1. Proposed Low-Distortion Topology
Figure 1 shows a conventional second order SDM, how-ever as mentioned in Section 2.1 it has serious non-linearity distortion problems. In order to overcome the nonlinearity distortion problems, a high OSR is usually applied in this architecture, and therefore it is restricted to low or mid bandwidth applications. When carefully analyzing the signal flows of Fig. 1, we can find the er-ror signal E(z) is the difference between the input sig-nal U (z) and output sigsig-nal Y (z), and the noise-shaping mechanism of Fig. 1 tries to minimize the difference in the desired frequency band. The STF is a delay version of the input signal and it causes E(z) to restore the inte-grator outputs, I1(z) and I2(z) . When the effects of the
nonlinear amplifier DC-gain, slew rate limitation, and incomplete setting noise are considered, the harmonic
components of the input signal can be created at the integration outputs, I1(z) and I2(z) [8]. Medeiro and
Perez-Verdu [9] reported that the non-linear amplifier open-loop gain, Av, whose dependency on the output voltage (v) could be approximated by a polynomial function, Av = A0(1+ γ1v + γ2v2+ · · ·). Where A0
is the dc gain with zero output voltage,γ1 andγ2 are
the first and second order deviating coefficients respec-tively. Thus, the harmonic distortion of the SC integra-tor caused by a nonlinear dc gain can be modified as [9] vo(n) ∼= vo(n−1) + g1 vi(n− 1) − vi(n− 1) + vo(n) A0 + γ1vo(n) vi(n− 1) + vo(n) A0 + γ2vo2(n) vi(n− 1) + vo(n) A0 , (5)
wherevi andvoare the input and output of the SC
in-tegrator respectively. The equivalent distortion at the integrator input can be estimated by analyzing the har-monics in brackets in (5). If the input and output of the integrator are approximated by their first harmonic,
vi ∼= Visin(2π fbnTS) vo∼= Vocos(2π fbnTS) (6)
where fb is the frequency of the input and TS is the
sampling period. Substituting the expressions in (5) and performing a Fourier series expansion of those terms in the bracket, the amplitudes of the second and third harmonics referred to the integrator input are [9]:
AH,2= |γ1| 2 A0 Vo Vi2+ Vo2 AH,3= |γ2| 4 A0 Vo2 V2 i + Vo2 (7)
According to equations (7), the harmonic distortion grows with the amplitudes of Viand Vo. For this reason
the input signal U (z) can be cancelled out from I1(z)
and I2(z), and this can reduce the output swing of the
integrator. Therefore, the amplitudes of Vi and Vocan
also be minimized to reduce the harmonic distortions. Based on this function, a new SDM architecture is pro-posed and is shown in Fig. 2. The STF and NTF of this SDM are given as follows:
STF(z)= 1, (8)
NTF(z)= (1 − z−1)2. (9)
Under this architecture, the STF is unaffected, but the integrators only process the quantization noises, and the performance requirements of the integrators can be significantly relaxed. Both Figs. 1 and 2 are simu-lated with a sampling frequency of 40 MHz and the input signal is a sine wave of frequency 200 KHz
with −6 dB amplitude and two 2-bit quantizers are
used. Figure 3 shows the spectra of I1(z) and I2(z) of
both architectures. Obviously the distortions in I1(z)
and I2(z) of the proposed architecture are reduced
significantly.
3.2. The Proposed Swing-Suppression Topology The proposed architecture has the characteristic of swing suppression. As discussed in Section 2.2, the integrator output swing should be reduced to avoid the nonlinearity and overload in the low power supply volt-age SDM. The transfer functions of I1(z) and I2(z) in
Fig. 1 are expressed as [10]:
I1(z)= (1 − z−1)z−1U (z)+ (1 − z−1)z−1Q1(z),
(10) and
I2(z)= z−2U (z)+ (−2z−1+ z−2)Q1(z). (11)
Furthermore, the transfer functions of I1(z) and I2(z)
in Fig. 2 are derived as:
I1(z)= −(1 − z−1)z−1Q1(z), (12)
and
I2(z)= −z−1Q1(z). (13)
From equations (10) to (13), I1(z) and I2(z)
(equa-tions (10) and (11)) of Fig. 1 contain both input signal,
U (z), and quantization noise, Q1(z), but I1(z) and I2(z)
(equations (12) and (13)) of Fig. 2 contain only quan-tization noise, Q1(z). Therefore, the integrator output
swings of the proposed architecture are smaller than that of the conventional one. The simulated integra-tor output waveforms of both the proposed and con-ventional architectures, with a sampling frequency of 40 MHz, a 100 KHz sine wave input with−6 dB ampli-tude, and with 2-bit quantizers and DAC, are shown in
104 105 106 107 -120 -100 -80 -60 -40 -20 0 F FT(I 1 ), d B Conventional topology 104 105 106 107 -120 -100 -80 -60 -40 -20 0 F FT(I 1 ), d B P roposed topology 104 105 106 107 -120 -100 -80 -60 -40 -20 0 Frequence,Hz FFT (I 2 ), d B 104 105 106 107 -120 -100 -80 -60 -40 -20 0 Frequence,Hz FFT (I 2 ), d B
Fig. 3. Distortion simulation of the traditional and proposed architectures.
0 0.5 1 1.5 x 10-5 -0.5 0 0.5 1s t i n te gr at or o u tput
The output swing of proposed architecture
0 0.5 1 1.5
x 10-5 -1
0 1
The output swing of conventional architecture
0 0.5 1 1.5 x 10-5 -0.5 0 0.5 Th e 2nd in te gr a to r o u tput 0 0.5 1 1.5 x 10-5 -1 0 1 0 0.5 1 1.5 x 10-5 -1 0 1 Time Th e q uan tiz e r out pu t 0 0.5 1 1.5 x 10-5 -1 0 1
Fig. 4. The output swings of the proposed and conventional architecture.
Fig. 4. According to Fig. 4, the integrator output swings of the proposed architecture are much smaller than that of the conventional architecture. The output swings of conventional SDM are in the range from 1 V to−1 V,
but in our architecture, the first integrator output swing is reduced from 0.5 V to−0.5 V and especially the second integrator output swing is reduced from 0.2 V
Fig. 5. The output spectrum of the proposed and Leslie-Singh ar-chitecture.
3.3. Proposed Topology with Extended Dynamic Range
Accordingly, the power of the quantization noise, which is shaped by the second-order high-pass func-tion, can be expressed as [11]:
PQ2∼= 2 12 π4 5 1 OSR5 , (14)
where is a quantization step and the relationship of the intervals of the high-bit quantizers between the proposed and the Leslie-Singh architecture can be
Fig. 6. The linear model of the proposed SDM with gain error and pole error.
given by
P ∼=
1
4L, (15)
whereP andL are the high-bit quantizer intervals
of the proposed and the Leslie-Singh architecture, re-spectively. By equations (14) and (15), the dynamic range of the proposed architecture can be improved by 12 dB compared with that of the Leslie-Singh architec-ture. Figure 5 shows the output spectra of the proposed and Leslie-Singh architectures. The low- and high-bit quantizers of the architecture are equal to 2-bit and 4-bit, respectively and the sampling rate and bandwidth are equal to 40 MHz and 1 MHz, respectively.
In practice, the transfer functions of H1(z) and H2(z)
can be realized accurately by a digital circuit, but the exact form of the noise transfer function NTF(z) will depend on the analog components of the low-bit modu-lator loop. If NTF(z) and H2(z) cannot be identical, then
the leakage noise will be appeared in the output of the modulator and may degrade the performance. Indeed the leakage noise can be reduced and the cancellation technique is discussed in the following subsection. 3.4. Digital Calibration Techniques
In practice, the gain error and pole error of the inte-grator may degrade the performance of the modulator. Consider the non-ideal effects of the proposed second-order modulator, as shown in Fig. 6.α1,β1andα2,β2
are the actual gain coefficients and pole coefficients of the first integrator and second integrator in our pro-posed modulator, respectively. Ideally, the gain and
Fig. 7. The output spectrum of the proposed modulator with blind on-line calibration.
pole coefficients of the integrators must equal unity and the low-bit quantization error of the modulator can thus be cancelled by the digital cancellation fil-ter, H2(z). Unfortunately, the coefficients varying due
to the pole and gain errors may cause leakage noise in the modulator output [1]. The digital cancellation filter,
H2(z), must equal the NTF of the modulator to solve
this problem, and can be expressed as follows,
H2(z)= 1− β1z−1 α1 1− β2z−1 α2 . (16)
Therefore, the key to the digital correction is a tech-nique to adaptively estimate the digital filter coeffi-cients [12–15]. The blind on-line digital calibration [12] can be used to correct the leakage noise in the modulator output. By the least-square formulation of the calibration, we can modify the coefficients of the digital cancellation filter, H2(z), and cancel the
leak-age noise. The detail of the blind on-line calibration is given in Appendix A. Figure 7 shows the output spectra of the proposed SDM with a 2% gain error and a 50 dB finite op-amp gain by using blind on-line calibration.
The effective SNDR of the proposed SDM, obtained by the blind on-line calibration technique as a function of the number of the calibration samples and the relative signal bandwidth fn/ fs = 1/OSR, can be analyzed as
follows. A lower bound on the number of samples, L, required for calibration is approximated by [12]
1− 1
OSR
L > n − 1, (17)
where n is the number of the estimated parameters of
H2(z). The rank of the effective number of the
lin-early independent calibration samples must exceed the number of the estimated parameters of H2(z).
Simu-lation results indicate that an excellent performance is obtained with only 256 calibration samples with five-time iterations of the linear regression for the proposed SDM (modulator order= 2, OSR = 40) using blind on-line calibration.
4. Circuit Implementation
Based on the proposed architecture, a SDM for Blue-tooth application (BW= 500 KHz) with sampling rate
of 40 MHz under 0.25µm 1P5 M mixed-mode CMOS
process was designed and implemented. The digital fil-ter coefficients are calculated by using Matlab tool, and the cancellation logics are not implemented to the cir-cuits. The details of the circuit design are discussed in the following subsections.
4.1. Opamp Circuit Design
The opamp is a key component of the sigma-delta mod-ulators and may affect the performance of the modula-tors seriously. A fully differential folded-cascode OTA with gain-boosted technique [16] is applied to the pro-posed modulator and is shown in Fig. 8. Due to the fully differential architecture of the opamp, the com-mon mode feedback circuit (CMFB) must be added. In order to optimize the opamp circuit specifications such
Vbp1 Vbn2 Vbp2 Vbp1 Vbn2 Vbp2 Vip Vin Vcmfb Von Vop
20 30 40 50 60 70 80 90 35 40 45 50 55 60 65 70 75 80 85 opdc gain (dB) S NDR (dB )
Fig. 9. The SNDR of the proposed modulator versus finite opamp gain.
as dc gain and unity-gain bandwidth . . . etc, the system level simulation is used to obtain the optimum opamp specifications. Figure 9 shows the simulated SNDR as a function of the finite op-amp gain for the proposed SDM with an input magnitude of−6 dB. The key per-formance parameters for the opamp are summarized in Table 1.
4.2. Comparator and Quantizer Circuits Design Figure 10 shows the comparator circuit used in the pro-posed SDM. This comparator has one stage of the
pre-Vss Vdd Q Q Ib ck1 ck2 vin1 vin2
Fig. 10. The comparator circuit of the proposed modulator.
Table 1. Performance summary of the gain-boosted folded-cascode OTA.
Opamp specification Values
DC gain 72 dB
GBW 300 MHz (@5 pF load)
Phase margin 72 degree
Differential output swing 2.4 V (Vdd= 2.5 V)
Maximum current 1 mA
Power dissipation 15 mW
Technology 0.25µm CMOS
amplification followed by a track-and-latch stage, and is suited to the high-speed sigma-delta modulator de-sign [17].
The three-level quantizer can be implemented by us-ing two comparators and two logic gates (XOR and AND). Figure 11 shows the schematic of a 1.5-bit (three-level) quantizer circuit. The performance of the modulator is relatively insensitive to the offset and hys-teresis in the three-level quantizer because the effects of the impairments are attenuated in the baseband by the second-order noise shaping.
The 4-bit quantizer is implemented by a fully dif-ferential flash ADC with 16 parallel comparators and a resister divider to generate the reference voltage of the comparators. Figure 12 shows the schematic of the 4-bit quantizer circuit. The modulator performance is also very tolerant to the nonlinearity and hysteresis
Vcm Vcm ck1d ck1d ck2d ck2d ck2 ck2 C C Vcm Vcm ck1d ck1d ck2d ck2d ck2 ck2 C C f1 f2 f 3 vinp vr+ vr+ vinn vinn vinp
vr-Fig. 11. The circuit schematic of the 1.5-bit (three-level) quantizer.
ck2d ck2 Vcm ck1d C "1" "1" R R/2 R/2 Vref+ Vref-Vinp Vinn R
Encoder
B3 B2 B1 B0 Vcm ck2d ck1d C ck2d ck1d C ck2d ck1d C ck2d ck1d C ck2d ck1d C Vcm Vcmf1 f2 f3 f1 f2 f3 Vinp Vinn ck1d ck2 ck1 ck1 Vr+ Vcm Vr-Vr+ Vr- Vcm ck1d ck1 ck2 ck2d ck2 ck2d ck2d ck2d ck2d ck1d ck1d ck1d ck1d ck2d ck1d ck1d ck2d ck2d C C C C C C Vcm Vcm Vcm Vcm Vcm Vcm Vcm Vcm Vcm Vcm Vcm Vcm ck2 ck2 ck2d ck1 ck1 4-bit ADC vin+ 4-bit ADC vin-C C C1 C2 C2 C3 C4 C4 C1=C2=C3=3pF C4=6pF C=1pF f1 f2 f3 ck1d ck1d B3 B2 B1 B0
Fig. 13. The circuit diagram implementation of the proposed SDM.
in the 4-bit quantizer because the outputs of the 4-bit quantizer are not in the feedback loop of the modulator. 4.3. Proposed Second-Order Sigma-Delta
Modulator
The circuit diagram of the proposed SDM imple-mentation (for simplicity, the 4-bit quantizer circuit is not shown here) is shown in Fig. 13. The switch sizes (W/L) of the nMOS and pMOS are chosen as
10µm/0.25 µm and 40 µm/0.25 µm respectively to
achieve a 150 switch turn-on resistance. The sam-pling capacitor value is chosen as 3pF to minimize the thermal noise. A three-level quantizer (as shown in Fig. 12) is used instead of the 2-bit quantizer (as shown in Fig. 2) to avoid the DAC mismatch and reduce the ana-log circuit complexity, but the gain of the second inte-grator must be equal to 0.5 to avoid the overloading of the integrators. This will cause 6 dB loss of the dynamic range in circuit implementation, but the feedback loop does not need a multi-bit DAC.
The first integrator of the modulator can be imple-mented by a noninverting SC integrator and has the equivalent transfer function of 1−zz−1−1. The second in-tegrator of the modulator can be implemented as an inverting SC integrator and has the equivalent transfer function of 1−0.5−z−1. Due to the inverting characteristic of the second integrator, the outputs of the first integrator must be across to the inputs of the second integrator
to achieve the positive transfer function of 1−z0.5−1. The summing stage of the modulator can be implemented as a SC summing amplifier.
5. Experimental Results and Comparisons
The SDM is implemented in a 0.25 µm, 1-poly
5-metal, CMOS process, operating from a 2.5-V supply. The chip area including bonding pads is 1.29 mm× 1.29 mm and shows in Fig. 14. In the floor
Table 2. Measured results of the experimental SDM. Parameter Values Sampling rate 40 MHz Signal bandwidth 0.5 MHz Oversampling ratio 40 Peak SNDR 78 dB Supply voltage 2.5 V Power dissipation 56 mW Technology 0.25µm, 1P5M, CMOS Chip area 1.29 mm× 1.29 mm
plan, we try to divide the active circuitry into two parts, analog circuit and digital circuit, and give in-dependent power supply voltages. In order to avoid the digital noise coupling, the guard ring and shield tech-niques are applied to the analog circuit components. By these arrangements, the performance of the modu-lator can have a better SNDR in the mixed-mode circuit design.
The whole modulator is integrated by the building blocks as mentioned in the above sections. The peak SNDR of the measurement results, which is calculated within a 500 KHz signal bandwidth, is 78 dB. A 32768-point FFT plot of the SDM output spectrum is shown in Fig. 15, where a 100 KHz and a−6 dB input signal is applied. The measurement results are close to that
Fig. 15. FFT plot of the SDM outputs.
-90 -80 -70 -60 -50 -40 -30 -20 -10 0 -20 -10 0 10 20 30 40 50 60 70 80 Input level (dB) SNDR ( d B ) proposed SDM
conventional SDM with DAC=1% error Leslie-Singh SDM with opamp DC-gain=50dB
Fig. 16. The SNDR versus input level of the proposed and conven-tional architectures.
obtained in the circuit simulation. The whole sigma-delta modulator power dissipation is about 56 mW. The measured results of the experimental SDM circuit are shown in Table 2.
The proposed second-order SDM has several ad-vantages compared with conventional SDMs. Firstly, the proposed SDM use a single-bit DAC in the feed-back loop, but the performance is still as good as that of the multi-bit SDM. This advantage can avoid the effects of the DAC mismatch, and reduce the circuit complexity. Secondly, the proposed SDM can improve
Table 3. The comparisons of the various architectures used in Bluetooth application. Architectures
Conventional Leslie-Singh [3] Proposed Multi-bit Dual-quantizer Dual-quantizer Specifications 2nd-order SDM 2nd-order SDM 2nd-order SDM
Quantization bits 4 1.5 and 4 1.5 and 4
Bandwidth (MHz) 0.5 0.5 0.5
OSR 40 40 40
Sampling ratio (MHz) 40 40 40
SNDR with ideal case (dB) 84 74 84
SNDR with Adc= 50 dB (dB) 76 62 78
SNDR with 1% DAC mismatch (dB) 62 74 (none DAC error) 78 (none DAC error)
the nonlinear distortion of the modulator and reduce the output swing of the integrators in the modulator. Furthermore, the gain error and pole error of the pro-posed modulator can be improved by using the blind on-line digital calibration technique. Finally, the pro-posed modulator can extend the dynamic range of the modulator and is suited to wide-bandwidth applica-tions such as xDSL and Bluetooth . . . etc. The simu-lated SNDR as a function of the input level is shown in Fig. 16. According to Fig. 16, the SNDR of the pro-posed SDM has better tolerance than Leslie-Singh [3] with non-linear amplifier dc gain. Moreover, our pro-posed SDM is suitable to multi-bit quantizer imple-mentation. Comparing with the conventional multi-bit second-order SDM, the non-linearity DAC effects have been avoided in our approach. The comparisons of the various second-order multi-bit SDM architectures used in Bluetooth application are shown in Table 3. 6. Conclusions
A low-distortion and swing-suppression second-order SDM is proposed to extend the dynamic range and bandwidth. The architecture is effective for low OSR and imperfect components of the modulator, and it can simplify the circuit complexity. According to the mixed-mode 0.25µm CMOS technology, the proposed architecture can achieve a DR of 90 dB and a peak SNDR of 78 dB at a Nyquist rate of 1 MHz for the Bluetooth application.
In order to improve the nonlinearity effects of the proposed dual-quantizer second-order SDM such as pole error and gain error, the blind on-line digital cal-ibration is applied to the modulator. According to the simulation results, the modulator performance can be
improved closely to the ideal case of the modulator. Therefore, the proposed dual-quantizer second-order SDM is very suited to wide-bandwidth application by the standard CMOS process.
Appendix A: Blind On-Line Digital Calibration Blind on-line digital calibration was proposed by Cauwenberghs [12] and can be used to correct the gain and pole errors of the multi-stage or dual-quantizer SDMs. The task of estimating the parametersα1,α2, β1, and β2 in equation (16) is ill-defined (i.e. blind).
The approach requires a band-limited input signal, with a sampling frequency, fs, strictly above the Nyquist
rate, fN= 2 fb, where fb is the base-band frequency.
Figure A1 illustrates the stop band [ fb, fs− fb] that is
reserved for calibration. No additional cost is incurred since an anti-aliasing band-limited filter is present for perfect reconstruction of the input.
A high-pass filter, Hc, spanning the band [ fb, fs− fb]
eliminates the input signal, X. The only complication arises from the frequency dependency of the quantiza-tion noise in equaquantiza-tion (16) through the noise shaping. The key to blind on-line calibration is to match the
f fS calibration band fS-fb fb X
noise-shaping of the quantization noise as faithfully as possible in the least-square formulation of the pa-rameter estimation, and is explained in the following paragraph.
First, the highpass filter, Hc, is applied to eliminate
the band-limited input, X. From equation (16), the co-efficients of the digital cancellation filter, H2(z), is
es-timated by minimizing the variance of the quantiza-tion noise, Q2(z), assuming a white and uniform power
spectrum over the calibration band:
|HcQ2(z)|2= α1 z− β1 α2 z− β2 HcY 2 ≈ |NcY1+ H(z)NcY2|2, (A1)
where z ≡ ejwith = 2πf / fs, and the digital
em-phasis filter, Nc(z)= 1 (z− 1)2Hc(z)≈ α1 z− β1 α2 z− β2 Hc(z), (A2)
serves to equalize the newly proposed noise-shaping of the spectrum of Q2(z) in the estimation and removes
the signal band of X. The error generated in the ap-proximation of the unknown noise-shaping in equation (A2) does not affect the accuracy of the results to the first order.
Acknowledgments
The authors would like to thank Prof. Gert Cauwen-berghs at Johns Hopkins University, Baltimore for his guidance and help in using blind on-line calibration. This work is partially supported by Nation Science Council of ROC under grant NSC91-2215-E-032-002. References
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Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in elec-tronics engineering from Tamkang University, Taipei,
Taiwan in 1983. In 1988 he received the M.S. de-gree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992 he received the Ph.D. de-gree in electrical engineering from Texas A&M Univer-sity, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently he is an asso-ciate professor and the department chair of the Depart-ment of Electrical Engineering at Tamkang University. Dr. Chiangs research interest includes computer arith-metic, computer architecture, digital signal processing for VLSI architecture, architecture for image data com-pressing, analog to digital data conversion, and low power circuit design.
Pao-Chu Chou was born in Yulin, Taiwan, Republic of China, in 1974. He received the B.S., M.S., and Ph.D.
degrees from the Department of Electrical Engineering, Tamkang University, Taiwan, in 1996, 1998, and 2004 respectively. His research interests include oversam-pling data converter and analog filter. He joined Sili-con Touch Technology Inc., Taiwan, in 2005, where he works on development of power management IC.
Teng-Hung Chang was born in Kaohsiung, Tai-wan, Republic of China, in 1976. He received the M.S. degree from the Department of Electrical Engineer-ing, Tamkang University, Taiwan, in 2000. He cur-rently is pursuing the Ph.D. degree at Department of Electrical and Control Engineering, National Chiao Tung University, Taiwan. His research interests in-clude high-performance analog-to-digital converters and low-voltage circuit designs.
![Figure A1 illustrates the stop band [ f b , f s − f b ] that is](https://thumb-ap.123doks.com/thumbv2/9libinfo/7666374.140894/12.892.466.786.910.1037/figure-a-illustrates-stop-band-f-b-f.webp)
