Design and Implementation of Sensorless Capacitor
Voltage Balancing Control for Three-Level
Boosting PFC
Hung-Chi Chen, Member, IEEE, and Jhen-Yu Liao
Abstract—Compared with the conventional boosting PFC
con-verter, the three-level boosting PFC converter has two cascaded switches and two cascaded capacitors across the dc-side voltage. Two capacitor voltages may be different due to their mismatched equivalent series resistance, their mismatched capacitance, and the mismatched conducting time of the corresponding switches. It fol-lows that the controller needs to sense the capacitor voltages to balance both capacitor voltages. In this paper, the sensorless ca-pacitor voltage balancing control (SCVBC) without sensing the capacitor voltages is proposed, and the total number of the feed-back signals is saved. The proposed SCVBC is digitally imple-mented in an FPGA-based system. The provided simulated and experimental results also demonstrate the proposed SCVBC.
Index Terms—Sensorless control, voltage-balancing control.
I. INTRODUCTION
T
O REDUCE the power transmission loss and increase the system stability, more and more power-electronics prod-ucts are forced to include the power factor correction (PFC) function [1]. Generally speaking, the PFC function includes shaping the ac-side current waveform and regulating the dc-side voltage. Due to the characteristics of the continuous current, the boost-derived PFC converters have been widely used to achieve the desired PFC function [2].For the conventional boost dc/dc converter, the single switch needs to withstand the dc output voltage when the single switch blocks. As shown in Fig. 1, two cascaded switches and two cascaded capacitors are connected together in the three-level boosting dc/dc converter. When one of the switches conducts and the other blocks, the blocking switch needs to withstand only half dc output voltage if both capacitor voltages are balanced. If not balanced, one of the capacitor voltages may be larger than the breakdown voltage of the switch, which would contribute to make damage to the switch.
It is noted that the inductor voltage in the three-level boost dc/dc converter has three levels, which makes the three-level boosting dc/dc converter to have smaller inductor current ripple
Manuscript received April 11, 2013; revised June 11, 2013 and July 30, 2013; accepted August 14, 2013. Date of current version February 18, 2014. Recommended for publication by Associate Editor C. K. Tse.
The authors are with the Department of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: hcchen@ mail.nctu.edu.tw; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2279718
Fig. 1. Three-level boosting PFC converter with multiloop feedforward con-trol and the conventional capacitor voltage balancing concon-trol loop.
than the boost converter under the same switching frequency. Therefore, the three-level boost converters are often used in the high-voltage-ratio applications [3], such as the fuel cell appli-cations [4], [5] and the grid-connected appliappli-cations [6]–[8].
In addition, the high-withstanding-voltage semiconductor switches often have higher cost and the larger drain-source resistances than the low-withstanding-voltage ones. Thus, the three-level boost converter has the additional advantages of the low switching loss and the high efficiency [9].
The three-level boosting PFC converter was first proposed in [9] by connecting the diode rectifier to the three-level boosting dc/dc converter as shown in Fig. 1 [9]–[14].
In [13], the multiloop interleaved control combining the mul-tiloop control and the interleaved PWM scheme was first pro-posed to control the three-level boosting PFC converter. As shown in Fig. 1, the multiloop control includes the feedforward loop, the inner current loop, and the outer voltage loop.
The three single-phase three-level boosting PFC converter in Delta connection are used to achieve the three-phase PFC function with the ability of redundancy [14].
However, the balance between two capacitor voltages should be noted. In practice, the mismatched capacitances and the mismatched equivalent series resistance (ESR) would result in 0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
the voltage imbalance. Therefore, the control of the three-level boosting converter needs to balance both capacitor voltages.
In the literature [7], [8], [11], [12], [15], the voltage balancing control loop for three-level boosting converters can be found. In fact, the other voltage balancing control can be found in the controls of the half-bridge PFC converter [16], [17] and the multilevel inverter [18], [19]. All the methods need to sense capacitor voltages to detect the voltage imbalance and yield the desired voltage balancing function. The multiloop interleaved control with conventional capacitor voltage balancing control (CVBC) is also shown in Fig. 1. One control signal is generated by the multiloop control, and the other control signal is yielded by CVBC with sensing the capacitor voltages. For the three-level boosting dc/dc converter, a voltage balancing control method with sensing only inductor current was first proposed in [20].
In this paper, the concept in [20] is extended to the three-level boosting PFC application and the proposed controller is named the sensorless capacitor voltage balancing control (SCVBC). The voltage imbalance between two capacitor voltages is skill-fully detected by sensing the inductor current. The detailed anal-ysis and the design rule of the proportion-type voltage balance controller are also provided. It follows that sensing individual capacitor voltage is not required, and at least one voltage sen-sor is saved. The provided simulation and experimental results show the effectiveness of the proposed SCVBC.
II. THREE-LEVELBOOSTINGPFC CONVERTER From Fig. 1, the input ac voltage vs = ˆVssin(2πf t) is
as-sumed to be a sinusoidal function with a peak amplitude ˆVs.
Through the diode rectifier, the input voltage of the three-level boosting converter can be expressed with the rectified voltage
|vs|. By assuming that the switching frequency fsis much larger
than the line frequency f , the control signals vcont1 and vcont2 can be regarded as two constants within the switching period Ts= 1/fs. In addition, the ideal inductor and the ideal
ca-pacitors are assumed. That is, the inductor resistance and the capacitor resistances are assumed to be zero.
In Fig. 1, two triangular signals vtri1and vtri2are interleaved by 180◦. The conventional multiloop control generates the con-trol signal vcont1, and then, the gate signal GT1is generated from the comparison of the control signal vcont1 and the triangular signal vtri1.
After sensing both capacitor voltages, the voltage imbalance is detected and the conventional CVBC generates the compen-sation signal Δvcont. Then, the other control signal vcont2 is obtained by adding the compensation signal Δvcontto the con-trol signal vcont1. The gate signal GT2 is obtained from the comparison of the control signal vcont2 and the triangular sig-nals vtri2.
Due to the input inductor L and two diodes D1 and D2 in the three-level boosting PFC converter, both switches can be conducting at the same time without the concern of the short-circuit damage. As plotted in Fig. 2, there are four switching states in the three-level boosting PFC converter.
As shown in Fig. 2(a), both switches turn ON in the switch-ing state 1. Thus, the inductor voltage vL in the three-level
Fig. 2. Possible switching states in the three-level boosting PFC converter: (a) state 1, (b) state 2, (c) state 3, and (d) state 4.
TABLE I
CAPACITORCURRENTS INEACHSTATE
boosting PFC converter equals the rectified input voltage
vL =|vs| and both capacitors supply energy to the load
iC 1= iC 2= (−id) < 0.
In the switching state 2 in Fig. 2(b), the top switch turns ON and the bottom switch turns OFF. The resulting induc-tor voltage vL equals the rectified input voltage |vs| minus
the bottom capacitor voltage vL =|vs| − vC 2. Additionally,
the capacitor C1 supplies energy to the load iC 1= (−id) < 0,
but the capacitor C2 stores the energy from the input voltage iC 2= (iL − id) > 0.
Similarly, the resulting inductor voltage in Fig. 2(c) equals the rectified input voltage minus the top capacitor voltage vL =
|vs| − vC 1. In the switching state 3, the top capacitor C1 is
charged iC 1= (iL− id) > 0, but the bottom capacitor C2 is discharged iC 2= (−id) < 0.
When both switches turn OFF in Fig. 2(d), the resulting in-ductor voltage equals the rectified input voltage minus the output voltage vL =|vs| − vd =|vs| − vC 1− vC 2. The rectified input
voltage|vs| supplies the load current and charges both capacitors
simultaneously iC 1= iC 2= (iL− id) > 0.
All the capacitor currents in various switching states are tab-ulated in Table I.
The behavior of the three-level boosting converter can be divided into two cases as shown in Fig. 3. In the case of 2 > vcont1+ vcont2 > 1, two switches may conduct at the same time within the switching period Tsand there are switching state 1,
state 2, and state 3.
In the other case of 1 > vcont1+ vcont2 > 0, only switching state 2, state 3, and state 4 exist.
Fig. 3. Behavior of the three-level boosting converter. (a) 2 > vc o nt 1+
vc o nt 2> 1and (b) 1 > vc o nt 1+ vc o nt 2 > 0.
Fig. 4. Equivalent voltage balancing loop with the conventional CVBC.
In the case of 2 > vcont1+ vcont2 > 1 in Fig. 3(a), the con-ducting times of the switching state 2 and the switching state 3 are (1− vcont2)Ts and (1− vcont1)Ts, respectively. The
re-maining time for the switching state 1 is (vcont1 + vcont2−
1)Ts. Therefore, the average capacitor currents iC 1T s and iC 2T swithin switching period Tscan be obtained by
iC 1T s =−id + (1− vcont1)iL (1) iC 2T s =−id + (1− vcont2)iL. (2)
Similarly, for the other case of 1 > vcont1 + vcont2 > 0 in Fig. 3(b), the conducting times of the switching state 2 and state 3 are vcont1Ts and vcont2Ts, respectively. The remaining
time for the switching state 4 is (1− vcont1− vcont2)Ts. After
calculations, it can be found that the average capacitor currents iC 1T sandiC 2T shave the same equations as (1) and (2).
Thus, in both cases, the difference between two average ca-pacitor currents is obtained from (1) and (2)
iC 1T s− iC 2T s= (vcont2− vcont1)iL = ΔvcontiL. (3)
It follows that the voltage imbalance ΔvC = vC 1− vC 2can
be expressed as ΔvC(s) = 1 s Δvcont C iL (4)
where Δvcont= vcont2− vcont1.
The equivalent voltage balancing loop with the conventional CVBC is plotted in Fig. 4 where the proportional controller (i.e., P controller) with the parameter KP is used. Thus, the
closed-loop transfer function of the voltage imbalance ΔvC(s)
becomes ΔvC(s) Δv∗C(s)= Kp C iL s +Kp C iL . (5)
Because that (5) is a first-order response with zero steady-state error, the voltage imbalance would be well regulated to the zero voltage imbalance Δv∗C = 0. Therefore, the design of the
Fig. 5. Multiloop interleaved control with the proposed SCVBC.
Fig. 6. Proposed sampling and hold strategy.
conventional CVBC with simple P controller is able to balance the capacitor voltages.
III. PROPOSEDSENSORLESSCAPACITORVOLTAGE BALANCINGCONTROL
The multiloop interleaved control and the proposed SCVBC with the proposed sampling/hold strategy are shown in Fig. 5 where only the input voltage vs, the output voltage vd, and the
inductor current iL are sensed. It is noted that the proposed
sampling/hold strategy samples the inductor current iL thrice
per switching period Ts as shown in Fig. 6, and obtains the
average value ILand the other two values Iv C 1and Iv C 2.
The average value current ILis input to the multiloop control
to yield the desired PFC function and obtain the control signal vcont1. The difference ΔIv Cbetween two values Iv C 1and Iv C 2
is calculated and the compensating signal Δvcontis obtained by the used P controller
Δvcont= Kp(Iv C 2− Iv C 1). (6)
Then, the other control signal vcont2 is generated by adding the compensating signal Δvcontto the control signal vcont1
vcont2 = vcont1+ Δvcont= vcont1+ Kp(Iv C 2− Iv C 1). (7)
Fig. 6 shows the proposed sampling/hold strategy with sens-ing the inductor current iL. The average value IL is obtained
by sampling the inductor current iL at the peak of the
triangu-lar signal vtri1 = 1. When the triangular signal vtri1rises to 0.5 from the valley, the inductor current is sampled and the obtained
Fig. 7. Illustrated waveforms (2 > vc o nt 1+ vc o nt 2> 1). (a) vC 1> vC 2 >
|vs| and (b) vC 1>|vs| > vC 2.
value is defined as Iv C 1. The value Iv C 2 is sampled when the
triangular signal vtri1 falls to 0.5 from the peak.
After finishing all the sampling actions, the multiloop control is performed at the controller time, and updates the two control signals at the valley of the triangular signal vtr i1.
In the following paragraphs, the analysis is divided into two cases - 2 > vcont1 + vcont2 > 1 and 1 > vcont1+ vcont2 > 0
2 > vcont1+ vcont2 > 1.
The illustrated waveforms for the voltage imbalance ΔvC >
0 (i.e., vC 1 > vC 2) are plotted in Fig. 7. Since the input ac
volt-age vsis time-varying, the voltage imbalance ΔvC > 0 may be
divided into two conditions—either vC 1> vC 2>|vs| or vC 1> |vs| > vC 2. The waveforms in the condition vC 1 > vC 2>|vs|
are plotted in Fig. 7(a), and the inductor current iL is falling
at the switching state 2. But the inductor current iL is rising at
the switching state 2 in the other condition vC 1 >|vs| > vC 2
as plotted in Fig. 7(b).
The illustrated waveforms for the voltage imbalance vC 2> vC 1>|vs| and vC 2>|vs| > vC 1are plotted in Figs. 8(a) and
(b), respectively. It is noted that in Fig. 8(a), the inductor current iL is falling at the switching state 3, but the current iL is rising
at the switching state 3 in Fig. 8(b).
Due to the waveform symmetry in Fig. 7 and Fig. 8, the time t1between the instants of sampling the value Iv C 1and the
turning-off instants of the gate signal GT1 is equal to the time between the turning-on instants of the gate signal GT1 and the instants of sampling the value Iv C 2. Therefore, the time t1 can be expressed in terms of the control signal vcont1
t1 = vcont1 2 − 1 4 Ts. (8)
Fig. 8. Illustrated waveforms (2 > vc o nt 1+ vc o nt 2> 1). (a) vC 2> vC 1>
|vs| and (b) vC 2>|vs| > vC 1.
From Fig. 7 and Fig. 8, the conducting time for the switching state 2 and the switching state 3 are (1− vcont2)Ts and (1− vcont1)Ts, respectively. The remaining time for switching state
1 is (vcont1+ vcont2− 1)Ts. Then, the average inductor voltage vLT s in the three-level boosting converter can be expressed
as equation (9) at the bottom of the page.
Because of zero average inductor voltage in the steady-state condition, the rectified input voltage|vs| must be equal to
|vs| = (1 − vcont1)vC 1+ (1− vcont2)vC 2. (10)
From Fig. 7 and Fig. 8, the difference ΔIv C between two
sampled values Iv C 1and Iv C 2can be expressed in terms of the
time t1 ΔIv C = Iv C 2− Iv C 1= 2|vs| L t1+ |vs| − vC 1 L (1− vcont1)Ts. (11) Substituting (8) and (10) into (11) obtains
ΔIv C = Ts
2L[(vC 2− vC 1)(1− vcont1)− ΔvcontvC 2] . (12)
By substituting (6) into (12), the expression ΔIv C in (12) can
be rewritten as ΔIv C = Ts(1− vcont1) 2L + TsKPvC 2 (vC 2− vC 1) = k1(vC 2− vC 1). (13) Because the coefficient k1 is always positive, the difference
ΔIv C is proportional to the voltage imbalance (vC 2− vC 1).
It follows that the difference ΔIv C can be used to detect the
voltage imbalance (vC 2− vC 1) without directly sensing the
ca-pacitor voltages.
1 > vcont1+ vcont2 > 0
vLT s=|vs|(vcont1
+ vcont2− 1)Ts+ (|vs| − vC 1)(1− vcont1)Ts+ (|vs| − vC 2)(1− vcont2)Ts Ts
Fig. 9. Illustrated waveforms (1 > vc o nt 1+ vc o nt 2> 0). (a)|vs| > vC 1>
vC 2and (b) vC 1 >|vs| > vC 2.
Fig. 10. Illustrated waveforms (1 > vc o nt 1+ vc o nt 2> 0). (a) |vs| >
vC 2> vC 1and (b) vC 2>|vs| > vC 1.
In this case, the illustrated waveforms for the voltage im-balance vC 1> vC 2>|vs| and vC 1> vC 2>|vs| are plotted in
Fig. 9(a) and (b), respectively. In Fig. 9(a), the inductor current iL is rising at the switching state 3, but the inductor current iL
is falling at the switching state 3 in Fig. 9(b).
The illustrated waveforms for the voltage imbalance|vs| > vC 2 > vC 1and vC 2 >|vs| > vC 1are plotted in Fig. 10(a) and
Fig. 10(b), respectively. It is noted that in Fig. 10(a), the inductor current iL is rising at the switching state 2 due to|vs| > vC 2,
but the current iLis falling at the switching state 2 in Fig. 10(b)
due to vC 2>|vs|.
Due to the symmetry, the time t2 between the instants of sampling the value Iv C 1and the turning-off instants of the gate
signal GT1can be expressed in terms of the control signal vcont1 t2 = 1 4 − vcont1 2 Ts. (14)
From Fig. 9 and Fig. 10, the conducting times for switch-ing state 2 and switchswitch-ing state 3 are (vcont1Ts) and (vcont2Ts),
respectively. The remaining times in a switching period Ts for
switching state 4 is (1− vcont1− vcont2)Ts. The average
induc-tor voltagevLT s in the three-level converters is the same as
(9), equation (15) at the bottom of the page.
From Fig. 9 and Fig. 10, the difference ΔIv C between two
sampled values Iv C 1 and Iv C 2 can expressed in terms of the
time ΔIv C= Iv C 2− Iv C 1=−|vs| − vC 2 L vcont1Ts− 2 |vs| − vd L t2. (16) Substituting (10) and (14) into (16) obtains
ΔIv C = Ts
2L[(vC 2− vC 1)vcont1+ ΔvcontvC 2] . (17)
By substituting (6) into (17), (17) can be rewritten as
ΔIv C =
Tsvcont1
2L− TsKPvC 2
(vC 2− vC 1) = k2(vC 2− vC 1).
(18) The coefficient k2may be either positive one or negative one. In order to force the coefficient k2positive, the denominator of (18) should be positive
2L− TsKPvC 2> 0. (19)
It implies that the controller parameter KP should be located
at the range
0 < KP <
2L
TsvC 2,m ax
(20) where vC 2,m axis the maximum bottom capacitor voltage. Then,
the difference ΔIv C would be proportional to the voltage
im-balance (vC 2− vC 1).
From (13) and (18) in both cases, the difference ΔIv Cin both
cases are proportional to the voltage imbalance (vC 2− vC 1) via
properly selecting the controller parameter KP, which implies
that the difference ΔIv C obtained from the proposed SCVBC
can be used to detect the voltage imbalance (vC 2− vC 1) without
directly sensing the capacitor voltages. IV. SIMULATION
In this section, some simulation results of the three-level boosting converter are provided and the used parameters are tabulated in Table II. For the multiloop control in Fig. 1, the pa-rameters of the voltage controller are KP v = 0.1 and KI v = 5,
and the parameters of the current controller are KP i = 0.02 and KI i = 10. From (20), the range of the parameter KP must be
vLT s=
(|vs| − vd)(1− vcont1− vcont2)Ts+ (|vs| − vC 1)vcont2Ts+ (|vs| − vC 2)vcont1Ts Ts
TABLE II
SIMULATEDPARAMETERS OFTHREE-LEVELBOOSTCONVERTER
Fig. 11. Simulation results for the three-level boost converter at 300 W.
between 0 and 0.1. Then, KP = 0.05 is selected with
consider-ation of the inductance variconsider-ation.
Two mismatched capacitances with C1 = 2240 μF and C2 = 1410 μF are used in the simulation. The capacitance-mismatch condition does not appear in the practical case, but the mis-matched conditions are helpful for the demonstration of the proposed SCVBC.
A. Steady-State Response
The simulation results for the three-level boosting PFC con-verter at 300W and 600 W are plotted in Fig. 11 and Fig. 12, re-spectively. The yielded input currents isare sinusoidal in phase
with the input voltage vs. Both capacitor voltages have the
av-erage values equal to the half avav-erage value of the dc voltage vd
even though the capacitances are mismatched.
The obtained value ΔIv C approximates to zero in the steady
state. The results show that the proposed SCVBC is able to achieve PFC function in the three-level boost converter without directly sensing capacitor voltages.
Fig. 12. Simulation results for the three-level boost converter at 600 W.
Fig. 13. Simulation waveforms during load change from 300 to 600 W.
B. Transient Response
In order to observe the transient response, the simulation results during load regulation are plotted in Fig. 13. The output power changes from 300 to 600 W due to the change of the load resistance from 300 to 150 Ω. During the operation, the
Fig. 14. Simulation results when a resistor 400Ω is connected to the capacitor C1and then, removed from the capacitor C1.
sinusoidal input current is is always in phase with the input
voltage vs and the output voltage vd is well regulated to the
command 300 V.
In addition, the bottom capacitor voltage vC 2possesses larger
voltage dip than the top capacitor voltage vC 1, because that the
capacitance C2 is smaller than the other capacitance C1. The significant dip in the difference ΔIv C can also be found during
the transient operation.
Both average capacitor voltages are finally equal to half voltage command 150 V, which also shows that the proposed SCVBC is able to detect the voltage imbalance and balance the capacitor voltages.
The other simulation results of the transient operation are pro-vided in Fig. 14(a) where a 400 Ω resistor is suddenly connected the capacitor C1 and then, removed from the capacitor C1. The zoomed waveforms are plotted in Fig. 14(b).
The capacitor voltage vC 1drops to 140 V in 0.1 s due to the
connected resistor, and at the same time, the capacitor voltage vC 2 raises to 160 V due to the voltage control loop in the
multiloop control.
It is noted that during the transient operation, the difference
ΔIv Cbecomes positive when the capacitor voltage vC 2is larger
than the other capacitor voltage vC 1. After the resistor is
re-moved, both capacitor voltages are finally balanced.
Obviously, the provided simulation results show that the pro-posed SCVBC works well without directly sensing the capacitor voltages.
Fig. 15. Implemented three-level boosting PFC converter with the FPGA board.
Fig. 16. Block diagram of the implemented three-level boosting PFC converter.
V. EXPERIMENTALRESULTS
The proposed SCVBC had been implemented in an FPGA-based system as shown in Fig. 15. The nominal parameters are the same as those in Table II. Fig. 16 is the block diagram of the implemented three-level boosting PFC converter. Due to no A/D and no D/A function in the commercial FPGA XC3S250 chip, three external A/D converters are used to sense the output voltage, the input voltage, and the inductor current. Some D/A converters are also used to show the control variables in the scope.
Fig. 17 and Fig. 18 show the steady-state experimental waveforms at the power level 300 (RL = 300 Ω) and 600 W
(RL = 150 Ω), respectively. Both output voltage vd are well
regulated to 300 V, and the input currents is are sinusoidal in
phase with the input voltage vs. Although two capacitor voltages
have different voltage ripples due to their different capacitance, they have the same average voltage 150 V.
The input current harmonics of the waveforms in Fig. 17 and Fig. 18 are listed in Table III where the limitations for the Class D in IEC-61000-3-2 standard are also provided for comparison.
Fig. 17. Experimental results at 300 W.
Fig. 18. Experimental results at 600 W.
In the experiment, the yielded input current harmonics are below the IEC-61000-3-2 standard.
In order to observe the transient responses, the experimental waveforms during the load change from 300 to 600 W are plotted in Fig. 19. The input currents iskeeps sinusoidal in phase with
the input voltage vsduring the load regulation. All three voltages vd, vC 1, and vC 2are well regulated during the transient period
and the capacitor vC 2has the larger voltage dip than the other
capacitor voltage vC 1.
TABLE III
INPUTCURRENTHARMONICS ATVARIOUSPOWERLEVELS
Fig. 19. Experimental waveforms during the load change from 300 to 600 W.
It can be found that the experimental results in Fig. 19 are sim-ilar to the simulation results in Fig. 13. Therefore, the proposed SCVBC is able to balance voltages during the load regulation.
After connecting a resistor 400 Ω to the capacitor C1, the experimental results are shown in Fig. 20(a) and the zoomed waveforms are plotted in Fig. 20(b). The resistor is removed from the capacitor after 0.1 s.
Due to the connected resistor across the capacitor C1, the capacitor voltage vC 1drops quickly, and at the same time, the
other capacitor voltage vC 2 rises in order to regulate the
dc-side voltage vd. After the resistor is removed, significant
posi-tive voltage imbalance (vC 2− vC 1) > 0 exists and the sensed
difference becomes positive ΔIv C > 0, too. It shows that the
proposed difference signal ΔIv Cis able to detect the voltage
im-balance by sensing the inductor current. Then, the two capacitor voltages are finally balanced.
There are many examples that the load current is not constant, but pulsating, such as phase-shifted dc/dc converter, electronic ballasts. To evaluate the performance of the pulsating load cur-rent, an additional semiconductor switch is connected in se-ries with the load resistor RL = 150 Ω. The additional switch
switches with the same 20 kHz as the PFC switching frequency, and its duty ratio changes linearly from 100% to 10% to vary the
Fig. 20. (a) Experimental results when capacitor voltages are forced to change and (b) the zoomed waveform of Fig. 20(a).
equivalent load resistor RL from 150 to 1500 Ω. The obtained experimental results are provided in Fig. 21.
Before PFC and SCVBC are applied, the capacitor voltages are not balanced due to the mismatched capacitances. The ca-pacitor voltages turn to rise and finally become balanced af-ter the PFC and the SCVBC are applied. Then, the equivalent load resistor RL changes linearly from 150 to 1500 Ω. The ex-perimental waveforms with equivalent resistors 150, 300, and 1500 Ω are plotted in Fig. 21(b), (c) and (d), respectively. Al-though the load current is pulsating, the PFC performances are still accepted.
The proposed SCVBC is developed based on the assumptions of ideal inductor and ideal capacitors. The provided experimen-tal results show that the proposed SCVBC works well in the practical condition of nonzero inductor resistance and capacitor resistance.
The provided results also show that the proposed SCVBC cooperated with the multiloop interleaved control possesses the ability to achieve both the PFC function and the voltage balanc-ing function without sensbalanc-ing any capacitor voltage even large difference between two capacitances exists.
Fig. 21. (a) Experimental results when the equivalent load resistor is changed, (b) the zoomed waveforms with equivalent resistor 150 Ω (duty ratio 100%), (c) the zoomed waveforms with equivalent resistor 300 Ω (duty ratio 50%). (d) Zoomed waveforms with equivalent resistor 1500 Ω (duty ratio 10%).
VI. CONCLUSION
In this paper, the SCVBC method for the three-level boosting PFC converter has been proposed. The proposed method shows that the voltage imbalance can be detected from sensing the inductor current by the proposed sampling/hold strategy. That is, it eliminates the need for extra sensors, reduces control com-plexity, and reduces the cost and size. The reduction of cost and size are the important contributions for PFC converters. The control method is implemented in an FPGA-based system, and all the provided results demonstrate the proposed method.
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Hung Chi Chen (M’06) was born in Taichung,
Taiwan, in June 1974. He received the B.S. and Ph.D. degrees from the Department of Electrical En-gineering, National Tsing-Hua University, Hsinchu, Taiwan, in June 1996 and June 2001, respectively.
From October 2001, he was a Researcher at the Energy and Resources Laboratory, Industrial Tech-nology Research Institute, Hsinchu. In August 2006, he joined the Department of Electrical and Control, National Chiao-Tung University, Hsinchu, where he is currently an Associate Professor. From September 2011 to February 2012, he was a Visiting Scholar in the University of Texas at Arlington, Arlington, TX, USA.
His research interests include power electronics, power factor correction, mo-tor and inverter-fed control, DSP/MCU/FPGA-based implementation of digital control.
Jhen Yu Liao was born in Taoyuan, Taiwan, in
August 1986. He received the B.S. degrees at the Department of Mechatronic Technology, National Taiwan Normal University, Taipei, Taiwan, in June 2008, the M.S. degrees at the Institute of Electrical Control Engineering, the National Chiao Tung Uni-versity, Hsinchu, Taiwan, in June 2010,where he is currently working toward the Ph. Degree .
His research interests include power electronics and control, power factor correction, and FPGA-based implementation of digital control.
