Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling

Abstract—Low-frequency flicker noise in analog n-MOSFETs with 15-A gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.

Index Terms—Low-frequency noise, random telegraph signal, ultrathin oxide MOSFET, valence-band tunneling.

I. INTRODUCTION

C

MOS technology, which possesses the advantages of low cost, high integration, and low power, is finding more and more important applications in the area of mixed-mode and RF ICs. As compared with bipolar transistors, CMOS devices exhibit large noise, especially in the low-frequency domain where flicker noise is dominant [1]. Drain current flicker noise has become one of the key considerations in device geomet-rical scaling since it will affect the signal-to-noise ratio in operational amplifiers and in analog/digital and digital/analog converters. In addition, low-frequency flicker noise can be up-converted to undesired phase noise in RF circuits [2] and limits the channel spacing in communication systems. In order to reduce low-frequency noise, the physical origin of flicker noise in today’s CMOS devices with gate oxide in direct tunneling regime should be further explored.

The origin of low-frequency flicker noise in MOSFETs with relatively thick gate oxides has been extensively studied. A unified noise model [3], [4] based on oxide charge tunnel trapping and detrapping has been adopted. The carrier number

Manuscript received December 2, 2004; revised May 18, 2005. This work was supported by the Taiwan Semiconductor Manufacturing Company (TSMC) and by the National Science Council, Taiwan, R.O.C., under Contract NSC92-2215-E009-024.

J.-W. Wu, H.-C. Ma, C.-C. Cheng, C.-F. Hsu, and T. Wang are with the De-partment of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

J.-W. You is with the United Microelectronics Corporation, Hsinchu 300, Taiwan, R.O.C.

C.-S. Chang is with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C.

G.-W. Huang is with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/TED.2005.854264

and mobility fluctuation resulting from trapped oxide charges is thought to be the source of flicker noise. In addition, some studies showed that the low-frequency noise may result from charge emission and capture at interface traps in weak inversion condition or in the very high frequency regime of noise power spectral density [5]. As gate oxide thickness is scaled into direct tunneling domain, oxide trap density should be much reduced. In addition, channel electrons would likely tunnel through an ultrathin gate oxide directly without being captured by oxide traps. However, the low-frequency noise in ultrathin oxide CMOS devices still exhibits a spectrum and possesses a significant level [6], [7]. The traditional oxide charge tunnel trapping and detrapping concept seems no longer suitable to explain the noise behavior in ultrathin oxide MOSFETs. Re-cently, a study for ultrathin gate oxide fully depleted/partially depleted silicon-on-insulator (SOI) MOSFETs has shown that linear kink effect induced by valence-band electron tunneling would increase the low-frequency noise spectral density [8]. In this paper, we observe another source of low-frequency noise in ultrathin gate oxide bulk n-MOSFETs arising from valence-band electron tunneling [9], [10]. Detailed discussion on the physical mechanism of this excess noise will be given.

The time domain presentation of low-frequency noise is known as random telegraph signal (RTS) and has been studied in past decades [11]–[14]. Due to a single charge trapping and detrapping in a small area device, RTS exhibits two levels. The upper level corresponds to an empty trap, i.e., no electron occupation, and the duration of time is denoted by . The lower level corresponds to an electron occupied state and is denoted by . In many cases, corresponds to the time it takes to capture an electron, while electron release (emission) from traps governs [15].

In this work, the low-frequency noise in a 15- gate oxide n-MOSFET is investigated. The electron trapping and detrap-ping times ( and ) are characterized from RTS in a small area n-MOSFET. The power spectral density of normalized drain current noise and gate referred voltage noise is also measured. In addition, the RTS time constants and noise power spectral density in 33 oxide n-MOSFETs, where valence-band tunneling is insignificant, are characterized for comparison. The drain bias in RTS and noise measurement in this paper is 0.2 V to ensure a uniform charge distribution in the channel. Finally, a new noise source due to valence-band electron tunneling will be proposed to explain the observed noise behavior.

2062 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005

Fig. 1. Measured and calculated Lorentzian-like noise power spectral density in a small area n-MOSFET (W=L = 0:16=0:12 m, t = 15 A). The noise is measured at strong inversion (V = 0:2 V, V = 1:1 V). The cut-off frequency (f ) is also shown in the figure.

Fig. 2. Cut-off frequency versus gate voltage in a small area n-MOSFET (W=L = 0:16=0:12 m, t = 15 A). A trap (E ) is observed in weak inversion (V  0:7 V) and another trap (E ) is in strong inversion (V > 1:0 V).

II. RESULTS ANDDISCUSSION

The noise characteristic in a small area ultrathin oxide n-MOSFET with a single trap time constant is first analyzed. Fig. 1 shows the measured and calculated noise power spectral

density in a m n-MOSFET. The gate

oxide thickness is 15- . The noise has Lorentzian-like spectral distribution [15], characterized by a constant power spectral density at low frequencies and a roll-off with for high frequencies, .i.e.

and (1)

The cut-off frequency corresponds to the 3-dB point of the spectrum and is related to the reciprocal characteristic time of the underlying trap . The calculated result (solid line in Fig. 1) is based on and extracted from associ-ated RTS (will be shown later) and is in good agreement with the measured power spectral density. Fig. 2 shows the gate voltage ( ) dependence of . Obviously, there exist two groups of trap frequency (or two trap energy levels) with one observed

Fig. 3. Substrate current(I ) versus gate voltage in a 15-A oxide n-MOSFET. TheI in the 15-A oxide device drastically increases for V > 1:0 V (strong inversion regime), which indicates the occurrence of valence-band electron tunneling.

Fig. 4. (a) Typical RTS patterns at various gate voltages fromV = 0:65 to 0.9 V in a small area n-MOSFET (W=L = 0:16=0:12 m, t = 15 A). RTS is undetectable atV = 0:9 V. (b) Average  and  (extracted from RTS) versus gate voltage in weak inversion regime.

in weak inversion V and the other in strong inversion V . Furthermore, significant substrate cur-rent arises in the 15- oxide device in strong inversion regime V in Fig. 3 because valence-band electron tunneling from the Si substrate to the polysilicon gate occurs and gener-ated holes flow to the substrate [16].

Fig. 4(a) shows typical RTS patterns in a small area

m 15- gate oxide n-MOSFET in weak inversion V . As can be seen, increases and decreases as increases from 0.65 to 0.9 V. Noticeably, RTS vanishes at V in our measurement period. Fig. 4(b) shows the dependence of average and (extracted from RTS) in weak inversion regime. The and in weak inversion cor-respond to the electron emission and capture times at the inter-face trap , as illustrated in Fig. 5(a). As increases,

Fig. 5. (a) Band bending in weak inversion. The RTS results from electron capture ( ) and electron emission ( ) through the interface trap E . (b) Band bending in strong inversion. The RTS results from electron capture ( ) and hole capture ( ) at E . Channel hole creation due to valence-band electron tunneling is shown.

decreases and increases because of a larger channel elec-tron population and thus a smaller elecelec-tron capture time. Our result here is consistent with the findings for thicker gate ox-ides in previous publications [11]. In contrast, Fig. 6(a) shows the RTS patterns in strong inversion from to 1.6 V. The RTS is still undetectable at V and reappears for

V. Fig. 6(b) shows the dependence of average and . Interestingly, we find that the RTS patterns in strong inversion regime V exhibit an opposite trend. The dependence of and in strong inversion is opposite to that in weak inversion. We repeated our measurement on dif-ferent samples and the opposite trend of the dependence is always obtained. Although the mobility fluctuation theory [17] can possibly explain the above opposite gate bias dependence of and from weak inversion to strong inversion, further analysis shows that number fluctuation should dominate in the entire range of our measurement gate bias. According to the cal-culated result in [17, Fig. 3], number fluctuation is dominant in the range until changes sign. In our case, the mea-sured versus is shown in Fig. 7. The de-creases with gate voltage but does not change sign in the entire range of measurement .

In order to find out the cause of the opposite charge trapping and detrapping behavior from weak inversion to strong inver-sion, the trap electron occupation factor is analyzed. The

can be evaluated as follows:

(2) Fig. 8(a) shows versus from weak inversion to strong in-version. In weak inversion regime (i.e., V), gate oxide

Fig. 6. (a) Typical RTS patterns at various gate voltages fromV = 1:0 to 1.6 V in a small area n-MOSFET (W=L = 0:16=0:12 m, t = 15 A). (b) Average and  (extracted from RTS) versus gate voltage in strong inversion regime.

Fig. 7. 1I =I versus measurement gate bias. The 1I =I is extracted from the measured RTS.

tunneling is insignificant and the channel is in thermal equilib-rium. increases with because of a larger band-bending. As increases to 1, RTS is undetectable since the trap is always occupied by an electron. However, when increases above 1.1 V, begins to decline from unity with increasing . This means, at a larger , although the energy level of the interface trap moves more deeply with respect to the electron Fermi level, the chance of the trap being occupied by an electron is smaller. This result is obviously contradicting to the equilibrium case

that should increase as the

trap energy becomes more negative with respect to the Fermi level. In other words, the Si channel in strong inversion should be in nonequilibrium condition and the cause is valence-band electron tunneling.

In addition to , Fig. 8(b) shows the (measured at Hz in a small area n-MOSFET) from weak inversion to

2064 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005

Fig. 8. (a) Electron occupation factor(f ), (b) normalized drain current noise, and (c) gate referred voltage noise (measured atf = 100 Hz) versus gate voltage in a small area n-MOSFET (W=L = 0:16 m=0:12 m, t = 15 A).

strong inversion. The readers should be reminded that according to (1) should have a peak around , where is equal to and thus reaches a maximum. In Fig. 8(a), is 0.5 around V (weak inversion) and 1.5 V (strong inversion). Thus, in Fig. 8(b) exhibits two peaks at the above two . Fig. 8(c) shows the measured as well. Again, the double hump feature is noticed.

The possible explanation for the abnormal noise behavior in strong inversion is illustrated in Fig. 5(b). In strong inversion regime, a large causes strong valence electron tunneling and leaves generated holes behind in the channel. The channel is thus in nonequilibrium. and then correspond to electron capture time and hole capture time respectively, as illustrated

Fig. 9. (a) Electron occupation factor(f ), (b) normalized drain current noise, and (c) gate referred voltage noise (measured atf = 100 Hz) versus gate voltage in a small area n-MOSFET (W=L = 0:24/0:18 m, and t = 33 A).

in Fig. 5(b). Because of the increased channel hole concen-tration at a larger , is smaller. The nonequilibrium car-rier distribution also results in the splitting of electron and hole quasi-Fermi-levels. An interface trap between the two quasi- Fermi levels can serve as the recombination center of electrons and holes. As a result, the local electron concentra-tion in the vicinity of the trap is reduced and increases. The increase of and the decrease of lead to a reduced . The second peak of in strong inversion condition V in Fig. 8(b) therefore can be well explained. The authors also would like to remark that the Si substrate trap density in bulk

version. Neither RTS nor the double hump feature in noise power density is observed in strong inversion since valence-bane tun-neling is insignificant in such thick gate oxide devices.

III. CONCLUSION

We identified two low-frequency noise sources in ultrathin oxide (15- ) n-MOSFETs. In weak inversion, the noise arose from electron capture and emission at a shallower interface trap. In strong inversion, we observed an abnormal increase in low-frequency noise. This abnormal noise behavior is not ob-served in a thicker gate oxide (33 ) device, where valence-band tunneling is insignificant. The traditional flicker noise model based on oxide charge tunnel trapping/detrapping cannot ac-count for this excess low-frequency noise. The analysis of RTS patterns and trap occupation factor reveals that the channel is in nonequilibrium at a large gate voltage due to valence-band tunneling. The increased channel hole concentration and a Fermi-level splitting caused by valence-band electron tunneling should be responsible for the excess low-frequency noise.

ACKNOWLEDGMENT

The authors would like to thank TSMC, Taiwan, for providing technical support.

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[7] H. S. Momose, H. Kimijima, S.-I. Ishizuka, Y. Miyahara, T. Ohguro, T. Yoshitomi, E. Morifuji, S.-I. Nakamura, T. Morimoto, Y. Katsumata, and H. Iwai, “A study of flicker noise in n- and p-MOSFETs with ultrathin gate oxide in the direct-tunneling regime,” in IEDM Tech. Dig., 1998, pp. 923–926.

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[9] J. W. Wu, J. W. You, H. C. Ma, C. C. Cheng, C. S. Chang, G. W. Huang, and T. Wang, “Valence-band tunneling induced low-frequency noise in ultrathin oxide (15-A) n-type metal–oxide–semiconductor field effect transistors,” Appl. Phys. Lett., vol. 85, pp. 5076–5077, 2004.

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[17] S. T. Martin, G. P. Li, E. Worley, and J. White, “The gate bias and geom-etry dependence of random telegraph signal amplitudes,” IEEE Trans.

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Jun-Wei Wu (S’02) was born in Tao-Yuan, Taiwan,

R.O.C. He received the B.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1998 and 2004, respectively.

From 2004 to 2005, he was with Macronix Inter-national Company, Ltd. (MXIC), Hsinchu, where he worked on MOS device modeling. Since 2005, he has been with Taiwan Semiconductor Manufacturing Company (TSMC), Ltd., Hsinchu, where he has worked on RF CMOS device optimization and characterization, including RF noise, flicker noise, and device mismatch.

Jian-Wen You was born in Kao-Hsiung, Taiwan,

R.O.C., in 1979. He received the B.S. degree in engineering science from National Cheng-Kung University Tainan, Taiwan, in 2002 and the M.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2004.

In 2004, he joined United Microelectronics Cor-poration (UMC), Hsinchu. His research interest in-cludes the reliability issues and analog performance of CMOS.

Huan-Chi Ma was born in Tainan, Taiwan, R.O.C.,

in 1981. He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2003 and 2005, respectively, where he is currently pursuing the Ph.D. degree.

His research interest includes flicker noise charac-terization and modeling.

2066 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005

Chih-Chang Cheng received the B.S. degree in

physics from National Central University, Taoyuan, Taiwan, R.O.C., in 2002. He is currently pursuing the Ph.D. degree in electronics engineering at the National Chiao-Tung University, Hsinchu, Taiwan.

His research interests include high-voltage power devices and flicker noise.

Chang-Feng Hsu received the B.S. degree from

National Ocean University, Kee-Lung, Taiwan, R.O.C., in 1986, and the M.S. degree in electronics engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1990, where he is currently pursuing the Ph.D. degree.

From 1990 to 1998, he was with the Department of Electrical Engineering, Ming-Hsin University of Technology, Hsinchu, as an Instructor. From 1998 to 2002, he was with the Department of VLSI Technology Development, Etron Technologies Inc., Hsinchu, as a Member of Technical Staff where he was engaged in the development of memory devices design and modeling. From 2002 to 2004, he was with the Department of Technology Development, SiS Technologies Inc., Hsinchu, as a Technical Manager, where he was engaged in the development of deep submicrometer devices and RF devices and circuits. Since 2004, he has been with Taiwan Microelectronics Technologies Inc., Hsinchu. His research interests include reliability issues and hot carrier effects in deep submicrometer MOSFETs and RF CMOS device modeling, flicker noise characterization, and modeling.

Chih-Sheng Chang was born in Hualien, Taiwan,

R.O.C., on November 3, 1964. He received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1986 and 1990, respectively, and the Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, in 1996.

Since 1999, he has been with Taiwan Semicon-ductor Manufacturing Company (TSMC), Ltd., Hsinchu, where he has worked on TCAD, MOS device design, and RF devices optimization and characterization. He has been the main device designer for TSMCs 0.15-m and 0.13-m high-speed devices. Currently, he is a Technology Manager in the Communication Technology Department, Logic Technology Division, where he is in charge of the development of RF active and passive devices for 0.18-, 0.13-, and 90-nm technologies.

Gou-Wei Huang was born in Taipei, Taiwan,

R.O.C., in 1969. He received the B.S. degree in electronics engineering and the Ph.D. degree from National Chiao-Tung University, Hsinchu, Taiwan, in 1991 and 1997, respectively.

He joined National Nano Device Laboratories, Hsinchu, in 1997 as an Associate Researcher. His current research interests focus on microwave device design, characterization, and modeling.

Tahui Wang (S’85–M’86–SM’94) was born in

Tao-Yuan, Taiwan, R.O.C., on May 3, 1958. He received the B.S.E.E. degree from National Taiwan Univer-sity, Taipei in 1980, and the Ph.D. degree in elec-trical engineering from the University of Illinois, Ur-bana-Champaign, in 1985.

From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung Uni-versity, Hsinchu, Taiwan, where he is currently a Professor. His research inter-ests include hot carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices, and nonvolatile semiconductor devices.

Dr. Wang was granted the Best Teacher Award by the Ministry of Education, Taiwan, R.O.C. He has served as technical committee member of many inter-national conferences, including IEDM, IRPS, and VLSI-TSA. His name was listed in Who’s Who in the World.