Task scheduling method for low power dissipation in a system chip

US007779412B2

(12) United States Patent

Lin et al.

US 7,779,412 B2 Aug. 17, 2010

(10) Patent N0.:

(45) Date of Patent:

(54) TASK SCHEDULING METHOD FOR LOW POWER DISSIPATION IN A SYSTEM CHIP

(75) Inventors: Yung-Chia Lin, Taipei (TW); Yi-Ping You, Taichung Hsien (TW); Chung-Wen Huang, Chia-Yi Hsien (TW);

Jenq-Kuen Lee, Hsinchu (TW) (73) Assignee: National Tsing Hua University,

Hsinchu (TW)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35

U.S.C. 154(b) by 1334 days.

(21) App1.N0.: 11/228,283

(22) Filed: Sep. 19, 2005

(65) Prior Publication Data

US 2006/0064696 A1 Mar. 23, 2006

(30) Foreign Application Priority Data

Sep. 21, 2004 (TW) ... .. 93128573 A

(51) Int. Cl.

G06F 9/46 (2006.01) G06F 15/00 (2006.01) G06F 15/16 (2006.01) G06F 13/00 (2006.01) G06F 17/50 (2006.01) G06F 9/455 (2006.01) G06F 1/00 (2006.01)

(52) US. Cl. ... .. 718/102; 712/1; 709/201;

710/100; 703/13; 703/28; 713/300

(58) Field of Classi?cation Search ... .. 710/100;

712/1; 709/201; 718/104*105; 703/l3i28;

713/200

See application ?le for complete search history.

INPUT

(56) References Cited

U.S. PATENT DOCUMENTS

6,097,886 A * 8/2000 Dave et a1. ... .. 703/23 7,174,194 B2 * 2/2007 Chauvel et al. ... .. 455/574 7,552,304 B2 * 6/2009 Marchal et al. ... .. 711/170 2006/0101400 A1 * 5/2006 Capek et a1. .... .. 717/120 2007/0074216 A1 * 3/2007 Adachi et a1. 718/102 2007/0198971 A1 * 8/2007 Dasu et al. ... .. 717/140

OTHER PUBLICATIONS

Lin, Yung-Chia et al. “Power-aware Scheduling for Parallel Security Processors With Analytical Models”. Department of Computer Sci ence, National Tsing-Hua University, Hsinchu, Taiwan. LCPC 2004*

* cited by examiner

Primary ExamineriMeng-Ai An

Assistant ExamineriAdam Lee

(74) Attorney, Agent, or FirmiFitZpatrick, Cella, Harper &

Scinto

(57) ABSTRACT

A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling How of data associated With the tasks among the processing elements, and a main controller including a scheduler, a resource allo cation module, and a poWer management module. The sched uler assigns the tasks on the processing and non-processing elements With reference to time parameters of the processing and non-processing elements. The resource allocation mod ule controls operations of the processing and non-processing elements With reference to task assignments determined by the scheduler. The poWer management module performs dynamic voltage management upon the processing and non processing elements according to the scheduled tasks.

8 Claims, 4 Drawing Sheets

301

INlTIAL WULHIG 0F

‘mas on m; max A 302 common 1m 110mm

0mm n ruu. mm srms

IODEL

TASK "LING 011 P35 BASED ON VALUES DBTAXNED

smnam nmwncu. mar.- _ m PE: AND "0mm, AND , J03 mum-E mm P or ’\/

11m nsxs on m PEs AND NON-PBS mm 1112 ANALYTICAL

304

3208 55mm; mm ANALYTICAL ’\/

IDIEL ‘m! LUIBSI‘ POSSIBLE MEX DISSIPATION AND TIMING smuznms 01' THE TASKS UN Till! NDN-?is 1N STEP S04

WARE SCHEDULING RESULT IN STEP 302 I111! VALUES (IFEAINED IN W 804

INVLRIABLB SCREW-1M;

MELT?

Yes

PROVIDE scmuum RESULT 1o

mom Aimno? mm

307

US. Patent Aug. 17, 2010 Sheet 2 of4 US 7,779,412 B2

FEED TASK DESCRIPTIGN- RECREATION

TO IIAIN CONTROLLER II _ /N V

1

SCHEDULER 111 PERFORMS INITIAL 202

INTERACTIVE SCHEDULING ANALYSIS ,/\/

h? C) pm

RESOURCE ALLOCATION MODULE 112 CONTROLS‘ COMPONENT 203 OPERATION WITH REFERENCE TO TASK SCHEDULING RESULT

DETERMINED BY SCHEDULER 111 /\/

1

POWER MANAGEMENT MODULE 113 PERFORMS DYNAMIC /

VOLTAGE POWER MANAGEMENT UPON THE VARIOUS —

COMPONENTS ACCORDING TO SCHEDULED TASKS

FIG.2

INPUT TASKS TO

BE SCHEDULED ,x 301

INITIAL SCHEDULING 0F

TASKS 0N PES UNDER A 302

CONDITION THAT NON-PEs '

OPERATE AT FULL POWER STATES

I

308

ESTAB SH MLALYTIQ‘L MODEL FOR PEs AND NON—PEs, AND ESTIMATE TIME PARAMETERS OF THE TASKS ON THE PEs AND NON-PEs FROM THE ANALYTICAL MODEL

/

i

I

TASK RESCHEDULING ON PES

7 BASED ON VALUES OBTAINED

IN STEP 304

ESTIMATE FROM ANALYTICAL A MODEL THE LOWEST POSSIBLE POWER DISSIPATION AND TIMING SEQUENCES OF THE TASKS ON THE NON-PEs

304

I

COMPARE SCHEDULING RESULT IN STEP 302 WITH VALUES OBTAINED IN STEP 304

INVARIABLE SCHEDULING ‘

PROVIDE SCHEDULING RESULT TO RESOURCE ALLOCATION MODULE /

FIG.3

305

308

307

US. Patent Aug. 17, 2010 Sheet 4 of4 US 7,779,412 B2

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APPLICATION

This application claims priority of Taiwanese application

no. 093128573, ?led on Sep. 21, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a task scheduling method, more particularly to a task scheduling method for loW poWer dissi pation in a system chip.

2. Description of the Related Art

At present, mobile devices, such as mobile phones, per sonal digital assistants (PDAs), etc., are in Wide use. HoW ever, While these devices require numerous transistors in a System-on-a-Chip (SOC) so as to achieve the purposes of

lightWeight and compact dimensions, the large number of

transistors or logic gates results in escalation in poWer dissi pation. If the problem of poWer dissipation is not resolved, prolonged use of the mobile devices can result in instability due to overheating of the same.

PoWer dissipation in electronic components may be attrib uted mainly to static poWer dissipation caused by leakage current loss in a complementary metal-oxide-semiconductor

(CMOS) circuit, or dynamic poWer dissipation caused by

sWitching transient currents and charging/ discharging of

capacitive loads.

The folloWing equation is used for static poWer dissipation (Pmm-c) estimation:

Pstan'c: VddXN xkdesignxl leakage Equation (1) Wherein Vdd is an input transistor voltage, N is the number of transistors, kdeSl-gn is a design-dependent constant, and I leakage is the leakage current caused by reverse bias leakage of the integrated circuit.

The folloWing equations are used for dynamic poWer dis

sipation (P dynamic) estimation:

Pdynamic:cXaX/€<(Vdd)2 Equation (2) f:k><( Vdf V,)2/Vdd Equation (3) Wherein f is the operating clock frequency, C is the load capacitance, 0t is the sWitching activity, k is a circuit-depen dent constant, Vdd is an input transistor voltage, and vt is the

threshold voltage.

Due to the aforesaid factors of static and dynamic poWer dissipation existing in transistors of a system chip, it is very critical to loWer doWnpoWer consumption of the system chip.

Through the design of loW-poWer circuits and dynamic poWer

management, a system chip can be prevented from reaching high temperatures or even overheating under normal operat ing conditions so as to reduce the problem of heat dissipation.

Hence, manufacturers need not incur additional expense dur

ing chip packaging for overcoming the heat-dissipation prob

lem of system chips While enhancing circuit reliability and prolonging the service lives of the system chips.

To reduce poWer consumption of a system chip, many research papers and patents in the ?eld of variable voltage scheduling techniques are available. For instance, “Task

scheduling for loW-energy systems using variable supply

voltage processor” made public in the Asia and South Paci?c Design Automation Conference (ASPDAC) in 2001, and

“Variable voltage task scheduling for minimiZing energy or

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loWering doWn the overall energy consumption of a system

chip.

US. Pat. No. 5,831,864, titled “Design tools for high-level synthesis of a loW-poWer data pat ”, and US. patent Publi

cation No. 2003/0217090, titled “Energy-aWare scheduling of Application execution”, disclose data paths and principles

for scheduling tasks associated With the loWest poWer dissi pation on multiple processing elements (PEs). In US. patent Publication No. 2003/0217090, there is disclosed a mobile device that manages tasks using a scheduler for scheduling tasks on multiple processors. The scheduling method involves initial scheduling of tasks based primarily on energy consumption criteria, then dispatching the tasks to different processors according to the deadlines thereof so as to obtain an optimum scheduling result With loWest poWer dissipation.

Nevertheless, the prior art only disclose methods for sched uling tasks on different PEs of a system chip to minimiZe poWer consumption of the PEs. The applicants are unaWare of any prior art that also takes into consideration non-PEs, such as 1/0 interfaces, control circuits, etc., of a system chip during task scheduling. It is Well knoWn in the art that, during execu tion of tasks, the task processing ef?ciency is dependent upon the relationships betWeen PER and non-PEs. Therefore, if task scheduling only took PEs of the system chip into con sideration and excluded all non-PEs, the estimated result of overall poWer dissipation of the system chip is most likely to

be imprecise.

SUMMARY OF THE INVENTION

Therefore, the main object of the present invention is to provide a task scheduling method in Which processing and non-processing elements of a system chip are taken into con sideration during task scheduling to ensure loW overall poWer

dissipation of the system chip.

Another object of the present invention is to provide a system chip Which implement the task scheduling method of this invention.

According to one aspect of the present invention, there is provided a task scheduling method for scheduling tasks on a system chip that includes a plurality of processing elements and a plurality of non-processing elements on Which the tasks are to be executed. The task scheduling method comprises the steps of:

a) performing initial scheduling of the tasks on the process ing elements under a condition that the non-processing ele ments operate at full poWer states;

b) establishing an analytical model for the processing and

non-processing elements, and estimating time parameters of

the tasks on the processing and non-processing elements from

the analytical model;

c) determining loWest possible poWer dissipation and tim

ing sequence of the tasks on the non-processing elements according to the analytical model established in step b);

d) generating task scheduling results for the processing

elements With reference to values obtained in step c); and

e) repeating steps c) and d) until the task scheduling results

converge to an invariable scheduling result.

According to another aspect of the present invention, there is provided a task scheduling method for scheduling tasks on a system chip that includes a plurality of processing elements and a plurality of non-processing elements on Which the tasks are to be executed, a scheduler, a resource allocation module,

US 7,779,412 B2 3

and a power management module. The task scheduling method comprises the steps of:

a) enabling the scheduler to analyze time parameters of the

processing and non-processing elements, to assign the tasks

on the processing and non-processing elements With refer ence to the time parameters, and to determine a task sched uling result With a loWest possible poWer dissipation;

b) enabling the resource allocation module to control

operations of the processing and non-processing elements

With reference to the task scheduling result determined by the scheduler; and

c) enabling the poWer management module to perform dynamic voltage management upon the processing and non processing elements according to the scheduled tasks.

According to yet another aspect of the present invention, there is provided a system chip that comprises a plurality of

processing elements for performing primary computations of

a plurality of tasks, a plurality of non-processing elements for controlling How of data associated With the tasks among the processing elements, and a main controller including a sched uler, a resource allocation module, and a poWer management module.

The scheduler assigns the tasks on the processing and non-processing elements With reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements With reference to task assignments determined by the scheduler. The poWer management module

performs dynamic voltage management upon the processing

and non-processing elements according to the scheduled tasks.

BRIEF DESCRIPTION OF THE DRAWINGS Other features and advantages of the present invention Will become apparent in the folloWing detailed description of the preferred embodiment With reference to the accompanying draWings, of Which:

FIG. 1 is a system block diagram illustrating a preferred embodiment of a system chip that implements a task sched uling method according to the present invention;

FIG. 2 is a ?owchart to illustrate hoW the various compo nents of the system chip of FIG. I operate according to this

invention;

FIG. 3 is a ?owchart to illustrate a preferred embodiment of a task scheduling method according to the present invention;

and

FIGS. 4a to 40 illustrate exemplary voltage assignments for three different processing elements of a system chip, the

assignments being obtained through the task scheduling

method of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, a system chip 1 that implements the preferred embodiment of a task scheduling method according to the present invention is shoWn to be embodied in an encryp tion/ decryption semiconductor chip that can execute a variety of tasks, such as data encryption/ decryption, interrupt servic ing, etc. Each task can be executed independently or simul taneously With other tasks. The contents to be processed can include steps of different forms of encryption/ decryption.

HoWever, it can be readily appreciated by those skilled in the design of system chips that the task scheduling method for loW poWer dissipation of this invention should not be limited

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4

for application to the aforesaid encryption/decryption chip since it may also be applied to other types of chips that include similar components.

It should be noted that the method is based on the assump tion that the system chip 1 not only includes processing ele ments (PEs) that have characteristics of dynamic voltage scaling (DVS) and poWer gating (PG), but also includes non processing elements (N on-PEs) that have the same character istics. Moreover, the task scheduling method for loW poWer dissipation according to this invention may be implemented using a computer readable storage medium that includes a plurality of computer program codes to be loaded into a computer so as to enable the latter to execute the method of this invention. The softWare format enables a chip designer to

perform circuit simulation. Alternatively, implementation of

the method of this invention may be conducted using a dedi cated circuit or a programmed module embedded in the sys

tem chip 1, thereby enabling the latter to perform task analy

sis and scheduling in real-time.

In this embodiment, the system chip 1 includes a main controller 11, a processing module 12, a DMA module 13, a pair of external buses 141, 142, and an internal bus 143. The main controller 11 includes a scheduler 111, a poWer man agement module 112, and a resource allocation module 113.

It should be apparent to those skilled in the art that the scheduler 111 may be fabricated as a hardWare component or implemented as a programmed module built into the main controller 11. Alternatively, the operating system (OS) of an external central processing unit (CPU) or an external program may be relied upon to provide the requisite scheduling func tion. In addition, a static method, in Which task scheduling results are obtained after of?ine processing, is also Within the scope of the task scheduling method for loW poWer dissipa tion according to this invention.

The processing module 12 includes a plurality of process ing elements PE l~PEn. In the prior art, optimum poWer con sumption analysis is performed to assign the tasks on the processing elements PE l~PEn. Since the processing times of the processing elements PE1~PEn are different, each of the processing element PEl~PEn noti?es the main controller 11 Whenever a respective operation is ?nished thereby.

The DMA module 13 includes a plurality of channels CH l~CHn, and a plurality of transfer engines 131. The exter nal buses 141, 142 and the internal bus 143 are used to receive data. According to data content in the channels CH1~CHm, the transfer engines 131 request the external buses 141, 142 to transfer data from memory. The transfer engines 131 then pass the data to the processing elements PE 1~PEn via the internal bus 143. Preferably, the internal bus 143 is designed to support high-speed data transmission.

The poWer management module 112 can adjust magnitude of the operating voltage of the various components in the system chip 1 through softWare control. There are four poWer states available for all of the components in the system chip 1:

High (or Full), LoW, Ultra loW, and Sleep. In conjunction With

the scheduler 111, the tasks on the various components can be further assigned any of the aforesaid poWer states.

As evident from Equations (2) and (3) described herein above, When the input voltage (V dd) of a component becomes

higher, the dynamic poWer dissipation (P dynamic) of the com

ponent becomes higher. In the same manner, When the oper ating clock frequency (f) of a component becomes higher, the

dynamic poWer dissipation (P dynamic) of the component

becomes higher as Well. Therefore, When the poWer state of a

component is High, the dynamic poWer dissipation (P dynamic)

of the component is the highest accordingly. In the same manner, When the poWer state of a component is LoW or Ultra

ing of tasks to be processed is heavy, the poWer management module 112 adjusts the poWer states to the High poWer state such that the processing rate and ef?ciency of each compo nent becomes faster. In this manner, the system chip 1 is able to adjust the poWer states according to the loading of tasks so as to achieve an effect of loWer poWer dissipation.

Referring to FIGS. 1 and 2, hoW the various components of the system chip I operate according to this invention Will noW be described in the succeeding paragraphs.

Step 201: First, description information of each task is fed to the main controller 11 via the external bus 141.

Step 202: With reference to the description information, the scheduler 111 performs initial interactive scheduling analysis for the tasks to be scheduled through the use of an analytical model. This Will be described in greater detail in the

succeeding paragraphs.

Step 203: With reference to the task scheduling result determined by the scheduler 111, the resource allocation module 113 controls operations of the various components. In this step, the DMA module 13 is activated such that data for each task ?oWs to the corresponding component for process ing in accordance With the task scheduling result, in Which the component can be any of the processing elements (PEs) and the Non-PEs, such as the DMA module 13, the external buses 141, 142, the internal bus 143, etc.

Step 204: During actual execution of each task, the poWer

management module 113 performs dynamic voltage manage

ment upon the various components according to the sched uled tasks.

The analytical model of the task scheduling method for loW poWer dissipation according to this invention Will noW be described in greater detail hereinafter.

In the folloWing Equation (4), for a unit time period, it is assumed that the processing time spent on Waiting for the

processing elements (PEs) is

the processing time spent on Waiting for the non-processing elements (Non-PEs) is

m

Z 9111"

,

1:1

and that other time not spent on the processing and non processing elements, such as memory access time, transfer times of the external buses 141, 142, initialiZation of the main controller 11, activation delay of the transfer engines 131, etc., is (I). Equation (4) describes the fraction of time relation among the various components Within a unit time period. If the total is 1, When tWo parts of the time relation are knoWn, the remaining part of the time relation can be deduced.

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As evident from Equation (4), from the processing time spent on Waiting for the processing elements (PEs)

and the processing time spent on Waiting for the non-process

ing elements (Non-PEs)

the average latency time attributed to the Non-PEs may be estimated for scheduling planning based on the result.

The folloWing stabiliZing conditions are set for system

scheduling: Rate for entering the processing elements equals

rate for actual processing by the processing elements; and Total input/ output data rate of the processing elements equals total transmission rate Within the internal bus 143.

FIG. 3 is a ?owchart to illustrate the preferred embodiment of the task scheduling method according to the present inven tion. In this embodiment, the channels CH1~CHm and the internal bus 143 are used as Non-PEs. The task scheduling method can be generally subdivided into three stages;

The ?rst stageiln step 301, the tasks to be scheduled are inputted. Then, in step 302, initial scheduling of the tasks on the processing elements PEl~PEn is performed. In this step,

the operating voltages of the processing elements PEl~PEn

are determined under a condition that the Non-PEs operate at full poWer states for maximum performance, and the sched uler 111 assigns the tasks on the processing elements PEl~PEn according to a ?rst-come, ?rst-served scheduling rule With reference to inspected deadlines of the various tasks.

Since the principle of assigning tasks based on a ?rst-come,

?rst-served scheduling rule is knoWn in the art and is not the main feature of the invention, a detailed description of the same Will be omitted herein for the sake of brevity.

The second stageiln step 303, an analytical model for the

processing elements PEl~PEn and the non-processing ele

ments is established, and time parameters of the tasks on the

processing elements PE1~PEn and the non-processing ele

ments are estimated from the analytical model. In this step,

the latency of processing ef?ciency of the processing ele

ments PEl~PEn attributed to the other non-processing ele ments is evaluated. The factors that affect such latency include poWer dissipation and time parameters.

Thereafter, in step 304, from the analytical model, the

effect of the Non-PEs (i.e., the channels CH1~CHm and the internal bus 143) is determined for estimating the loWest poWer dissipation and timing sequence of the tasks on the Non-PEs. In this step, operating voltages for the channels CH1~CHm and the internal bus 143 are determined, and the average time spent by the Non-PEs on the tasks are calculated as Well. Then, in step 305, the scheduling result obtained in step 302 is compared With the values obtained in step 304.

US 7,779,412 B2 7

The third stageiin step 306, it is determined if an invari able scheduling result has been obtained. If the task schedul ing results do not converge to an invariable scheduling result, the How goes to step 308, in Which the tasks are rescheduled on the processing elements PEl~PEn With reference to the values obtained in step 304. That is, the scheduler 111 per forms iterative interactive analysis by repeating steps 303 to 305 until the task scheduling results converge to an invariable scheduling result. The invariable scheduling result in then provided to the resource allocation module 113 in step 307.

The folloWing example is provided to illustrate the effect of the task scheduling method of this invention. In the example, the system chip 1 has three processing elements (PE1~PE3), tWo internal buses (IBUS1, IBUSZ), and three channels (CHl~CH3). There are eight tasks (T1~T8) to be executed.

Each task has a respective arrival time, deadline time and execution time in the full poWer state as shoWn in the folloW ing Table 1:

TABLE 1

task arrival time deadline time execution time

T 1 0 100 20

T2 0 100 20

T3 0 100 20

T4 10 15 0 10

T5 10 15 0 10

T6 10 15 0 10

T7 30 200 30

T8 30 200 30

Description information of the tasks (T 1~T8) to be sched uled is inputted to the scheduler 111 that performs initial scheduling on a ?rst-come, ?rst-served basis. The Non-PEs (i.e., the tWo internal buses IBUSl, IEUS2, and the three channels CHl~CH3) are ?rst set to be in their full poWer states, and the operating voltages of each task over the pro cessing elements are obtained. The initial scheduling results are shoWn in the folloWing Table 2:

TABLE 2

start processing operating deadline execution

task time element voltage time time

T1 0 PE 1 LoW 50 50

T2 50 PE 1 Full 20 70

T3 70 PE 1 Full 20 90

T4 10 PE2 ultra 10W 50 60

T5 60 PE2 ultra 10W 50 110

T6 1 10 PE2 LoW 3 0 140

T7 3 0 PE3 LoW 80 1 10

T8 1 10 PE3 LoW 80 190

Then, an analytical model for the processing elements (PE1~PE3), the buses (IBUSl, IBUS2), and the channels (CHl~CH3) is established. Time parameters are estimated based on the analytical model so as to determine the loWest possible poWer dissipation and the timing sequence of the tasks (T1~T8) on the buses (IBUS1, IBUS2) and the channels (CHl~CH3). The poWer states of the buses (IBUSl, IBUS2) and the channels (CH l-CH3) thus obtained are shoWn in the:

folloWing Table 3:

Non-processing element Power state

IBUS 1 lOW

IBUS 1 lOW

CH 1 10W

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-continued

Non-processing element Power state

CH2 lOW

CH3 lOW

Based on the poWer states of the buses (IBUS1, IBUS2) and the channels (CH1~CH3) listed in Table 3, the time spent on

the buses (IBUSl, IBUS2) and the channels (CH 1~CH3) dur ing servicing of each task (T1~T8) is calculated and reported

to the scheduler 111. The scheduler 111 then determines neW

operating voltages for the tasks (T l-Ts) on the processing

elements (PE l~PE3) to achieve the object of loWer poWer dissipation, as shoWn in the folloWing Table 4:

TABLE 4

start processing operating deadline execution

task time element voltage time time

T1 0 PE 1 low 53 53

T2 53 PE 1 full 23 76

T3 76 PE 1 full 23 99

T4 10 PE2 ultra 10W 53 63

T5 63 PE2 ultra 10W 53 116

T6 1 1 6 PE2 10W 3 3 149

T7 3 0 PE3 10W 83 1 13

T8 1 13 PE3 10W 83 199

As shoWn in FIGS. 4a, 4b and 40, after iterative interactive

scheduling analysis, the folloWing invariable scheduling

result is obtained:

1. The processing element (PEI) processes tasks (T1~T3) After processing task (T l), the poWer state of the processing element (PEI) changes from loW to high and then to sleep.

2. The processing element (PE2) processes tasks (T4~T6) After processing tasks (T4, T5), the poWer state of the pro cessing element (PE2) changes from ultra loW to high and then to sleep.

3. The processing element (PE3) processes tasks (T7~T8) The poWer state of the processing element (PE3) changes from sleep to loW and then back to sleep.

In sum, in a complicated system chip, Whenever a task is processed in a processing element, a certain amount of time must be spent on an associated non-processing element. In the prior art, the effect of the non-processing elements over the scheduling of tasks on the processing elements is ignored such that the estimated poWer dissipation of the entire system chip is inaccurate. Since the task scheduling method of this invention takes into account both processing and non-pro

cessing elements of the system chip during task scheduling,

loWer poWer dissipation can be achieved accordingly.

While the present invention has been described in connec tion With What is considered the most practical and preferred embodiment, it is understood that this invention is not limited to the disclosed embodiment but is intended to cover various arrangements included Within the spirit and scope of the broadest interpretation so as to encompass all such modi?ca tions and equivalent arrangements.

We claim:

1. A task scheduling method for scheduling tasks on a system chip that includes a plurality of processing elements and a plurality of non-processing elements on Which the tasks are to be executed, said task scheduling method comprising the steps of:

non-processing elements, and estimating time param

eters of the tasks on the processing and non-processing elements from the analytical model, Wherein the time parameters correspond to the processing times of the tasks on assigned ones of the processing and non-pro

cessing elements;

c) determining loWest possible poWer dissipation and tim

ing sequence of the tasks on the non-processing ele ments according to the analytical model established in

step b);

d) generating task scheduling results for the processing

elements With reference to values obtained in step c);

and

e) repeating steps c) and d) until the task scheduling results

converge to an invariable scheduling result.

2. The task scheduling method as claimed in claim 1, Wherein, in step a), the tasks are scheduled on the processing elements in a ?rst-come, ?rst-served manner.

3. A computer program stored on a computer-readable medium, comprising program instructions for causing a com puter to perform consecutively the task scheduling method steps as claimed in claim 1.

4. A task scheduling method for scheduling tasks on a system chip that includes:

a plurality of processing elements and a plurality of non processing elements on Which the tasks are to be

executed,

a scheduler,

a resource allocation module, and a poWer management module,

said task scheduling method comprising the steps of:

a) enabling the scheduler to analyZe time parameters of the processing and non-processing elements, to assign the tasks on the processing and non-processing elements With reference to the time parameters, and to determine a task scheduling result With a loWest pos sible poWer dissipation, Wherein the time parameters correspond to the processing times of the tasks on assigned ones of the processing and non-processing

elements;

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c) enabling the poWer management module to perform

dynamic voltage management upon the processing

and non-processing elements according to the sched uled tasks.

5. The task scheduling method as claimed in claim 4, Wherein, in step a), the scheduler performs iterative interac tive analysis to determine the task scheduling result.

6. A computer program stored on a computer-readable medium, comprising program instructions for causing a com puter to perform consecutively the task scheduling method steps as claimed in claim 4.

7. A system chip comprising:

a plurality of processing elements for performing primary computations of a plurality of tasks;

a plurality of non-processing elements for controlling How of data associated With the tasks among said processing elements; and

a main controller including a scheduler, a resource alloca tion module, and a poWer management module, said scheduler assigning the tasks on the processing and

non-processing elements With reference to time param eters of the processing and non-processing elements, Wherein the parameters correspond to the processing times of the tasks on assigned ones of the processing and

non-processing elements,

said resource allocation module controlling operations of said processing and non-processing elements With ref erence to task assignments determined by said sched uler, said poWer management module performing

dynamic voltage management upon said processing and

non-processing elements according to the scheduled

tasks,

Wherein said scheduler performs iterative interactive analysis to determine a task scheduling result having

loWest possible poWer dissipation.

8. The system chip as claimed in claim 7, Wherein said non-processing elements include at least one of an internal bus and a data channel.