Storage Systems
郭大維 教授
ktw@csie.ntu.edu.tw
嵌入式系統暨無線網路實驗室
(Embedded Systems and Wireless Networking Laboratory)
國立臺灣大學資訊工程學系
Reading:
Kam-yiu Lam and Tei-Wei Kuo, “Real-Time Database Systems: Architecture and Techniques”, Kluwer Academic Publishers, 2000
Krishna and Kang, “Real-TimeSystems,” McGRAW-HILL, 1997.
Storage Systems
Real-Time Disk Scheduling
Flash-Memory Storage Systems
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Real-Time Disk Scheduling
Motivation: Disparity between CPU and disk speed.
access time = queuing time + seek time + latency delay + transfer time
Strategies to improve the performance of disk service:
First-come-first-served (FCFS) algorithm * :
Poor because of no consideration in deadlines and arm movements.
Earliest-deadline-first (EDF) algorithm:
Not optimum in minimizing the number of transaction deadlines missed.
Track
1 4 380 390
Requests Deadlines Track
1 20 390
2 40 1
3 60 380
4 80 4
Real-Time Disk Scheduling
Scan (or elevator) algorithm * :
Start at one end of the disk, and moves toward the other end, servicing requests as it reaches each track, until it gets to the other end of the disk.
At the other end, the direction of head movement is reversed and servicing continues.
Bad for service requests at either end of a disk.
C-Scan (Circle Scan) algorithm * :
Goal: Provide a more uniform wait time.
As does Scan scheduling, servicing requests as it goes. However, when the head reaches one end, it immediately returns to the beginning of the
Track
queue=295, 30, 150
30 295
queue=5, 70, 225
150 225 399
70
5
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Real-Time Disk Scheduling
Shortest-seek-time-first (SSTF)algorithm * :
A greedy algorithm which always selects the request with the minimum seek time from the current request queue.
Starvation of some requests...
A variation of SCAN:
Classify requests into classes.
Service requests in the same class in terms of SCAN.
Service classes in order of their priorities.
Q: How many priority levels are enough, and how to partition them?
* means no consideration of deadlines.
Track
queue=305, 30, 5, 225
30 70 150 225 305 399
5
queue=305, 150
Real-Time Disk Scheduling
A weighted scheduling algorithm:
Sort requests in the waiting queue in the increasing order of their deadlines.
Each request is assigned a weight w i depending on their order in the queue.
Let δ i be the distance the arm has to move from its current position to serve the request.
Consider q requests at a time to reduce the algorithm complexity.
Service the request with the highest priority p i = 1/ (w i δ i ) Q: How to assign processes weights w i ?
A variation of the weighted scheduling algorithm:
Motivation: Consider deadline instead of deadline order!
Service the request with the highest priority p i = f(d i , δ i ) = α δ i + (1-α) d i . α is a design factor, and choosing α in the range 0.7 to 0.8 looks good.
Reading: A. Silberschatz and P.B. Galvin, “Operating System Concepts,” 4th Ed., Addison-Wesley Publishing Company, 1994.
C.M. Krishna and K.G. Shin, “Real-TimeSystems,” McGRAW-HILL, 1997.
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Real-Time Disk Scheduling
Another paper for discussion:
A.L. N. Reddy and J.C. Wyllie, “I/O Issues in Multimedia System,” IEEE Transactions on Computers, March 1994.
Flash-Memory Storage Systems
郭大維 教授
ktw@csie.ntu.edu.tw
嵌入式系統暨無線網路實驗室 (Embedded Systems and Wireless
Networking Laboratory) 國立臺灣大學資訊工程學系
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Agenda
Introduction
Management Issues
Performance vs Overheads Other Challenging Issues Conclusion
Introduction – Why Flash Memory
Diversified Application Domains
Portable Storage Devices Critical System Components Consumer Electronics
Industrial Applications
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Introduction – The Reality
Tremendous Driving Forces from Application Sides
Excellent Performance Huge Capacity
High Energy Efficiency Reliability
Low Cost
Good Operability in Critical Conditions
Introduction – The Characteristics of Storage Media
[Reference] DRAM:2-2-2 PC100 SDRAM. NOR FLASH: Intel 28F128J3A-150.
NAND FLASH: Samsung K9F5608U0M. Disk: Segate Barracuda ATA II. 1
1. J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A space-efficient flash translation layer for compact-flash systems.
- 12.4 ms(512B)
(average) 12.4ms (512B)
(average)
DISK
2ms (16KB) 201us (1B)
226us (512B) 10.2us (1B)
35.9us (512B)
NAND FLASH
1.2s (16KB) 211us (1B)
3.52ms (512B) 150ns (1B)
14.4us (512B)
NOR FLASH
- 60ns (2B)
2.56us (512B) 60ns (2B)
2.56us (512B)
DRAM
Erase Write
Read
Access time
Media
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Introduction – Challenges
Requirements in Good Performance Limited Cost per Unit
Strong Demands in Reliability Increasing in Access Frequencies
Tight Coupling with Other Components Low Compatibility among Vendors
Agenda
Introduction
Management Issues
Performance vs Overheads
Other Challenging Issues
Conclusion
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Management Issues – System Architectures
AP
File-System Layer
AP AP
Block Device Layer (FTL emulation)
Flash Memory MTD drivers
AP
Management Issues – Flash-Memory Characteristics
……
Block 0 Block 1 Block 2 Block 3
Erase one block 1 Page = 512B
1 Block = 32 pages(16KB)
……
Write one
page
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Management Issues – Flash-Memory Characteristics
Write-Once
No writing on the same page unless its residing block is erased!
Pages are classified into valid, invalid, and free pages.
Bulk-Erasing
Pages are erased in a block unit to recycle used but invalid pages.
Wear-Leveling
Each block has a limited lifetime in erasing counts.
Management Issues – Flash-Memory Characteristics
Example 1: Out-place Update
Live pages Free pages
A B C D
Suppose that we want to update data A and B…
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Dead pages
A B C D A B
Management Issues – Flash-Memory Characteristics
Example 1: Out-place Update
A live page A dead page A free page This block is to be recycled.
(3 live pages and 5 dead pages)
L D D L D D L D
L L D L L L F D
L F L L L L D F
F L L F L L F D
Management Issues – Flash-Memory Characteristics
Example 2: Garbage Collection
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L L D L L L D
L F L L L L D L L F L L F D
L L
D D D D
A live page A dead page A free page
Live data are copied to somewhere else.
L
D D D
D
Management Issues – Flash-Memory Characteristics
Example 2: Garbage Collection
A live page A dead page A free page
The block is then erased.
Overheads:
•live data copying
•block erasing.
L L D L L L D
L F L L L L D L L F L L F D
L L F F F F F F F F
L
Management Issues – Flash-Memory Characteristics
Example 2: Garbage Collection
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Management Issues – Flash-Memory Characteristics
Example 3: Wear-Leveling
L D D L D D L D
L L D L L L F D
L F L L L L D F
F L L F L L F D
100
10
20
15
Erase cycle counts
Wear-leveling might interfere with the
decisions of the block- recycling policy.
A live page A dead page A free page
A
B
C
D
Management Issues – Policies: FTL
FTL adopts a page-level address translation mechanism.
The main problem of FTL is on large memory space
requirements for storing the address translation information.
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Management Issues – Policies: NFTL
A logical address under NFTL is divided into a virtual block address and a block offset.
e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3
. . .
(9,23)
Write data to LBA=1011
. . .
NFTL
Address Translation Table (in main-memory)
Free Free Free Used
Free Free Free Free
Used Used Used Free Free Free Free Free A Primary Block
Address = 9
A Replacement Block Address = 23
VBA=126
Block Offset=3
If the page has been Write to the used
first free page
Management Issues – Policies: NFTL
NFTL is proposed for the large-scale NAND flash storage systems because NFTL adopts a block-level address translation.
However, the address translation
performance of read and write requests might deteriorate, due to linear searches of address translation information in primary and replacement blocks.
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Management Issues – Policies
Small Large
Memory Space Requirements
Long Short
Address Translation Time
More Less
Garbage Collection Overhead
Low High
Space Utilization
NFTL FTL
The Memory Space Requirements for one 256MB NAND (512B/Page, 4B/Table Entry, 32 Pages/Block)
FTL: 2,048KB (= 4*(256*1024*1024)/512) NFTL: 64KB (= 4*(256*1024*1024)/(512*32))
Management Issues – Flash- Memory Characteristics
*FTL: Flash Translation Layer, MTD: Memory Technology Device
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Management Issues – Observations
The write throughput drops significantly after garbage collection starts!
The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly.
Reliability becomes more and more critical when the manufacturing capacity increases!
The significant increment of flash-memory access numbers seriously exaggerates the Read/Program Disturb Problems!
Agenda
Introduction
Management Issues
Performance vs Overheads
Other Challenging Issues
Conclusion
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System Architecture
Garbage Collection
Address
Translation FTL Layer File system (FAT, ext2...)
Device Driver fwrite(file,data)
Block write (LBA,size)
Flash I/O Requests
Control signals
File Systems process process
process Applications
Flash-Memory Storage System
Physical Devices (Flash Memory Banks)
Flash Management
Objectives
Performance
Memory Overheads
User data . . .
Logical Block Address (array index)
Physical Block Address (block,page)
Physical Block Address (block,page) Access LBA = 3
Address Translation
Table (in main-memory) Flash memory 0,0
0,1 0,2 0,3 0,4 0,5 0,6 0,7 1,0 1,1 1,2 1,3
(0,3) (0,1) (0,6) (0,4) (4,7) (1,0) (2,1) (1,2) (1,3)
0 1 2 3 4 5 6 7 8 9 10 11
. . .
Spare data
Spare data
LBA=3;
ECC=. . .;
Status=. . .;
Space Utilization Garbage Collection Cost
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Flash Management
Stripping Designs
Efficient Hot-Data Identification Reliability
Address Translation Efficiency Large-Scale Flash
Stripping Designs
Why?
Could we boost the system performance and enlarge the system capacity by simply having multiple flash banks working together?
Issues
Space Utilization vs Wear-Leveling Stripping Levels vs Performance
Performance vs Management Granularity
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Stripping Designs – Parallelism
An Example Parallelism in Write Operations
c
data busy data c busy
c
data busy
c
data busy
command
Measured performance:
¾command + data = 313 μsec
¾busy = 606 μ sec
Stripping Designs
Each bank can operate (read/write/erase) independently.
One Common Technical Issue:
How to smartly distribute write requests among banks?
Bank #0 Bank #1 Bank #2 Bank #3
Decoder
Latch Latch Latch Latch
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Stripping Designs
Potential Issues
Static or Dynamic Stripping
Performance Boosting Bound?
Access Locality
Hot versus Cold Data
Stripping Designs – A Static Striping Policy
A typical static striping policy would
“evenly” scatter write requests over banks to improve the parallelism.
A RAID-0-Based Approach:
Bank address = (LBA) % (# of the total number of banks)
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Stripping Designs – A Static Striping Policy
0 1 2 3
0 1 2 3
4 5 6 7
4 5 6 7
True “fair usages” of banks could be hardly achieved by static striping!
Stripping Designs – A Snapshot of
a Realistic Workload
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Stripping Designs – Hot data
Hot data usually come from
meta-data of file-systems, and
Small. A piece of hot data is usually ≦ 2 sectors.
structured (or indexed) user files, etc.
Storing of hot data on a statically assigned bank might
consume free space quickly,
start garbage collection frequently, or wear their residing banks quickly.
Stripping Designs – Cold Data
Cold data usually come from
read-only (or WORM) files.
E.g., bulk and sequential files that often have a number of sectors.
Storing of cold data on a statically assigned bank might
increase the capacity utilization, and deteriorate the efficiency of garbage collection severely.
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Stripping Designs – A Dynamic Striping Policy
Main Strategies:
Distribute hot/cold data properly among banks.
Hot data Æ banks have low erase cycle counts.
Cold data Æ banks have low capacity utilizations.
Remark: The hotness of written data should be efficiently identified!!!
Stripping Designs – Dynamic Striping
0 15 16 0 5 6 7 8 9 10
0 15
16 0
5
6
7 8
9 10
Hot data Cold data
100 200 250 300
Erase cycle
count
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Stripping Designs – A Hot-Cold Identification Mechanism
New element with LBA is added if the LBA does not exist in any list.
Element is discarded if the candidate list is full.
Element is promoted to the hot list if the LBA already exists in the candidate list.
Element is demoted to the candidate list if
the hot list is full.
Candidate list Hot list
Stripping Designs – Address Translation
U s e r A r e a
S p a r e A re a
s p a re
L B A = 3 ; E C C = ...;
S ta tu s = ...;
. . . .
. .
L B A (a rra y in d e x )
P h y s ic a l a d d re s s (b a n k ,b lo c k ,p a g e )
p h y s ic a l a d d re s s ( b a n k ,b lo c k ,p a g e ) A c c e s s
L B A = 3
A d d r e s s T r a n s la tio n
T a b le ( In R A M ) F la s h m e m o r y
0 ,0 ,0 0 ,0 ,1 0 ,0 ,2 0 ,0 ,3 0 ,0 ,4 0 ,0 ,5 0 ,0 ,6 0 ,0 ,7 0 ,1 ,0 0 ,1 ,1 0 ,1 ,2 0 ,1 ,3
0 ,0 ,3 0 ,0 ,1 0 ,0 ,6 0 ,0 ,4 0 ,4 ,7 0 ,1 ,0 1 ,2 ,1 0 ,1 ,2 2 ,1 ,3
0
1
2
3
4
5
6
7
8
9
1 0
1 1
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Stripping Designs – Performance Evaluation
0 5,000 10,000 15,000 20,000 25,000 30,000 35,000 40,000
1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 Write Requests Processed So Far
W ri te R equ es t R e s p ons e T im e (u s )
4 Banks 2 Banks 1 Bank
B a n k 0 B a n k 1 B a n k 2 B a n k 3 E ra s e c yc le c o u n ts
(D yn a m ic ) 3 5 0 3 5 2 3 4 8 3 5 0
E ra s e c yc le c o u n ts
(S ta tic ) 3 0 7 4 7 5 3 7 3 3 3 4
C a p a c ity U tiliza tio n
(D yn a m ic ) 0 .7 6 0 .7 6 0 .7 6 0 .7 6
C a p a c ity U tiliza tio n
(S ta tic ) 0 .7 2 0 .8 1 0 .7 7 0 .7 4
B a n k 0 B a n k 1 B a n k 2 B a n k 3 E ra s e c yc le c o u n ts
(D yn a m ic ) 3 5 0 3 5 2 3 4 8 3 5 0
E ra s e c yc le c o u n ts
(S ta tic ) 3 0 7 4 7 5 3 7 3 3 3 4
C a p a c ity U tiliza tio n
(D yn a m ic ) 0 .7 6 0 .7 6 0 .7 6 0 .7 6
C a p a c ity U tiliza tio n
(S ta tic ) 0 .7 2 0 .8 1 0 .7 7 0 .7 4
When the Flash Capacity
Is Fixed
Flash Management
Stripping Designs
Efficient Hot-Data Identification Reliability
Address Translation Efficiency
Large-Scale Flash
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Efficient Hot-Data Identification – A Snapshot of a Realistic Workload
Efficient Hot-Data Identification –
Why Important?
Wear-Leveling
Pages that contain hot data could turn into dead pages very quickly.
Blocks with dead pages are usually chosen for erasing.
Hot data should be written to blocks with smaller erase counts.
Erase Efficiency (i.e., effective free pages reclaimed from garbage collection.)
Mixture of hot data and non-hot data in blocks
might deteriorate the efficiency of erase operations.
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Efficient Hot-Data Identification
Related Work
Maintain data update times for all LBA’s (Logical Block Addresses) 1
Introduce significant memory-space overheads
Have a data structure to order LBA’s in terms of their update times 2
Require considerable computing overheads
Our Approach
A Multi-Hash-Function Framework
Identify hot data in a constant time Reduce the required memory space
2. L. P. Chang and T. W. Kuo, “An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems,” 8th IEEE RTAS, September 2002, pp. 187-196
1. M. L. Chiang, Paul C. H. Lee, and R. C. Chang, “Managing Flash Memory in Personal Communication Devices,” ISCE ’97, December 1997, pp. 177-182
Efficient Hot-Data Identification –
A Multi-Hash-Function Framework
K independent hash functions
M-entry hash table C-bit counters
Checkup
Status Update Decay
f k (y) f 1 (y)
f 2 (y)
……
0 1 2
M – 1
……
C-bit counter
Hash functions
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3. Check if the H most significant bits of every counter of the K hashed values contain a non-zero bit value.
Efficient Hot-Data Identification –
A Multi-Hash-Function Framework
y
Logical Block Address
1. An LBA is to be verified as a location for hot data.
f 4 (y) f 1 (y)
f 2 (y)
f 3 (y)
1 0 1 1
1 1 0 1 1 0 1 0 0 0 1 1
2. The corresponding LBA y is hashed simultaneously by K given hash functions.
H most significant Bits z
f 4 (z) f 1 (z)
f 2 (z)
f 3 (z)
1 1 1 1 1 0 0 0 0 1 1 1
– Hotness Checkup
f 4 (y) f 1 (y)
f 2 (y)
f 3 (y)
1 0 1 1
1 1 0 1 1 0 1 0 0 0 1 1
2. The corresponding LBA y is hashed simultaneously by K given hash functions.
3. Each counter corresponding to the K hashed values (in the hash table) is incremented by one to reflect the fact that the LBA is written again,
1 1 0 0
1 1 1 0 1 0 1 1 0 1 0 0
Efficient Hot-Data Identification –
A Multi-Hash-Function Framework
y
Logical Block Address
1. A write is issued to the FTL.
– Status Update
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Efficient Hot-Data Identification –
A Multi-Hash-Function Framework
For every given number of sectors have been written, called the “decay period” of the write numbers, the values of all counters are divided by 2 in terms of a right shifting of their bits.
H most significant Bits
1 0 1 1
1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1
0 1 1 0 0 1 0 1 0
0 0 0 0 0
0
0 0 0 1
0 0 0 0 0 0
0 0 0
0 0 0
– Decay
Efficient Hot-Data Identification –
Implementation Strategies
A Column-Major Hash Table
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(1 – (1 – 1/M) 2NRK ) K – R
K Number of Hash Functions
R Ratio of Hot Data in All Data (< 50%)
N Number of Write References
M Number of Counters/Entries in a Hash Table
Notation System Model Parameters
Efficient Hot-Data Identification –
Analytic Study
The probability of false identification of an LBA as a location for hot data:
Ratio of Hot Data to All Data (%)
Efficient Hot-Data Identification –
Impacts of Hash-Table Sizes
Ratio of False Hot-Data Identification (%)
The locality of data access (decay period: 5117 writes)
Ratio of false hot-
data identification
for various hash-
table sizes
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Efficient Hot-Data Identification –
Impacts of Decay Period
0 5 10 15 20 25 30 35 40
0.25 0.5 0.75
1 1.25 1.5 1.75
2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.8 Direct Address
Multi-Hash-Function
The Number of Write Requests So Far (unit: 1279 writes) Decay Period
(unit: 5117 writes)
Ratio of Hot Data to All Data
Efficient Hot-Data Identification –
Runtime Overheads
N/A N/A
90.7671 3565
Decay
11453.72 12301.75
45.09809 1537.848
Status Update
2328.367 4126.353
97.98981 2431.358
Checkup
Standard Deviation Average
Standard Deviation Average
Two-Level LRU List*
(512/1024) Multi-Hash-Function
Framework (2KB)
Unit: CPU cycles
* L. P. Chang and T. W. Kuo, “An Adaptive Striping Architecture for Flash Memory Storage
Systems of Embedded Systems,” 8th IEEE RTAS, September 2002, pp. 187-196
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Agenda
Introduction
Management Issues
Performance vs Overheads Other Challenging Issues Conclusion
Challenging Issues – Reliability
Selected cell I DS
Control Gate
Drain
Source
Each Word Line is connected to control gates.
Each Bit Line is connected to the drain.
Cell
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Challenging Issues – Reliability
Read Operation
When the floating gate is not charged with electrons, there is current I D (100uA) if a reading voltage is applied. (“1” state)
5V
1V
Program Operation
Electrons are moved into the floating gate, and the threshold voltage is thus raised.
Challenging Issues – Reliability
Over-Erasing Problems
Fast Erasing Bits Æ All of the cells connected to the same bit line of a depleted cell would be read as “1”, regardless of their values.
Read/Program Disturb Problems
DC erasing of a programmed cell, DC Programming of a non-programmed cell, drain disturb, etc.
Flash memory that has thin gate oxide makes disturb problems more serious!
Data Retention Problems
Electrons stored in a floating gate might be lost such that
the lost of electrons will sooner or later affects the charging
status of the gate!
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Challenging Issues – Observations
The write throughput drops significantly after garbage collection starts!
The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly.
Reliability becomes more and more critical when the manufacturing capacity increases!
The significant increment of flash-memory access numbers seriously exaggerates the Read/Program Disturb Problems!
Wear-leveling technology is even more critical when flash memory is adopted in many system components or might survive in products for a long life time!
Conclusion
Summary
Striping Issues
Hot-Data Identification
Challenging Issues
Scalability
Scalability Technology
Reliability Technology
Customization Technology
1/25/2006 Embedded Systems and Wireless Networking Lab. 67
Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.