Gate Dielectrics and Cell Membrane Studies for La2O3/ Si0.3Ge0.7 p-MOSFETs and Biologic Cells

閘極介電材料與細胞膜在氧化鑭之矽鍺電晶體與生物細胞上的研究

研究生：吳建宏 指導教授：荊鳳德教授

謝 家教授 中華大學電機系電機研究所

摘要

我們已經發展出一個簡單方法形成高介電係數的氧化鑭閘極，就是沉積鑭薄

膜再直接熱氧化。由於應用低氧化溫度，減少氧化鑭厚度使介電質完整地改善。

從測量電容值，這 60 Å的氧化鑭有27的K值，它的等效氧化層厚度是8.7Å。從

MOSFET's 的高電流驅動和轉移電導隨著低的off-state的電流進一步證據高介

電質的長遠性。它被發現與二氧化矽比起來有低應力引發的漏電流(SILC)和高電

荷崩潰，它被證實有極好可靠性。那低的等效氧化物厚度是由於在矽上的高熱力

穩定性以及用氫氣穩定的在550^oC以下退火。

同時我們也發展出成長磊晶矽鍺合金的新方法。這方法主要是藉由固相磊晶

法將沈積在矽基板上的無晶狀錯層在高溫下趨入並形成矽鍺磊晶層。我們發現晶

片表面殘存原生氧化層的存在與否對於矽鍺層的品質有重大的影響。為了評估此

矽鍺層應用於實際元件的可行性，我們做了以矽鍺為通道的電晶體。然而，這樣

的結果和以往的文獻記載並不相同，我們推測這樣的差異是因為此方法形成的矽

鍺層已是應力釋放過的材料。因此，並不會有應力在高溫氧化釋放造成缺陷的現

象。儘管如此,此矽鍺層氧化層仍會因錯原子累積在氧化層和矽鍺介面而造成其

介面缺陷密度稍高於傳統的二氧化矽。

因此我們也將結合上述成長閘極氧化層與矽鍺層的技巧，來應用於P 型電

晶體的通道,其展現了較好的電流,驅動力與次臨界特性。這項技術的優點不僅在

於其簡單,經濟,最重要的是它完全相容於現有的積體電路製程技術。

未來隨著元件尺寸的不斷縮小，閘極氧化層的厚度也必須隨之減少。原來

的閘極氧化層的厚度可能到一個臨界值，我們也正在研究以細胞為介電材料的可

行性而做了一系列的細胞與電場之間相關的研究。

Gate Dielectrics and Cell Membrane Studies for La2O3/ Si0.3Ge0.7 p-MOSFETs and Biologic Cells

Student: C. H. Wu Advisor: Dr. Albert Chin Dr. I. J. Hsieh

Abstract

We have developed high K La2O3 gate dielectrics by a simple process using direct thermal oxidization of deposited La. The dielectric integrity improves as decreasing La2O3 thickness because of the applied low oxidation temperature.

From the measured capacitance, the 60Å La2O3 has a K value of 27 that has an equivalent oxide thickness of 8.7Å. This high K is further evidenced from MOSFET’s high current drive and transconductance with low off-state current.

Low stress-induced leakage current and high charge-to-breakdowncomparable with SiO2 are obtained that demonstrates excellent reliability. The achieved low equivalent oxide thickness is due to the high thermodynamic stability on Si and also stable for hydrogen annealing up to 550^oC.

At the same time, it is developed a new approach to form epitaxial SiGe layer .The epitaxial SiGe was formed by the deposition of amorphous Ge layer and subsequent high temperature annealing through the mechanism of solid phase epitaxy. It was found that the existence of native oxide plays a critical role in the quality of SiGe layer. To evaluate the feasibility of this SiGe layer in practical applications, it has been fabricated SiGe channel MOSFET's. However,

formed in this method is a relaxed material and may not suffer from the strain-relaxation related problems in the high temperature oxidation step.

Therefore, we have successfully integrated two techniques into current VLSI technology to fabricate SiGe cham1el PMOSFET's with high k dielectric. It manifests batter current drive capability and batter subthreshold swing. More important, this approach is simple, less expensive and fully compatible with current VLSI tech1ology.

In the future, according to the continuous scaling down of device, the thickness of gate oxide has to be reduced. The thickness of gate oxide will be decreased to the limitation. It also has been investigated into the feasibility of the biological cell, in order to substitute for gate dielectric. Then it is experimenting with the relationship between the cell and the electric field.

Acknowledgement

I would like to thank Prof. Albert Chin, Prof. I. J. Hsieh and Prof.

S.J. Wang for their fruitful discussion and illuminative comment. In

addition, I am also grateful to my group members for their enthusiastic

assistance and cooperation. Especially thanks to my parents’ continuing

encouragement and spiritual support.

Contents

Abstract (in Chinese)……….……….……….………i

Abstract (in English) ………..……….……….………….…iii

Acknowledgement………...v

Contents……….……….………….……vi

Figure Captions……….. ….……….……….…...viii

Chapter 1 Introduction

1.1 High K Gate Dielectrics in La₂O₃

/

^Si_0.3^Ge_0.7 MOSFET………1

1.2 Cell Membranes in Biological Cells………..5

Chapter 2 Experimental

2.1 La₂O₃

/

^Si_0.3^Ge_0.7 p-MOSFETs ……….11

2.2 Process for Deep Trench Array Structure………12

Chapter 3 Results and discussion

3.1High K Gate Dielectrics in La₂O₃

/

^Si_0.3^Ge_0.7 p-MOSFET...16

3.2 Biological Cells……….19

Chapter 4 Conclusion.

...21

Figure.3.1----Figure.3.12

...23

References

...37

Figure Caption

Chapter1 Introduction

Fig.1.1

The SIA’s International Technology Roadmap for Semiconductor 2001

Table1

. Phaysical properties for various high-k materials

Fig.1.2

The principle of the cell membrane is integrity dependence on electric field

Fig.1.3

Cell membrane is similar to the gate dielectric in the MOSFET.

Chapter2 Experimental

Fig.2.1(a)

conventional technology for p-MOSFET scaling

Fig.2.1(b)

advanced technology for p-MOSFET scaling

Fig.2.2

cross-section for deep trench array structure and electric field.

Chapter3 Results and Discussion

Fig.3.1

XRD and electron diffraction patterns of Si0.3Ge0.7 after ion implantation and post annealing.

Fig.3.2

(a) Gate leakage current and (b) cumulative TDDB of La2O3 /Si and La2O3

/Si0.3Ge0.7 p-MOSFETs under positive gate bias.

Fig.3.3

C–V characteristics of La2O3 /Si and La2O3 / Si0.3Ge0.7 MOS capacitors.

Fig.3.4

ID –VD characteristics of La2O3/Si and La2O3/Si0.3Ge0.7 p-MOSFETs.

Fig.3.5

(a) ID –VD characteristics and (b) the hole mobility of La2O3/Si and La2O3

/ Si0.3Ge0.7 p-MOSFETs.

Fig.3.6

(a) The TEM picture of a human placenta cell, (b) the structure of a MOSFET, and (c) the TEM picture of the gate dielectric in the

MOSFET.

Fig.3.7

The picture of the fabricated 3-D cell traps on Si with electrical electrode patterns. The trench is for allocating and restraining the cells.

Fig.3.8

The current density flowing through the cells with the applied voltage.

Some cell membrane started to breakdown and broken at above 4 V. The

dummy cultivation liquid keeps very low conductivity over the whole

voltage range

Fig.3.9

The pictures of the human placenta TL cells before (a) and (b) after electric field applying, and stained by Typan Blue is applied to both case

but only stains the cells after applying voltage because of the leaks on the

cell membranes

Fig.3.10

The survival rate of the human placental TL cells with the applied

electric field. The survival rate reduces from ~100 % to < 4 % after 40

V/cm.

Fig.3.11

The survival rate of the human lung cancer cells with the applied electric field. The reduction trend with increasing electric field is similar to that

of the human placenta TL cells shown in Fig.3.9

Fig.3.12

The survival rate of the human lung cancer cells with the distance between the two opposite electrodes after applying a 0 ~ 20 V sweep

voltage. The rate is proportional to the distances, suggesting the electric

field is the key to breakdown the cell membranes.

Chapter 1 Introduction

1.1 High K Gate Dielectrics in La

2

O

3

/Si

0.3

Ge

0.7

MOSFET

CMOS technology is being continuously scaled towards tenth-micron and

smaller dimensions region due to the increasing need for higher speed, integration

density, as well as lower power consumption. Recently, with the advent of SiGe alloy

[1.1-1.2], it sheds a new light on the problem and appears to be a promising candidate

material for the next VLSI generation. SiGe has the advantage that it may be used to

modify conventional transistors to give higher speed and lower power. The SIA

roadmap show in Fig.1.l predicts that conventional CMOS transistors cannot operate

below gate lengths of order of 70nm while the use of SiGe in conventional FET

devices has been predicted to allow smaller dimensions. Coupled to this the ability to

produce quantum devices on the same chip gives SiGe substantial potential for future

circuits.

Silicon (Si) and germanium (Ge) have the same crystal structure. Thus, a layer

of one material can be placed on the other if consistent atomic order is maintained.

However, there is an approximately 4% greater natural spacing between atoms in

germanium crystal than atoms in a silicon crystal. If one is grown on the other, the

layer is strained when grown below the critical thickness. Above the critical thickness,

it takes too much energy to strain additional layers of material into coherence with the

substrate. As a result, defects appear causing misfit dislocations, which act to relieve

the strain in the epitaxial film. When epitaxial layer relaxes, the high defect density

significantly reduces the mobility of the material.

To reduce the strain from the mismatch of the lattice, researchers have

concentrated on building layers of silicon-germanium alloys with less than 30%

germanium. The growth of SiGe epitaxial layer have several approaches, including

Molecular-Bean Epitaxy(MBE)[1.3-1.4], Ultra-High Vacuum Chemical Vapor

Deposition (UHV-CVD) and Low-Pressure Chemical Vapor Deposition (LPCVD).

These approaches have some problems to form SiGe layer.

In this thesis, we have developed a new process technique for the formation of

epitaxial SiGe layer. Much different to previous work, SiGe in this new approach was

grown at high temperature and have good crystalline quality with uniform

composition as evidenced by TEM and SIMS analysis. In this new process, epitaxial

SiGe layer was formed by depositing an amorphous Ge layer and a subsequent

thermal cycle. We have found that the existence of native oxide before deposition

played an important role in the quality of epitaxial layer and HF-vapor passivation is

an effective way to suppress its growth. Since it was formed at high temperature, it

was supposed to be a relaxed layer that it do not suffer from the problem associated

with strain relaxation and shows great potential in device applications. We have also

successfully integrated this new technique into conventional CMOS process to

fabricate SiGe channel PMOSFET with ~60A gate oxide and shows superior

characteristics as compared to its Si counterpart. In addition, the new process is much

less expensive compared with CVD or other systems. More important, this technique

is easy and fully compatible with the current VLSI process.

In the scaling of CMOS, reducing the thickness of gate stack with lower leakage current plays an important role. Although the leakage current of the devices with the

same gate dielectric reduces with the scaling gate length and width, that leakage

current density increases with the scaling of gate dielectrics exponentially. Therefore,

the gate leakage current increases as the device size decreases. The larger leakage

current will not only cause the higher power consumption but also degrade the

reliability of the devices [1.5-1.6].

Using the material with high dielectric constant (high K), the physical thickness

of the dielectric in the devices can be increased without the reduction of capacitance

density. Since the leakage current is related to the physical thickness, the increasing

thickness of high K dielectric can reduce the leakage current of the devices. Although

high K dielectrics often exhibits smaller band gap, weaker bond, and higher defect

density than SiO2, the leakage high K dielectrics with the same effective oxide

thickness (EOT) with SiO2 still shows lower leakage current than SiO2 by few

orders[1.7-1.8]. That is the reason why high K dielectrics have drawn much attention

for future gate dielectrics.

Although oxynitride or Si3N4 has demonstrated lower leakage current than

direct-tunneling current limited SiO2 at the same equivalent-oxide-thickness (EOT),

unfortunately, Si3N4 can only be applied for one or two VLSI generation because of

relatively low dielectric constant (K). To continue the scaling trend of CMOS

technology, ultra-thin gate dielectrics beyond Si3N4 with high K and low leakage

current are urgently required. In addition to high K and low leakage current, the high

K gate dielectric must have good reliability, thermal stability, and process

compatibility with VLSI technology. Unfortunately, some high K dielectrics have

poor thermal stability as contact with Si and the effective EOT may be limited by the

reaction barrier Si3N4 or interface reaction region between gate dielectric and Si.

Therefore, the search for thermodynamically stable high K dielectric directly on Si is

important to meet future sub-10Å requirement. Furthermore, good hydrogenstability

and high amorphous to crystal transition temperature, are necessary to prevent

dielectric degradation by hydrogen and crystalline structure created defects or

dislocations during strain relaxation in subsequent process, respectively. Previously,

we have reported that amorphous Al2O3 directly on Si has higher K than Si3N4 , and

can meet near all the requirements and stable up to 1000^oC .

However, it is difficult to scale EOT below 10Å because K is still not high

enough. In this paper, we have successfully scaled EOT below 10Å using amorphous

La2O3 (K~27) that has close property as Al2O3. Besides higher K, La2O3 has even

better thermal stability on Si than Al2O3 as shown in Table 1. Therefore, very low

EOT of 4.8Å can be achieved that gives high transconductance and current drive in

MOSFETs using La2O3 gate dielectric. Small stress-induced leakage current (SILC)

and large charge-to-breakdown (QBD) comparable with SiO2 are also obtained that

demonstrates excellent reliability.

1.2 Cell Membranes in Biological Cells

The penetration of cell membrane is important for the cloning of Dolly sheep.

One role played by the electric field used in cloning is to cause recoverable transient

breakdown of cell membrane for both donor and recipient cells. However, there is

only little understanding of cell membrane integrity dependence on electric field as

shown in Fig.1.2 [1.9]. In addition, it is wondering if it is possible to control the

transient breakdown in multi- parallel, which is important for certain applications like

bio-computers. For these purposes, in this section we have integrated the human

placenta TL and lung cancer cell A549 into 3D trap arrays on Si substrate and studied

the electrically stimulated cell membrane breakdown phenomenon. The applied

electric field can break down the cell membrane and destroy the cell. We have also

measured the dependence of cell membrane breakdown distributions on electric field.

From measured data, the survival rate of cells under the electric field stress is similar

to the gate dielectric reliability of MOSFET as shown in Fig.1.3 [1.10].

Fig.1.1 The SIA’s International Technology Roadmap for

Semiconductor 2001

Table.1 Physical properties for various high-K materials.

SiO2 Al2O3 La2O3

Stability on Si (kJ/mole)

Si + MOx→ M+ SiO2 stable +63.4 +98.5

Lattice energy (kJ/mole) 13125 15916 12452

Structure amorphous amorphous amorphous

Fig.1.2 The principle of the cell membrane is integrity dependence on electric field

Applying Electric Field

↓

Permeabilization in biological membranes

↓

Cell Differentiation

Fig.1.3 Cell membrane is similar to the gate dielectric in the MOSFET.

Cell membrane

cytoplasm nucleus

gate dielectric

Chapter 2 Experimental

2.1 La

2

O

3

/Si

0.3

Ge

0.7

p-MOSFETs

Standard 4-in (100) n-type Si wafers with 1~ 2 Ω-cm resistivity (5e15~ 1e16

cm^-3 concentration) were used in this work. After device isolation and modified RCA

clean, the amorphous Ge layer was selectively deposited on the active region. An

HF-vapor passivation was used to suppress the native oxide formation before Ge

deposition [2.1-2.2]. After rapid thermal annealing (RTA) at 900 ⁰C, a 350 Å single

crystal SiGe was formed by solid-phase epitaxy in the active region, as confirmed by

X-ray diffraction, electron diffraction pattern, and cross-sectional transmission

electron microscopy(TEM) . The formed SiGe may be strain-relaxed, since it was

formed at high temperature. Then, the source-drain p⁺ region was formed by

implantation followed by a 950 ⁰C RTA. The La2O3 gate oxide of ~60 Å was formed

by depositing La and oxidation and measured by ellipsometer. More detailed SiGe

and La2O3 characterization can be found in our previous study [2.3-2.5]. Next, NH3

nitridation was performed at 550 ⁰C before gate electrode formation. The p-MOSFETs

and MOS capacitors were fabricated using Al as gate electrode and characterized by

I–V and C–V measurements. In addition to La2O3 /SiGe p-MOSFETs, La2O3 /Si

control devices were also fabricated as references. Fig2.1(a)(b) cross-section for

p-MOSFET and Fig2.2 La2O3 /SiGe p-MOSFETs process flow.

2.2 Process for Deep Trench Array Structure

KOH was used to etch the 4-in Si wafer to a designed deep trench array structure

after depositing 300 nm Si3N4 for masking. The average depth of the trench was 50

µm, which was deep enough for locating and fixing the cells. Then a 200 nm SiO2

was grown for electrically isolating the low-resistivity Si substrate. The electrode was

fabricated by depositing 2-µm thick aluminum layer and subsequent patterning. The

human placenta TL and lung cancer cell A549 were directly cultured on the fabricated

3D traps by immerging the Si chip into the culture medium. The cell membrane

breakdown was studied by applying voltage to the electrode pad of 3D traps. The

survival rate was calculated by counting the Trypan blue stained cells, since the cell

membrane was already broken under the applied electric field to allow the blue dye to

diffuse into the cells. Fig2.3 cross-section for deep trench array structure and Fig2.4

Biological Cell Chip Process Flow

Fig2.1(a) conventional technology for p-MOSFET Scaling

SiO ₂

Si Channel

Gate Length

Fig2.1(b) advanced technology for p-MOSFET Scaling

Gate Length

La ₂ O ₃

SiGe Channel

Fig2.2 La

₂

O

₃

/ Si

_0.3

Ge

_0.7

p-MOSFETs process flow

Grow Field oxide: 5000Å Si wafer preparation (clean wafer)

Pattern active region (mask1)

Doping source and drain

Field oxide above the channel stripping

Grow gate oxide(La₂O₃) 60 Å

Open contact hole (mask3)

5000Å Al deposited

Source, Drain, and Gate pads (mask4) Ge deposite then RTA at 900 ⁰C

Fig2.3 cross-section for deep trench array structure and electric field

Si

Al

V=1 volt V=0 volt

Electric Field

SiO

₂

Biologic cell

Fig2.4 Biological Cell Chip Process Flow

Si wafer preparation (clean wafer)

3000Å-thick Silicon dioxide

Lithography and SiO2 patterning(mask1)

Etching Si to 50mm deep

Removing SiO2

Silicon dioxide ( SiO2) growth 2000Å

Aluminum deposition

Aluminum patterning(mask2)

Chapter 3

Results and Discussion

3.1 La

2

O

3

/Si

0.3

Ge

0.7

p-MOSFETs:

Fig.3.1 shows the XRD and diffraction pattern of SiGe formed by solid phase

epitaxy. Single crystalline material quality and composition of Si0.3Ge0.7 are

confirmed. Fig.3.2(a) and (b) shows the – characteristics and cumulative

time-dependent dielectric breakdown (TDDB) of both La2O3/Si0.3Ge0.7 and La2O3/Si

p-MOSFETs, respectively. The almost identical gate current suggests the Si0.3Ge0.7

channel has little negative effect as compared with the Si case. The same gate current

was due to nearly the same work function of Si and SiGe and conduction band

difference between La2O3 and Si or SiGe. The comparable gate oxide integrity was

also evidenced from the nearly identical TDDB for La2O3 on Si or SiGe.

It has been further measured the quasi-static and high-frequency (100 KHz) C –

V characteristics of both La2O3 /Si and La2O3 / Si0.3Ge0.7 p-MOSFETs and the results

were shown in Fig.3.3. The identical accumulation capacitance and the same small 10

meV hysteresis measured for both devices indicate that the using SiGe does not have

any side effect. An EOT of ~16 Å was measured with a leakage current of 1.5 *10^-4

A/cm² at 1 V that is four orders of magnitude lower than SiO2 at the same EOT. The

smaller flat band voltage in La2O3/ Si0.3Ge0.7 devices may be due to the smaller energy

bandgap, which gives additional flexibility to tune VT .

Fig.3.4 shows the ID– VD characteristics of 4 µm La2O3 /Si and La2O3 /

Si0.3Ge0.7 p-MOSFETs plotted at the same VG – VT. Although a relatively large

junction leakage of 1* 10^-7 A/cm² is measured, it can be lowered to 1* 10^-8 A/cm²

using Ni gemeno- silicide, which was used in our previous study. In addition to the

good device I– V characteristics, the Si0.3Ge0.7 has ~2 times higher current driving

capability than the Si device at the same Vg of -2 V. Because the La2O3 was formed on

Si and Si0.3Ge0.7 on the same lot with identical inversion capacitance in Fig.3.3, the

higher hole current is not due to the different gate dielectric. The significantly higher

hole current was especially important for high-speed circuit application, which was

the fundamental motivation for continuously scaling down.

Because the improved hole current may came from both higher mobility and

threshold voltage (VT) difference, we have further measured the transfer ID–VG

characteristics. Fig.3.5(a) and (b) shows the ID– VG and hole effective mobility for

both La2O3/Si and La2O3 / Si0.3Ge0.7 p-MOSFETs, respectively, where the VT

difference was also included for the mobility extraction. In addition to having a higher

saturation hole current than La2O3 /Si devices, the La2O3 / Si0.3Ge0.7 p-MOSFETs

have the same off- state current (IOFF ) and lower VT. The lower in the La2O3 /

Si0.3Ge0.7 device was due to the smaller energy bandgap in Si0.3Ge0.7 . In addition to

the small VT difference of 0.2 V, the large hole current improvement was primary

coming from the higher mobility using Si0.3Ge0.7 . A peak hole mobility of 31 cm²

/V-s is obtained in the nitrided La2O3 /Si p-MOSFET that was comparable with

nitrided HfO2 /Si . In sharp contrast, the La2O3 / Si0.3Ge0.7 device has a higher hole

mobility of 55 cm² /V-s that was 1.8 times higher than the La2O3 /Si control devices

without using SiGe. In addition to the comparable gate oxide integrity and IOFF , the

higher mobility and ION indicate that the superior device performance can be realized

in nitrided high-k La2O3 p-MOSFETs using solid-phase epitaxy formed SiGe.

3.2 Biological Cells

Since the cell membrane was made of lipids and proteins with relatively poor

electrical conductivity as shown in Fig.3.6 it can be treated as a dielectric layer similar

to gate dielectric used in Si MOSFET. Fig.3.7 shows the fabricated 3D trap arrays and

metal lines on Si substrate for cell culture. Fig.3.8 is the current flowing through the

cells under applied voltage. The cell membrane behaves like an insulator layer when

the voltage is <3 V, since only small current was flowing through the cells and close

to dummy culture medium. However, the current density increased linearly with

increasing voltage >5 V, indicating that some cell membranes were broken to release

ions from cytoplasm and nucleus. At higher electric field, the cell membranes were

completely broken and the nucleus was exposed as confirmed by transmission electric

microscopy (TEM). The status of the cell membrane could be investigated by using

Trypan Blue stain, which stained the cell cytoplasm if there were leaks on the cell

membrane. Fig.3.9(a) and (b) show the comparison of human placenta TL cells before

and after applied voltage, where the dyes only stain the cells if the membrane was

damaged by electric field shown in Fig.3.9(b).

By counting the number of the stained cells (broken cell membrane) and

unstained cells, we analyzed the relationship between the applied electric field and the

after 20 sec electric stress. The survival rate started to decrease abruptly after

increasing electric field > 40 V/cm and reached <4 % at 80 V/cm. The measured

reducing survival rate trend of human placenta cells with increasing electric field was

consistent with those of human lung cell A549 shown in Fig.3.11 and Fig.3.12 shows

the survival rate vs. distance between two electrodes for human lung cancer cell A549

after applied 0 ~ 20 V linearly sweep voltage. The survival rate reached a higher value

of 97 % at the distance of 3000 µm but reduced to 74 % at 1000 µm, which suggested

that the electric field breaks down the cell membranes similar to gate dielectric in

MOSFET.

62 64 66 68 70

0 20 40 60 80 100 120

Si substrate

Si0.3Ge

0.7

2 θ (deg)

C o u n ts (A rb itr a ry U n it)

Fig.3.1 XRD and electron diffraction patterns of Si

0.3

Ge

0.7

after ion

implantation and post annealing.

0.0 0.5 1.0 1.5 2.0 2.5 3.0 10

^-7

10

^-6

1x10

^-5

1x10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

10

²

Accumulation

Lg=4µm & W

g=100µm pMOSFETs Si

SiGe

Ga te Cur re nt De nsi ty ( A /c m

2

)

Gate Voltage (V)

Fig.3.2(a) The gate leakage current of La

2

O

3

/Si and La

2

O

3

/Si

0.3

Ge

0.7

p-MOSFETs under positive gate bias.

Fig.3.2(b) The cumulative TDDB of La

2

O

3

/Si and La

2

O

3

/Si

0.3

Ge

0.7

p-MOSFETs under positive gate bias.

10

¹

10

²

10

³

10

⁴

20 0 20 40 60 80 100 120

solid: La₂O₃/Si_0.3Ge_0.7 pMOSFETs open: La₂O₃/Si pMOSFETs

3.0V 2.9V 2.8V

Time to Breakdown (sec)

C u m u lative F a ilure (% )

Fig.3.3 C–V characteristics of La

2

O

3

/Si and La

2

O

3

/ Si

0.3

Ge

0.7

MOS capacitors.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5

0.0 0.5 1.0 1.5 2.0

2.5 La₂O₃/Si at 100KHz La₂O₃/SiGe at 100KHz

La₂O₃/Si at quasi-static frequency La₂O₃/SiGe at quasi-static frequency

Gate Voltage (V)

Capaci tance (

µ

F/ cm

2

)

0.0 -0.5 -1.0 -1.5 -2.0 0

-1 -2 -3 -4

V

_G

-V

_T

= -1V V

_G

-V

_T

= -1.5V

V

G

-V

T

= -2V L

g

=4

µ

m & W

g

=100

µ

m solid : La

₂

O

₃

/Si pMOSFET open : La

₂

O

₃

/SiGe pMOSFET

Dr ai n Cur rent ( m A)

Drain Voltage (V)

Fig.3.4 I

D

–V

D

characteristics of La

2

O

3

/Si and La

2

O

3

/Si

0.3

Ge

0.7

p-MOSFETs.

0.0 -0.5 -1.0 -1.5 -2.0 10

^-7

10

^-6

1x10

^-5

1x10

^-4

10

^-3

10

^-2

Dra in Cur re nt ( A )

V_DS = -0.5V Si SiGe

Gate Voltage (V)

Fig.3.5 (a) I

D

–V

D

characteristics of La

2

O

3

/Si and La

2

O

3

/ Si

0.3

Ge

0.7

p-MOSFETs.

0.0 0.2 0.4 0.6 0.8 1.0 0

30 60 90 120 150 180

Universal hole Si mobility NH₃ annealed La₂O₃/SiGe NH₃ annealed La₂O₃/Si

E

eff

(MV/cm)

µ eff

(c m

2

/V -sec)

Fig.3.5 (b)The hole mobility of La

2

O

3

/Si and La

2

O

3

/ Si

0.3

Ge

0.7

p-MOSFETs.

Fig.3.6 (a) The TEM picture of a human placenta cell, (b) the structure of a MOSFET, and (c) the TEM picture of the gate dielectric in the MOSFET.

poly-Si oxide

20Å

Si

Gate dielectric

Fig.3.7 The picture of the fabricated 3-D cell traps on Si with

electrical electrode patterns. The trench is for allocating

and restraining the cells.

Fig.3.8 The current density flowing through the cells with the

applied voltage. Some cell membrane started to breakdown and broken at above 4 V. The dummy cultivation liquid keeps very low conductivity over the whole voltage range

0 5 10 15 20

0.0 1.0x10^-4 2.0x10^-4 3.0x10^-4 4.0x10^-4 5.0x10^-4

Current Density (A/µm2 )

Voltage (V) Cell

Cultivation Liquid

Fig.3.9 The pictures of the human placenta TL cells before (a) and (b) after electric field applying, and stained by Typan Blue is applied to both case but only stains the cells after

applying voltage because of the leaks on the cell membranes

Fig.3.10 The survival rate of the human placental TL cells with the applied electric field. The survival rate reduces from ~100

% to < 4 % after 40 V/cm.

0 20 40 60 80 100

0 20 40 60 80

100 20 sec.

Human Placenta Cell

Survival Rate (%)

Electric Field (V/cm)

Fig.3.11 The survival rate of the human lung cancer cells with the applied electric field. The reduction trend with increasing electric field is similar to that of the human placenta TL cells shown in Fig.3.9

0 5 10 15 20

90 92 94 96 98 100 102

Human Lung Cancer Cells 2 V 30 secs

Survival Rate(%)

Electric Field (V/cm)

Fig.3.12 The survival rate of the human lung cancer cells with the distance between the two opposite electrodes after

applying a 0 ~ 20 V sweep voltage. The rate is proportional to the distances, suggesting the electric field is the key to breakdown the cell membranes.

0 1000 2000 3000 4000

50 60 70 80 90 100

Human Lung Cancer Cell 0-20 V

Survival Rate (%)

Distance between electrodes (

µ

m)

Chapter 4

.

Conclusion

It has been fabricated high K La2O3 gate dielectrics using oxidizing the

deposited La similar to conventional thermal SiO2. Because of the low temperature

oxidation, dielectric integrity improves as decreasing La2O3 thickness. Owing to the

high hermodynamic stability on Si, thin 60Å La2O3 can be formed with a high K of 27

and a low EOT of 8.7Å. The high K is also confirmed from high current drive and

transconductance of MOSFETs with low off-state current. Because of the high lattice

energy close to SiO2, low SILC and high QBD are achieved and comparable with SiO2.

Good hydrogen annealing stability up to 550^oC is also obtained that is important for

process integration.

In addition to the almost identical gate oxide leakage current, capacitance density,

TDDB, and it had been achieved a ~2 times higher and high hole mobility of 55 cm²

/V-s in nitrided La₂O₃ /Si_0.3Ge0.7 p-MOSFETs. The improved hole mobility in the

La₂O₃ /Si_0.3Ge0.7 p-MOSFET gives another step to realize high- gate dielectrics for

VLSI integration.

The integration of cells into 3D trenched trap arrays in Si substrate and the

electrical control of the cell membranes integrity are important for future bio-medical

applications. We also have investigated into the feasibility of the biological cell, in

order to substitute for gate dielectric.

References

[1.1] K. Rim, J .Welser, J. L. Hoyt and J. F. Gibbons, "Enhanced hole mobilities in

surface-channel strained-Si p-MOSFETs," Electron Devices Meeting, pp.

517-520, 1995.

[1.2] K. Ismail, J. O. Chu and B. S. Meyerson, “High hole mobility in SiGe alloys

for device applications,” Appl. Phys. Lett. 64, 3124 ,1994.

[1.3] D. K. Nayak, J. C. S. Woo, J.S. Park, K. L. Wang, and K. P. Mac Williams,

“High-mobility p-channel metal-oxide-semiconductor field-effect transistor on

strained Si,” Appl. Phys. Lett. 62, pp. 2853, 1993.

[1.4] D. K. Nayak, J. C. S. Woo, G. K.Yabiku, K. P. Mac Williams, J.S. Park and K.

L. Wang, “High-mobility GeSi PMOS on SIMOX ,” IEEE Electron Devices

Lett. 14, pp. 520-522, 1993.

[1.5] W. Bin, J. S. Suehle, E. M. Vogel and J. B. Bernstein, “Time-dependent

breakdown of ultra-thin SiO2 gate dielectrics under pulsed biased stress,”

IEEE Electron Device Lett. 22, pp. 224-226, 2001.

[1.6] J. H. Stathis, A. Vayshenker, P. R. Varekamp, E. Y. Wu, C. Montrose, J.

McKenna, D. J. DiMaria, L. -K. Han, E. Cartier, R. A. Wachnik and B. P.

Linder, “Breakdown measurements of ultra-thin SiO2 at low voltage,” IEDM

Tech. Dig., pp. 94-95, 2000

[1.7] M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C.

Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorporated

ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” IEDM

Tech. Dig., pp. 20.3.1-20.3.4, 2001

[1.8] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A.

Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A.

Gribelyuk, H. Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N.

Bojarczuk, L. A. Ragnarsson and Rons, “Ultrathin high-K gate stacks for

advanced CMOS devices,” IEDM Tech. Dig., pp. 20.1.1-20.1.4, 2001

[1.9] J. A. Lundqvist, F. Sahlin, M. A. I. Åberg, A. Strömberg, P. S. Eriksson, and O.

Orwar, “Altering the biochemical state of individual cultured cells and

organelles with ultramicroelectrodes,” The National Academy of Sciences ,

vol.95, pp. 10356-10360 ,September 1998.

[1.10] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and Reliability

of High-K Al2O3 Gate Dielectric with Good Mobility and Low Dit,” Symp. on

VLSI Technology, p.133-134, Japan, June 1999.

[2.1] Y. H. Wu and A. Chin, “High-temperature formed SiGe p-MOSFETs

with good device characteristics,” IEEE Electron Device Lett., vol. 21,

pp. 350–352, July 2000.

[2.2] “Gate oxide integrity of thermal oxide grown on high temperature

formed Si Ge ,” IEEE Electron Device Lett., vol. 21, pp. 113–115,

Mar. 2000.

[2.3] Y. H. Wu, A. Chin, and W. J. Chen, “Thickness-dependent gate oxide

quality of thin thermal oxide grown on high-temperature formed SiGe,”

IEEE Electron Device Lett., vol. 21, pp. 289–291, June 2000.

[2.4] C. Y. Lin, W. J. Chen, C. H. Lai, A. Chin, and J. Liu, “Formation of

Ni germano-silicide on single crystalline Si Ge /Si,” IEEE Electron

Device Lett., vol. 23, no. 8, pp. 464–466, 2002.

[2.5] C. Salm, J. H. Klootwjik, Y. Ponomarev, P. W. M. Boos, D. J.Gravestejin,

and P. H. Woerlee, “Gate current and oxide reliability in poly MOS capacitors

with poly-Si and poly-Si Ge .” IEEE Electron Device Lett., vol. 19, pp.

213–215, July 1998.