The analytical potential model for asymmetrical tri-material double-gate (ASTMDG) and tri-material double-gate (STMDG) devices (i.e. Φi,asym(y,z) and Φi,sym(x,z), i=1,2,3) have been developed. By using the perimeter-weighted-sum method, that treats tri-material tri-gate (TMTG) device as separate devices operating in parallel, the analytical potential for the tri-material tri-gate (TMTG) MOSFETs can be obtained as the perimeter-weighted sum of the analytical potential for the asymmetrical tri-material double-gate (ASTMDG) device and symmetrical tri-material double-gate (STMDG) device. Accordingly, the analytical potential for the tri-material tri-gate device can be defined by
1,TMTG( , , )x y z 1,sym( , )x z αsym 1,asym( , ) (1y z αsym) under M1
Φ = Φ × + Φ × − (3.3.1)
2,TMTG( , , )x y z 2,sym( , )x z αsym 2,asym( , ) (1y z αsym) under M2
Φ = Φ × + Φ × − (3.3.2)
3,TMTG( , , )x y z 3,sym( , )x z αsym 3,asym( , ) (1y z αsym) under M3
Φ = Φ × + Φ × − (3.3.3)
with
= 2 2
si sym
si
t
W t
α + (3.3.4)
whereΦ1,TMTG( , , )x y z ,Φ2,TMTG( , , )x y z andΦ3,TMTG( , , )x y z are the analytical potential in region 1, 2 and 3 for tri-material tri-gate (TMTG) device,Φ1,sym( , )x z ,Φ2,sym( , )x z and
3,sym( , )x z
Φ are the analytical potential in region 1, 2 and 3 given by eq.(3.2.58)-eq.(3.2.60) for symmetrical tri-material double-gate (STMDG) device,
1,asym( , )y z
Φ ,Φ2,asym( , )y z and Φ3,asym( , )y z are the analytical potential in region 1, 2 and 3 given by eq.(3.1.62)-eq.(3.1.64) for asymmetrical tri-material double-gate (ASTMDG) device, respectively, and αsym is the ratio of symmetrical tri-material double-gat (STMDG) MOSFETs to the entire tri-material tri-gate (TMTG) MOSFETs, which can be 1 (if w<<tsi) for pure STMDG MOSFETs device and can be 0 (if w>>tsi) for genuine ASTMDG MOSFET. For TMTG MOSFETs device, 0<αsym<1.
In the tri-material tri-gate (TMTG) MOSFETs, material workfunctions will be selected in such a way that workfunction of the material near the source is highest and that near the drain is lowest for p-channel MOSFET. To verify the analytical body potential model, Fig. 3.3.3 shows the 3-D potential distribution with cut plane along y-z direction from the device simulator DESSIS of ISE TCAD for tri-material tri-gate (TMTG) device of Vgs=0V and and L1:L2:L3=1:1:1. Fig. 3.3.4 shows the 3-D potential distribution with cut plane along y-z direction from the model results for tri-material tri-gate (TMTG) device of Vgs=0V and and L1:L2:L3=1:1:1. Fig. 3.3.5 shows the 3-D potential distribution with cut plane along x-z direction from the device simulator DESSIS of ISE TCAD for tri-material tri-gate (TMTG) device of Vgs=0V and and L1:L2:L3=1:1:1. Fig. 3.3.6 shows the 3-D potential distribution with cut plane along x-z direction from the model results for tri-material tri-gate (TMTG) device of Vgs=0V and and L1:L2:L3=1:1:1. It is obviously seen that a close agreement for the 3-D potential distribution between the device simulator and analytical model are obtained.
Due to the fact that the most leaky path will be in the middle of the channel width along the bottom plane for the 3-D tri-material tri-gate device (i.e. (x=W/2, y=tsi, z), the 3-D potential of (x=W/2, y=tsi, z) can be equivalently decomposed of 2-D central potential of (x=W/2, z) for symmetrical tri-material double-gate (STMDG) device and 2-D bottom potential of (y=tsi, z) for asymmetrical tri-material double-gate (ASTMDG) device. Fig. 3.3.7 shows the variation of the bottom potential Ф(x=W/2,y= tsi,z) with the normalized channel length position z/Lg for the different gate ratios of L1, L2 and L3. A good agreement between the results calculated from our model with those simulated using the device simulator is obtained. The plot reveals that the minimum bottom potential barrier between the source side and the minimum channel position of zmin can be increased for the large ratio of L1 to L2 and L3 such as 2:1:1, which therefore enhances the immunity to SCE and effectively represses DIBL for the device. It is also evident that there are two step-changes of potential along the channel at the interface of M1, M2 and M2, M3. The small difference of voltage due to different gate material keeps uniform electric field along the channel, which in turn improves the carrier transport efficiencythat allows us to utilize the benefits of ballistic and overshoot transport in the MOSFETs. The ratio of three metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. Another important factor associated with the single-material tri-gate (SMTG) structure is the
DIBL. Hence, the single-material tri-gate (SMTG) MOSFETs are also included for comparison. It is shown that the slope of bottom potential to the drain side for tri-material tri-gate (TMTG) MOSFETs is much smaller than that for single-material tri-gate (SMTG) MOSFETs. It implies that in comparison to single-material tri-gate (SMTG) MOSFETs, the tri-material tri-gate (TMTG) MOSFETs can effectively reduce the electric field near the drain side and exhibits the strong immunity to SCE induced by the increased drain voltage. Fig. 3.3.8 depicts the dependence of the bottom potential on the normalized channel length with the gate oxide thickness as a parameter. It is obvious that the thin gate oxide provides the better gate control capability than thick gate oxide for lowering the minimum surface potential. However, insulator thickness cannot be scaled down to very small values otherwise tunneling through the thin insulator and hot-carrier effects become prominent. Besides, it is interesting to note that for tri-material gate (TMG) MOSFETs the offset voltage increases as the oxide thickness decreases. As the offset voltage increases so is the screening of region under M1 from drain voltage variation and therefore, more reduction in DIBL. (The gate of material 3 is known as the screen gate and the gate of material 1 is known as the control gate, respectively.). Fig. 3.3.9 shows the simulated bottom potential profile for a channel length of Lg=120 nm with different drain biases. The simulated data of single-material tri-gate (SMTG) MOSFETs are also included for comparison. It is shown that the slope of bottom potential to the drain side for the tri-material tri-gate (TMTG) MOSFETs is much smaller than that for the SMTG MOSFETs. It implies that in comparison to SMTG MOSFETs, the TMTG MOSFETs can effectively reduce the electric field near the drain side and exhibits the strong immunity to the SCEs induced by the increased drain voltage.
Fig. 3.3.3 The 3-D potential distribution with cut plane along y-z direction from the device simulator DESSIS of ISE-TCAD for tri-material tri-gate (TMTG) device of Vgs=0V and L1:L2:L3=1:1:1.
Fig. 3.3.4 The 3-D potential distribution with cut plane along y-z direction from the model results for tri-material tri-gate (TMTG) device of Vgs=0V and L1:L2:L3=1:1:1.
Fig. 3.3.5 The 3-D potential distribution with cut plane along x-z direction from the device simulator DESSIS of ISE-TCAD for tri-material tri-gate (TMTG) device of Vgs=0V and L1:L2:L3=1:1:1.
Fig. 3.3.6 The 3-D potential distribution with cut plane along x-z direction from the model results for tri-material tri-gate (TMTG) device of Vgs=0V and L1:L2:L3=1:1:1.
0 0.2 0.4 0.6 0.8 1 Normalized Channel Position , (z/L
g)
0
Fig. 3.3.7 The dependence of bottom potential on the normalized channel length with different ratios of gate material regions for tri-material tri-gate MOSFET and the single-material tri-gate (SMTG) MOSFETs are also included for comparison.
0 0.2 0.4 0.6 0.8 1
Normalized Channel Position , (z/L
g) 0.2
Fig. 3.3.8 The bottom potential versus the normalized channel position (z/Lg) with the different gate oxide thicknesses for the tri-material tri-gate (TMTG) MOSFET.