Electric Field

From eq.(3.1.62), eq.(3.1.63) and eq.(3.1.64), the electric field can be derived by the partial derivative of Φ1(y,z), Φ2(y,z) and Φ3(y,z) with respect to z. The electric field of the silicon body under material 1-3 for the TMG MOSFETs can be expressed as

( ) ^{( ) ( )}

In tri-material gate (TMG) MOSFETs structure, the arrangement is such that the work function of the gate metal near the source is higher than others near the drain. Fig.

3.1.8 shows the variation of the electric field with the normalized channel position for ratio of L1:L2:L3=1:1:1. It indicates that the TMG structure induces the peak electric fields at the interface between the different gate materials within the channel. This peak causes more uniformity of the electric field in the channel resulting in higher carrier drift velocity and device speed. It is seen that there are two peaks in the TMG MOSFETs, which ensures better average electric field across the channel as compared to a single peak in the SMG [38] case, and therefore, better carrier transport velocity is achieved. Moreover, the peak electric field at the drain for TMG-MOSFET is lower than that in SMG-MOSFET as shown in Fig. 3.1.8. This reduction in electric field experienced by the carriers in the channel can be interpreted as reduction of the hot-carrier effect at the drain end.

0 0.2 0.4 0.6 0.8 1 Normalized Channel Position , (z/L

)

0 4 8 12

Electric Field , E ( |E |¥ 10

V/c

m )

Symbol : Model Line : DESSIS F_M1 = 4.77 eV F_M2 = 4.40 eV F_M3 = 4.17 eV t_ox = 3 nm

t_si = 10 nm t_box = 100 nm L_g = 120 nm V_gs = 0.0 V V_ds = 0.05 V V_sub = 0.0 V N_a = 1â10¹⁷ cm^-2 N_d = 1â10²⁰cm^-2

. : L1 : L₂ : L₃ = 1 : 1 : 1 , : SMG

Fig. 3.1.8 The variation of the electric field with the normalized channel position for ratio of L1:L2:L3=1:1:1, and the single-material gate (SMG) MOSFETs are also included for comparison.

3.1.9 Threshold Voltage Roll-off Model

As mentioned in chapter 2.1, the most popular Vth definition used in compact modeling is the gate voltage φB at which the band bending reaches at the silicon surface, where φB is the difference between the Fermi level and intrinsic level of silicon in the neutral region. Under this condition, the inversion carrier density at the silicon surface equals the density of the doping atoms in the silicon bulk Na. This definition has been physically reasonable and successful in identifying the turn-on condition for bulk devices, where Na -values are in the range of 1×10¹⁷cm^-3.

In order to solve analytical threshold voltage, we need to rewrite coefficients as a linear equation related to Vgs. From eq.(3.1.25), eq.(3.1.26) and eq.(3.1.49-3.1.56), we get

( )

By using eq.(3.1.70)-eq.(3.1.83), the minimum potential as a linear equation related to gate bias (i.e. Vgs) of the silicon body for material 1-3 can be expressed as

( )( ) ^{( )}

Using eq.(3.1.99)-eq.(3.1.101) and Фmin=2φB, respectively, we can get three quadratic equations in region 1-3 as

2

From eq.(3.1.109)-eq.(3.1.115), Фmin=2φB, and solving for Vgs, the threshold voltage can be achieved as

2

In tri-material single-gate MOSFETs, the work function of the gate metal near the source is higher than the others near the drain that cause the minimum potential will occur in region 1. From eq.(3.1.99), Ф1min=2φB, and solving for Vgs, the threshold voltage can be achieved. However, the form of the threshold voltage is too complicated to be used in analyzing the subthreshold characteristics. To obtain the simple and feasible analytical threshold voltage model, the condition of kn >>1 is assumed.

Therefore, the threshold voltage for the single-gate MOSFETs is obtained as

, , , the threshold voltage roll-off caused by the short-channel effects. By eq.(3.1.119) and eq.(3.1.121), the numerical form is obtained as follows

( )

Fig. 3.1.9 shows the dependence of threshold voltage roll-off (ΔVth,s) on the channel length (L) with a variation in metal gate M1 to the total gates of M1, M2 and M3. It is shown that the high ratio of M1 to the total gate that alleviates SCEs can maintain the low threshold voltage degradation. Unquestionably, the gate 1 is the major control gate in this device, which is known as “control gate”. However, the high workfunction of the gate material will induce a large threshold voltage and decrease the turn-on current for the analog circuits, which may plague the switching speed. As for the large workfunction of the gate material that is used for the tri material gate (TMG) MOSFET, the trade-off between the circuit stability regarding threshold voltage degradation and the driving capability with respect to the decreased turn-on current should be considered concurrently. Fig. 3.1.10 shows the dependence of threshold voltage roll-off (ΔVth,s) versus the channel length (L) for various gate oxide thickness as a varied parameter and the data are compared with the 2D numerical simulation results. The threshold voltage roll-off predicted by the analytical solution is in good agreement with those from numerical simulation. The plot indicates that the threshold voltage roll-off increase rapidly when the channel length decreases, particularly when the gate oxide thickness is increase to 5 nm. This implies that the gate gradually loses control of the channel as the gate oxide steadily increases its thickness, which prevents the vertical electric field from passing through the channel, which brings about severe DIBL. However, for a long channel device of 100<L<180nm, the threshold voltage roll-off will diminish andthe long-channel device behavior for all the cases of oxide thickness is maintained as shown in Fig. 3.1.10. Both thin gate oxide and the thin silicon are preferred to alleviate the threshold voltage roll-off. To improve the degradation of the threshold voltage that is to make the silicon film thickness much thinner as shown in Fig. 3.1.11. It is revealed that as the silicon film thickness is decreased, the threshold voltage roll-off will increase accordingly. The more thin silicon film will result in the less threshold degradation. It suggests that the thin film is preferred to suppress the short channel effects as the designing device pushed into sub-micrometer regime, particularly for the silicon film thickness down to 5 nm.Fig. 3.1.12 shows the threshold voltage roll-off (ΔVth,s) versus the channel length (L) for the TMG MOSFETs with various drain biases. It is revealed that the threshold voltage roll-off for Vds=4.0V is several times higher than that for Vds=0.05V due to the severe DIBL induced by a large drain bias.

30 60 90 120 150 180

Fig. 3.1.9 The threshold voltage roll-off ΔVth,s versus the channel length L with the different ratios of L1:L2:L3.

Fig. 3.1.10 The threshold voltage roll-off ΔVth,s versus the channel length L with the different gate oxide thicknesses.