From eq.(3.2.27)-eq.(3.2.29) and eq.(3.2.36)-eq.(3.2.38), the potential of the silicon body under material 1-3 for the tri-material double-gate MOSFETs can be expressed as
( ) ( )
Material workfunctions will be selected in such a way that workfunction of the material near the source is highest and that near the drain is lowest for p-channel MOSFET. To verify the analytical body potential model, Fig. 3.2.2 and Fig. 3.2.3 show the 3-D potential distribution from the device simulator DESSIS of ISE-TCAD and model results with the same device structure at x=0 and Vds= 0.05V for L1 equal to L2
and L3. It is obviously seen that a close agreement for the 3-D potential distribution between the device simulator and analytical model are obtained.The model predicts two step-functions in the potential along the channel, which ensures screening of drain potential variation by the gate near the drain.
Fig. 3.2.4 shows the variation in surface potential with the normalized channel position for different ratios of gate lengths L1, L2 and L3 of M1, M2 and M3, respectively, maintaining the sum of the total gate length, i.e., (Lg=L1+L2+L3) to be constant. It is observed that as the length of gate M1 is reduced, the position of the minimum surface potential, lying under M1 is shifted toward the source and that the minimum channel potential is increased, which causes intense DIBL. This implies that as L1 increases, a portion of the channel controlled by the gate metal with a larger work function is increased and the SCEs are suppressed substantially. It is also clearly seen that the TMDG structure exhibits two step functions in the surface potential along the channel.
The small difference of voltage due to different gate material keeps uniform electric
field along the channel, which in turn improves the carrier transport efficiency that allows us to utilize the benefits of ballistic and overshoot transport in the MOSFETs.
Due to the feature, the area under M1 of the TMDG structure is essentially screened from the drain-potential variations. This means that the drain potential has very little effect on the drain current after saturation reducing the drain conductance and DIBL.
The predicted values of the eq.(3.2.58), eq.(3.2.59) and eq.(3.2.60) agree well with the simulation results. In addition, Both our model and simulation results of the single-material double-gate (SMDG) structure is included and compared with the model.
From the plots, the SMG MOSFET demonstrates a unique peak field (the slope of the potential with respect to the channel length) almost near the drain side and brings about hot carrier effects (HCEs) that cause tremendous drain current when the device enters into saturation. On the contrary, the TMDG MOSFET exhibits a third peak electric field at the interface of M2 and M3 (i.e., the potential step at the interface between M2 and M3
will result in the third electric field) aside from inducing the second peak field near the drain side, which causes a much more uniform field than in the SMG MOSFET along the entire channel and reduces the HCEs.
Fig. 3.2.5 depicts the dependence of the surface potential on the normalized channel length with the gate oxide thickness as a parameter. It is obvious that the thin gate oxide provides the better gate control capability than thick gate oxide for lowering the minimum surface potential. However, insulator thickness cannot be scaled down to very small values otherwise tunneling through the thin insulator and hot-carrier effects become prominent. Besides, it is interesting to note that for tri-material gate (TMG) MOSFETs the offset voltage increases as the oxide thickness decreases. As the offset voltage increases so is the screening of region under M1 from drain voltage variation and therefore, more reduction in DIBL. (The gate of material 3 is known as the screen gate and the gate of material 1 is known as the control gate, respectively.).
Fig. 3.2.2 The 3-D potential distribution from the device simulator of DESSIS for tri-material double-gate device of Vgs=0V and L1:L2:L3=1:1:1.
Fig. 3.2.3 The 3-D potential distribution from the model results for tri-material double-gate device of Vgs=0V and L1:L2:L3=1:1:1.
0 0.2 0.4 0.6 0.8 1 Normalized Channel Position , (z/L
g)
0
Fig. 3.2.4 The dependence of surface potential on the normalized channel length with different ratios of gate material regions, and the single-material double-gate (SMDG) MOSFETs are also included for comparison.
0 0.2 0.4 0.6 0.8 1
Normalized Channel Position , (z/L
g) 0.2
Fig. 3.2.5 The surface potential versus the normalized channel position with the different gate oxide thicknesses.
3.2.7 Minimum Channel Potential
In the tri-material double-gate (TMDG) MOSFETs, the subthreshold leakage current mainly occurs at the position of the minimum potential along the channel.
According to TMG MOSFETs, the arrangement is such that the work function of the gate metal near the source is higher than others near the drain that causes the minimum potential will occur under M1. Therefore, the subthreshold behavior can be monitored by the minimum channel potential in region 1. From eq.(3.2.58), the minimum potential can be derived by setting 1( , )
x z 0 z
∂Φ =
∂ . Accordingly, the position of the minimum channel potential in the region 1 (i.e. z1min) can be found by
1 As z1min is solved, the minimum channel potential in the region 1 (i.e. Ф1min) for the tri-material double-gate MOSFETs can be obtained as
( )
Fig. 3.2.6 shows that the minimum channel potential on the gate bias is increased as the channel length decreased. Thus, the subthreshold leakage current is stronger for short channel length, and it leads to threshold voltage roll-off. Besides, the drain-induced barrier lowering effect (DIBL) increases for the shorter channel length.
As the potential barrier is reduced by the short channel length, the channel is easily to conduct as the thermal voltage mounts above the barrier height. Fig. 3.2.7 shows the dependence of the minimum surface potential Ф1min on the gate bias with the ratio of L1:L2:L3 as a parameter. It is revealed that a larger ratio L1:L2:L3 (i.e. L1:L2:L3=2:1:1) efficiently decreases the value of Ф1min, which raises the potential barrier between the source end and position zmin and enhances the resistance of the device to SCE. Although a larger ratio of the control gate to the screen gate can effectively reduce SCE, it will also increase the threshold voltage simultaneously and set a hard limit to low-voltage and low-power VLSI application.
-0.2 -0.1 0 0.1 0.2
Minimum Potential , F
1min(V)
tox = 3 nm
Fig. 3.2.6 Variation of minimum surface potential Φ1minwith gate bias Vgs for different channel lengths.
Mini mum Pot ential , F
1min(V)
tox = 3 nm
Fig. 3.2.7 Variation of minimum surface potential Φ1minwith gate bias Vgs for different ratios of L1:L2:L3.