For decades, progress in device scaling has followed an exponential curve, with the device density on a microprocessor doubling every three years. This has come to be known as Moore's law [1]. In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator (SOI) MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-gate, tri-gate or quadruple-gate devices). These devices offer a higher current drive per unit silicon area than conventional MOSFETs. In addition, they offer optimal short-channel effects (reduced DIBL and subthreshold slope degradation). As CMOS devices have been scaled down, the channel length shrinks and the absolute value of threshold voltage becomes smaller due to the reduced controllability of the gate over depletion region by the increased charge-sharing from the source/drain. Fig. 1.1 shows the SOI MOSFETs ‘‘family tree’’ [2]. The first publication describing a double-gate SOI MOSFET dates back to 1984. The Tri-Gate or FinFET is the recent solutions for controlling SCEs and improving the subthreshold swing as well as packing densities. A group of leading companies publishes their projections for the next decade in the most recent International Technology Roadmap for Semiconductors (ITRS) [4], This roadmap projects a device gate-length of about 20nm for the year 2014. Scaling beyond ~20 nm, however, can be much more difficult. This is because we are close to the fundamental limits of semiconductor physics. The most important issue to be addressed is how much further can aggressive device scaling be continued.Multi-gate field-effect transistors (MuGFETs) such as Tri-Gate, FinFETs, have a strong potential for sub 32 nm technologies, which is in agreement with the ITRS roadmap.
Fig. 1.1 SOI MOSFET family tree [2].
A numerous of literatures have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade. So far, very little work has been done on the analytical modeling of Tri-Gate (TG) MOSFETs including the localized interface trapped charges, although there have been some works studying the TG device performance through numerical simulation [5], or studying the device physics from experimental data [6]. To overcome limitations and realize high-performance MOS transistors, by considering effects of equivalent oxide charges on the flat-band voltage, effective conducting path, and poisson equation, a concise analytical subthreshold behavior model for TG MOSFETs with the interface trapped charges including threshold voltage, subthreshold slope, and subthreshold current are needed.
Besides these new structures of TG or FinFET, we renew the top gate structure.
The top and two side gate of the TG MOSFETs consists of two/three laterally contacting materials with different work-functions. This dual/tri Material gate structure takes advantage of material work-function difference leads that the threshold voltage near the source is larger than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to overcome short-channel effects [3]. Hence, Dual-Material Gate/Tri-Material Gate MOSFETs promise simultaneous suppression of SCEs, enhancement of average carrier velocity in the channel, and alleviation of reduced threshold problems using gate material engineering.
1.2 Tri-Gate Device Overview
The Schematic of TG MOSFETs is shown in Fig. 1.2. The devices consist of a top and two side gates on an insulating layer. To avoid solving for 3-D Poisson equation that is too complicated to be derived, the 3-D TG device can be replaced with the 2-D equivalent asymmetric and symmetric double-gate structures by ignoring the coupling effects for assuming that channel length/channel width and channel length/channel thickness is larger than 2 which fall within the restrictions required to obtain realistic and operational TG devices [7].
Vgs
Fig. 1.2 Schematic of Tri-Gate MOSFETs: (a) three-dimensional device structure, (b) with cut plane along A-A’ (c) with cut plane along B-B’. The device can be equivalently composed of two-dimensional symmetrical double-gate (SDG) MOSFET with width of W as shown in (b) and asymmetrical double-gate (ASDG) MOSFET with width of tsi as shown in (c).
A transition from bulk to multiple-gate fully depleted (FD) silicon-on-insulator MOSFETs offers higher current drive per unit silicon area and better short-channel immunity. The TG device improves on the planar devices which reduce drain-source current leakage, and the control of the gates on the channel in a TG MOSFET is stronger than that in a conventional MOSFET as the gate voltage is applied from several sides and not just from the top. In recent years, TG MOSFETs have received more attention than the planar MOSFETs in the high speed or high frequency applications.
Comparing TG device to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. TG MOSFETs will be more promising for the future VLSI circuits.
Therefore, exploitation and use of TG MOSFETs in memory circuits [7] require the physics-based transistor model [8-11]. The findings of the model are much useful to investigate hot-carrier-induced threshold voltage and offer the basic guidance for the design of memory device. Furthermore, three-dimensional (3-D) simulations of TG transistors with gate lengths down to 30 nm show that the 30 nm TG device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the TG transistor could pose a viable alternative to bulk transistors in the near future [12].