respectively. The related expressions are given in Table 3 for details. It should be noted that the above equations are exact in the sense that any arbitrary doping profile in the Si film can be treated.
In the following analysis, the uniformly doped Si film is assumed for simplicity. Therefore, the 2–D potential distribution at the zone II can be further repressed as follows [30]:
( ) ( ) [ ( ) ]
(2–5)
2–2.2
Since the F
the front surface potential distribution of the Si film is usually used to monitor the turn–on status of FD–SOI MOSFETs. From equation (2–5), the potential distribution along the front surface of the Si film can be derived as:
The accuracy of the derived front surface potential distribu
the 2–D numerical analysis as shown in [30]. In the paper by Guo [30], to develop an analytical threshold voltage model, the minimum potential along the front surface of the Si film has to be calculated first. By differentiating the equation (2–6), the position of the minimum potential along the front surface of the Si film can be calculated.
(2–7)
distribution along the front surface of the Si film. By introducing the value of xmin into equation (2–6), the minimum surface potential
φ
sfII,min can be obtained. However, the position of the minimum surface potential xmin can be only solved iteratively and no explicit form of xmin can be obtained. Therefore, the calcu inimum front surface potential is too comp to be further implemented in the derivations of the analytical I–V model for a circuit simulator like SPICE.The new ap
lation of the m
proach for the develop ent of the threshold voltage model is described in the following. Firstly
2–11)
ne a
licated
m
, by differentiating equation (2–3) with respect to y, the normal electric field along the front Si film surface can be obtained and expressed as:
(2–8)
Then, by integrating equation (2–8) with respect to x from x = 0 to x = L, the total charge density controlled by the front gate can be obtained and expressed as:
(2–9)
( ) [ ( )
1]
.By applying Gauss’s law at the front SiO2–Si interface, we obtain
(2–10)
From equation (2–10), the threshold voltage can be obtained as:
( )
fficient due to the calculation of xmin. Therefore, in this work, the averageom computationally ine
normal electric field along the front surface of the Si film E is used to substitute the sf Esf
( )
xmin . From equation (2–9), E can be obtained and expressed as: sf
(2–13)
or a aver
OI MOS
te can
(2–14) bi
(2–12)
[
1( )
1]
.∑
Then, the threshold voltage can be redefined as:
Due to the effect of the lateral electric field igin ting from the source/drain junctions, the age normal electric filed along the front surface of the Si film is expected to be smaller than the normal electric filed at the position of minimum potential. Therefore, in order to compensate the error results from the charge–sharing effect, a modification to the equation (2–13) is necessary.
Figure 2–2 shows the normal electric field along the front SiO2–Si interface of the FD S FETs, where the case of the average surface normal electric field is shown in (a) and the case of the surface normal electric field accounting for the charge–sharing effect is shown in (b). In Figure 2–2(a), the total depletion charges Qdepl,1 in the Si film that terminate the average surface normal electric field originating from the ga be expressed as:
The charge–sharing effect is due to the loss of the control a lity of the gate to the depletion charge under it. In other words, the depletion charge controlled by the gate is no longer equal to Qdepl,bulk
(Q =qN y , for bulk MOSFETs, where y is the maximum depletion width of the depletion region under the gate), but to a fraction of it. The reduction of the depletion charge is due to the presences of the source/drain junctions and the surface normal electric field is disturbed by the lateral electric field originating from the source/drain junctions, as shown in Figure 2–2(b).
According to the charge–sharing scheme shown in Figure 2–2(b), the effective depletion charge controlled by the gate can be obtained as:
max
,bulk B d
depl dmax
1
∞
=
m
ε
sikmL − −= m
m sf sf
E D
, .
fox sf si inv f f FB
TH C
V E
V
ε
φ
++
=
1 .
, si sf si
depl E W L t
Q =
ε
⋅ ⋅ ⋅(2–15)
here and drain–substrate junctions at the
.
quating equations (2–14) and (2–15), the relationship between and
w are the depletion widths of the source– and surface
By e Qfg E can be sf
obta
(2–16)
herefore, in order to com ge–sharing effect, we add the
ined as
where
T pensate the errors caused by the char
modified factor
β
into equation (2–13) and obtain the final expression of the analytical threshold voltage model:(2–17)
of th
After some mathematical manipulations, the equation (2–17) can be further expressed in terms e terminal voltage as:
β
.(2–18) where the coefficients G , m F , bm F and dm Fgm are listed in Table 4 for details and
γ
is an empirical constant assum t cc t for t errors resulting from the drain–induced barrier lowering effect.ed o a oun he
–3 Verifications and Discussion
In order to verify the accuracy of the derived equations, the analytical model of the , given in t
(2–19)
2
VTH
he equation (2–18), has been compared with the results obtained by the 2–D numerical device simulator Medici [32] and experimental data [33]. The threshold voltages of the results obtained by the 2–D numerical simulator are defined by the relationship between the drain current and external gate–source voltage as follows. In general, the drain current in the non–saturation region can be expressed as
For the long channel length devices operating at low VDS (e.g., VDS =50mV), using the extrapolation method on the I –DS V curve at GS V equal to the voltage at which the maximum GS
GS
DS dV
dI occurs, the threshold voltage can be obtained by the intercept on the V –axis. GS
(2–20) 2 .
1
DS DS TH
GS eff
eff fox eff
DS V V V V
L C
I W ⎟⋅
⎠
⎜ ⎞
⎝
⎛ − −
=
µ
1 .
int
, ercept DS
GS
TH V V
V
= −
Additionally, when VGS =VTH, the normali ed drain curr t is defined as a reference current. z en
–21)
s
n curre ice. When axim
(2
2
longL DS eff normalized DS
reference L I
I
I = , = ,
where Ireference is the reference current, IDS i the normalized drain current and IDS,longL is Weff
normalized ,
the drai nt of the long channel dev the channel length is very short, the m um transconductance extrapolation method would fail due to the significant short channel effect. Thus, the threshold voltage of the short channel device is extracted by equating the normalized drain current to the reference current, which is determined by the long channel device. For high VDS
operation, VTH is extracted from the parallel shift of ln
( )
IDS versus VGS in the subthreshold region, as mentioned in [33].The comparisons of the threshold voltage versu fective channel length of the fully depleted SOI
s ef
MOSFET’s with
11
nm front gate oxide,330
nm buried oxide and 1×1017cm bulk −3 doping concentration for different Si film thicknesses are shown in Figure 2–3 when VDS =0.05V and VBS =0V . In this figure, it is expected to see that the roll–off of the threshold voltage is severer in the Si film due to the short channel effect. In other words, the VTH roll–off starts to occur at larger gate lengths in the MOS transistors with thicker Si film thickne lly, it is clearly seen that the calculated results using the present model agree very well with the 2–D numerical analysis.Figure 2–4 shows the comp case of thicker
sses. Additiona
arisons of the threshold voltage versus effective channel length for the devices of
eter. From this figure, it is seen that the devices with thinner front gate oxides can significantly retard the roll–off of the as the channel length
can be seen, the present model corre
nm
70
Si film,330
nm buried oxide and bulk dopinggetting shorter. This is because that with thinner front gate oxide, the ability of control of the gate to the depletion region under it becomes better. It is also seen that a good agreement is obtained between the simulated results and 2–D numerical analysis.
Figures 2–5 and 2–6 compare the roll–off of the threshold voltages for different back gate voltages with 2–D numerical analysis and experimental data. As
3
1017
1× cm− concentration with front gate oxide as the param
VTH
ctly predicts the V roll–off for different back gate biases. Figure 2–7 shows the effect of the drain voltage on the roll–off of the threshold voltage of the devices with
1 . 6
nm front gate oxide,nm
400
buried oxide,21
nm Si film and 1.5×1018cm bulk doping concentration. It is −3 expected to see that at larger drain bias, the encroachment field from es moret, especially at s annel length. F re, the accurate predictions of the severe threshold voltage roll–off by the proposed model are obtained, even for the devices with
m
TH
the drain becom
significan mall ch rom this figu
µ
07 .
0
channel length. Figure 2–8 shows the comparisons of the threshold voltages obtained bythe present model with the experimental data for the devices biased at different drain voltages. In e, it is seen that a good agreement is obtained between the simulated results and the experimental data. Eventually, the present model is compared with the numerical data used in [30]
(Figs. 5–7) and the compared results are shown in Figure 2–9. From the figure, it is seen that a good agreement is obtained and evaluates the validity of the modified model.