( )
00
µ
β
⋅ ⋅∆
−
∆
= − ox
drawn
drawn C
L L
W W
From equation (6–11), the plots of parameter β0 versus Wdrawn and parameter 1/β er Ldrawn can b
plot of parameter β0 versus Wdrawn, the parameters ∆W can be obtained (with known value of Cox) from the x–axis intercept of the best–fit linear line for the experimental data. With the determined parameter ∆W, the parameters ∆L and µ0 can be obtained (with known value of Cox) from the x–axis intercept and slope of the best–fit linear line for the experimental data, respectively, from the plot of parameter 1/β0 versus Ldrawn.
6–3 Experimental Results an
The proposed extraction method is ap u
iguration using on–wafer RF probes and an HP 8510C vector network analyzer. The initial calibration is performed on a separate ceramic calibration substrate using a SOLT calibration method. Before the extraction procedure, the parasitic components of input and output pads and interconnections have to be removed. To remove on–wafer pad parasitics, a two–steps de–embedding technique is carried out by subtracting S–parameters of the open pad structure from S–parameters of the measured devices.
The S–parameters measurements for test devices are performed at different gate voltages for zero drain voltage. The small–signal sour
arameter Z22d , which excludes the parasitics of pads and interconnections by de–embedding technique.
The test d ces are n–MOSFETs with drawn gate length ranging from 0.35 to 20 µm, drawn gate width
evi
ranging from 0.35 to 2 µm, and oxide thickness of 109 Å. All the parameters of the MOS
Ts with several drawn gate
(6–8), the parameter θ2 can be determined from the y–axis inter
easurement using linear extra
ization to fit equation (6–7) to the experimental data gdsm shown in Fig.
etermine the parameters ∆L, ∆W and µ0. Figs. 6–8(a) and 6–8(b) show the plots of para
FETs mentioned above are extracted by using equations (6–7)–(6–11).
Figure 6–4 shows the measured data gdsm as a function of gate voltage for different drawn gate lengths. Fig. 6–5 shows the linear plots of F2(Vgs) versus Vgs for n–MOSFE
lengths. From this figure, the threshold voltage VT and parameter β0 can be obtained from the x–axis intercept and slope, respectively, of the best–fit straight line of the measured data for each device according to equation (6–10).
Figure 6–6 shows the linear plots of F1(Vgs) versus 1/(Vgs–VT)2 for devices with different drawn gate lengths. According to equation
cept of the best straight–line fit of the measured data for each device.
Figure 6–7 shows the comparison of the threshold voltage, as a function of drawn gate length, obtained by the proposed method, and the one extracted from DC Id–Vgs m
polation method [90]. In this figure, the error bars show the 97%–confidence intervals of VT
obtained by the present extraction method. The small difference between the values of VT obtained by these two methods makes the present method become the alternative of determining VT of MOSFETs in RF applications.
With the extracted threshold voltage VT, parameters β0 and θ2, we determine the two remaining parameters RT and θ1 by optim
6–4.
Next, we make use of the extracted values β0 of devices with different drawn gate lengths and widths to d
meter β0 versus Wdrawn, and parameter 1/β0 versus Ldrawn, respectively. In Fig. 6–8(a), we determine the parameter ∆W from the x–axis intercept of the best–fit straight line for the experimental data β0. In Fig. 6–8(b), the parameters ∆L and µ0 are extracted from the x–axis intercept and slope of the best–fit straight line for the experimental data 1/β0.
The extracted values of parameters VT, RT, µ0, θ1, θ2, ∆L, ∆W and β0 for test devices with different drawn lengths are summarized in Table 7. Theoretically, the parameters RT, θ1 and θ2 are inde
with Wdrawn/Ldrawn = 10 µm/ 0.5 µm. The inset in Fig. 6–9 shows the intrinsic chan
ves are shown as the s
pendent of gate length. In this work, it is seen to be the case for parameters RT and θ1 obtained by the independent parameter optimization on the measured data for different gate lengths, where even if the parameter θ2 is determined from the measured data, rather than optimization on the measured data.
Figure 6–9 shows the plot of effective inversion layer mobility µeff versus gate bias Vgs for a MOS transistor
nel conductance gds as a function of Vgs obtained from equation (6–5) with the extracted parameter RT. Due to the fact that effective inversion layer mobility µeff is usually extracted from the intrinsic channel conductance gds directly [90], with the relationship between gds and gate bias, extracted parameters VT, RT, ∆L, ∆W and the known Cox, µeff is determined through equation (6–4).
In Fig. 6–9, it is seen that the extracted µeff by equation (6–4) has a significant raise with reducing Vgs just above VT. This is attributed to the failure of the approximation of inversion layer charges Qn
using equation: Qn = Cox(Vgs–VT) while Vgs approaches VT [90]. Besides, according to the SPICE–based mobility model expressed in equation (6–6), µeff can be also obtained and shown in Fig. 6–9. Since the difference between the two sets of µeff obtained by equations (6–4) and (6–6) is within 2% in the strong inversion region, the µeff calculated by equation (6–6) using extracted parameters θ1 and θ2 should be a good prediction of actual mobility in this region.
Additionally, the curves of experimental data gdsm as a function of gate voltage Vgs is compared to those calculated using equation (6–7) and the extracted parameters. These cur
olid lines in Fig. 6–10 and a good agreement is obtained over the range of Vgs where the experimental gdsm are used in the extraction procedure. In addition, simulated results Ids as a function of gate bias obtained from equation (6–2) with the extracted parameters are compared with the experimental data. The comparison results are shown in Fig. 6–11 for devices with different drawn gate lengths biased at Vds = 0.1 V. In these figures, a good agreement is obtained between the
experimental data and simulated results.
6–4 Conclusions
In summary, a simple and novel method using S–parameters measurement has been proposed r the simultaneous extraction of threshold voltage VT, sum of drain and source series resistance RT, gain
fo
factor βeff, and mobility degradation parameters θ1 and θ2 of MOSFETs. In addition, by carrying out the extraction method for devices with different geometries, the effective channel length Leff and width Weff can be also obtained. The proposed method, based on the relationship between small–signal source–drain conductance and gate bias, is shown to provide good agreements to the experimental data. The advantages of this method are the accuracy and simplicity as well as a number of parameters can be obtained by a single measurement, and by using S–parameters measurement and avoiding DC drain bias, the influence of drain bias on the extraction of the parameters has been eliminated.