完全空乏型單晶矽在絕緣層上之短通道金氧半場效電晶體的二維分析及新解析模式

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(1)國. 立. 交. 通. 大. 學. 電子工程學系電子研究所博士論文. 完全空乏型單晶矽在絕緣層上之短通道金氧半場效電晶體的二維分析及新解析模式 2–D Analysis and New Analytical Models for Fully–Depleted SOI Short–Channel MOSFETs. 研究生：王漢邦指導教授：張國明博士中華民國九十三年十二月.

(2) 完全空乏型單晶矽在絕緣層上之短通道金氧半場效電晶體的二維分析及新解析模式 2–D Analysis and New Analytical Models for Fully–Depleted SOI Short–Channel MOSFETs. 研究生：王漢邦. Student : Han–Pang Wang. 指導教授：張國明博士. Advisor : Dr. Kow–Ming Chang. 國立交通大學電子工程學系. 電子研究所. 博士論文 A Dissertation Submitted to Institute of Electronics, Department of Electronics Engineering College of Electrical Engineering and Computer Science National Chiao Tung University For the Degree of Doctor of Philosophy in Electronics Engineering December, 2004 Hsinchu, Taiwan, Republic of China. 中華民國九十三年十二月.

(3) 完全空乏型單晶矽在絕緣層上之短通道金氧半場效電晶體的二維分析及新解析模式. 研究生:王漢邦. 指導教授:張國明博士國立交通大學電子工程學系電子研究所博士論文. 摘. 要. 本論文針對完全空乏型之單晶矽/二氧化矽金氧半場效電晶體建立了臨界電壓、汲極電流之解析模型。此外，並對於結合大傾角佈植（Halo or Pocket Implantation）製程之短通道完全空乏型單晶矽/二氧化矽金氧半場效電晶體，依序建立其電位分佈、臨界電壓以及次臨界電流之解析模式。另外，本文亦推導一適用於高頻積體電路之金氧半場效電晶體小信號模型及一正確的參數萃取方法。在二維數值分析以及相關實驗之測試下，所提出的解析模式之有效性已經成功地被驗證。第一章包含有關於我們研究動機的概括論述及介紹本論文的組織架構。在第二章中，我們利用三區域格林函數解法（Three–Zone Green’s Function Solution Method）於二維帕松方程式（Poisson’s Equation），且根據適當的邊界條件選取合適的格林函數，精確地解出位於前/ 後閘二氧化矽以及單晶矽內的二維電位分佈。我們藉由在前閘二氧化矽與單晶矽介面間應用高斯定律（Gauss’s Law）來定義臨界電壓。在推導出的二維電位分佈函數之基礎下，我們提出了一新方法用以避免傳統欲求得最小表面電場位置時，可能需要的重複運算以及時間耗費。我們將使用垂直平均電場來替代前二氧化矽/單晶矽介面間最小表面電場，並由此來定義臨界電壓。但是，這將會忽略了來自源極及汲極接面的側向電場侵入。因此，我們將引入一.

(4) 具有物理意義之修正因子以彌補此一可能產生的錯誤，並且提升此解析模型之準確性。經由二維數值分析比較之後，證實此模式可準確地預測完全空乏型之單晶矽/二氧化矽金氧半場效電晶體在各種不同結構及外加偏壓下之臨界電壓。在第三章中，我們將前一章所得之臨界電壓模式對於汲極電壓加以線性化，置入線性區域之電流–電壓解析模式中，以考慮汲極導引位障降低（Drain–Induced Barrier Lowering, DIBL）效應。此外，並將溫度提昇模型一併考慮在內。接著，在飽和區域之電流–電壓解析模式中包含了汲極飽和電壓模式以及通道長度調變模式（Channel Length Modulation, CLM）。再者，次臨界區域電流–電壓解析模式也涵蓋在內。其中，寄生電阻、溫度、撞擊離子化及寄生雙載子電晶體等效應皆內含於所提出之電流–電壓解析模式中。經由實驗結果分析比較之後，發現所得到的解析模式可以準確地估算完全空乏型之單晶矽/二氧化矽金氧半場效電晶體在各種不同外加偏壓下電流–電壓關係。在第四章中，我們將探討具有大傾角佈植結構之短通道完全空乏型單晶矽/二氧化矽金氧半場效電晶體，並建立其電位分佈、臨界電壓以及次臨界電流之解析模式。首先，我們應用三階連續函數於二維帕松方程式，配合適當的邊界條件，解出單晶矽內部的二維電位分佈，並進而推得前閘二氧化矽與單晶矽介面處之電位分佈。接著，藉由求出最低表面電位，進而導出臨界電壓解析模式。此外，配合漂移–擴散電流方程式，我們推導出次臨界電流之解析模型。所提出的解析模式經由與二維數值模擬比較結果顯示，我們發現：當通道長度縮減到 0.06 微米時，解析模式也能獲得令人滿意的結果。第五章提出了一個適用於高頻電路方面應用之金氧半場效電晶體小信號模型及其相關參數之萃取方法。此小信號模型考慮了閘極區域內呈現連續分佈之閘極電阻、基板電阻網路及不可互逆的電容。在適當的假設及邊界條件之下，配合閘極區域之傳輸線方程式，即可求得位於閘極區域之電流及電壓關係式。接著，配合二埠電路模型，我們求得等效電路之 Y 參數。此外，以所求得之 Y 參數與頻率之關係為基礎，我們發展出一套準確的電路參數萃取方法。此參數萃取方法已成功地應用在實驗數據的參數取得上，我們發現其所萃取出的參數仍具有相當的物理意義。此外，將所萃取得之參數置入小信號模型中，經由計算結果與實驗數據比較分析後，我們得知：即使當操作頻率提昇至 10 G 赫茲時，此小信號模型仍可準確預測電.

(5) 晶體之高頻特性。第六章中，在為了能夠同時萃取得金氧半場效電晶體交流及直流參數的動機之下，我們提出了一個參數萃取方法：除了萃取得交流參數之外，藉由使用 S 參數量測方法來萃取金氧半場效電晶體之元件參數。所萃取的參數包含了臨界電壓、寄生串聯電阻、有效之載子遷移率以及元件尺寸相關參數。此參數萃取方法已成功地應用於實驗數據上，經由實驗數據以及模擬計算結果的分析比較之後，我們得知此一參數萃取方法提供了極佳的準確性。第七章將本論文的重要貢獻做一整理回顧，並展望值得延伸探討的研究方向。.

(6) 2–D Analysis and New Analytical Models for Fully–Depleted SOI Short–Channel MOSFETs. Student: Han–Pang Wang. Advisor: Dr. Kow–Ming Chang. Department of Electronics Engineering & Institute of Electronics National Chiao Tung University Hsinchu, Taiwan, R. O. C.. ABSTRACT The analytical models for the threshold voltage and drain current of short–channel fully–depleted SOI MOSFETs have been developed in this thesis. Additionally, new analytical models of potential distribution, threshold voltage and subthreshold current of short–channel fully–depleted SOI MOSFETs with halo and pocket implants have also been proposed. Moreover, a new small–signal model of MOSFETs and the relevant parameter extraction method are presented for high frequency applications. Based on the numerical analysis and experimental results, the validities of the developed analytical models are successfully verified. This thesis is consisted of seven chapters. In Chapter 1, the potential advantages of SOI MOSFETs are globally discussed and the organization of the thesis is given. In Chapter 2, a three–zone Green’s function solution method is proposed to analytically model the potential distributions in the front/bottom oxide and silicon regions of the fully–depleted SOI MOSFETs. The exact solution of 2–D Poisson’s equation is obtained by means of the Green’s theorem, in which the Green’s function solutions are determined according to the appropriate boundary conditions. The threshold voltage is defined by applying the Gauss’s Law to the surface of the silicon film. Based on the derived 2–D potential distribution, a new approach of approximating the normal electric field at the location of minimum surface potential with the average electric filed is proposed to avoid the.

(7) iterations in solving the position of the minimum surface potential. In the development of the analytical threshold voltage model, a modified factor accounting for the lateral electric encroachment from the drain junction is further introduced to compensate the error resulted from the above approximation. Comparisons between the developed analytical threshold voltage model and the 2D numerical analysis are presented. It is shown that good agreements are achieved for wide range of device structure parameters and applied biases. In Chapter 3, a new analytical model for I–V characteristics of fully–depleted SOI MOSFETs is proposed, in which an analytical threshold voltage model considering the drain–induced barrier–lowering (DIBL) effect and a temperature raise model are incorporated. The DIBL factor, which is obtained by linearizing the threshold voltage model derived in the Chapter 2, is then incorporated into the I–V model in the linear region. In the saturation region of the I–V model, a quasi–2D saturation model, which includes a source–drain saturation voltage model and a channel length modulation model is presented. Furthermore, the effects of the parasitic series resistances, temperature raise, impact ionization and parasitic bipolar junction transistor are included in the developed I–V model. It is shown that good agreements are obtained between the experimental data and the simulation results. In Chapter 4, new analytical models of subthreshold surface potential, threshold voltage and subthreshold current for the fully–depleted SOI MOSFETs with halo or pocket implants are developed. By using the cubic series function method, the 2–D Poisson’s equation for the fully–depleted SOI MOSFETs with halo implants is solved with the proper boundary conditions. Then, the subthreshold surface potential model is consequentially derived. Further, the threshold voltage model is defined by the minimum surface potential. Moreover, with the aids of the drift–diffusion current equation, the analytical subthreshold current model is derived. These derived analytical models have been compared with the 2–D numerical analysis and excellent agreements are obtained, which validates the accuracy of the models. In Chapter 5, a new small–signal MOSFET model and a relevant parameter extraction method.

(8) are proposed for RF IC applications. The small–signal model considers the distributed gate resistances, substrate network and the nonreciprocal capacitance. With the suitable assumptions and boundary conditions, the transmission line equation along the gate region is solved. Then, by applying the two–port circuit model, the Y–parameters of the small signal circuit are obtained. An extraction method for the relevant parameters of the small signal model is presented in detail. The extraction method has been applied to the experimental data and the extracted parameters show good physical meanings. Furthermore, with the extracted parameters, the derived Y–parameters are in a good agreement with the experimental data for the frequency up to 10 GHz, which shows the validity of the developed small signal MOSFET model and the parameter extraction method. In Chapter 6, an efficient method using S–parameters measurement is proposed for the extractions of the threshold voltage, parasitic series resistances, effective mobility and geometric dimensions of the MOSFETs. The proposed method provides the simultaneous extractions of the AC– and DC–related parameters. The method has been applied to the experimental data for a wide range of geometries, and a good agreement is obtained between the experimental data and the simulation results. Chapter 7 summarizes the conclusions of this thesis, in which the major contributions as well as the suggested future researches are given..

(9) CONTENTS. ABSTRACT ACKNOWLEDGEMENTS TABLE CAPTIONS FIGURE CAPTIONS NOMENCLATURE CHAPTER 1 Introduction. 1. 1–1 General Introduction. 1. 1–2 Organization of the Thesis. 6. CHAPTER 2 A Simple 2–D Analytical Threshold Voltage Model for Fully–Depleted Short–Channel SOI MOSFETs. 8. 2–1 Introduction. 8. 2–2 Derivation of the Analytical Threshold Voltage Model. 9. 2–2.1. Basic Analysis. 2–2.2. A New Approach for the Development of the Threshold Voltage Model. 9 11. 2–3 Verifications and Discussion. 15. 2–4 Conclusions. 17. CHAPTER 3 A New Analytical I–V Model for Fully–Depleted Short–Channel SOI MOSFETs 18 3–1 Introduction. 18. 3–2 Model Derivations. 19. 3–2.1. Analytical Threshold Voltage Model. 3–2.2. Analytical I–V model 3–2.2.1 I–V Characteristics in Linear Region (Vgs > VTH, VDS < VDSAT). 19. 21.

(10) 3–2.2.2 I–V Characteristics in Saturation Region (Vgs > VTH, VDS > VDSAT). 22. 3–2.2.3 I–V Characteristics in Subthreshold Region (Vgs < VTH). 27. 3–2.2.4 Impact–Ionization Effect and Parasitic Bipolar Junction Transistor (BJT) 29 3–2.3. Temperature Rise Model and Temperature Dependent Parameters. 30. 3–3 Verifications and Discussion. 32. 3–4 Conclusions. 33. CHAPTER 4 New 2–D Models for Threshold Voltage and Subthreshold Current of Fully–Depleted Short–Channel SOI MOSFETs With Halo or Pocket Implants 34 4–1 Introduction. 34. 4–2 Two–Dimensional Subthreshold Surface Potential Model. 36. 4–3 Two–Dimensional Threshold Voltage Model. 40. 4–4 Subthreshold Current Model. 42. 4–5 Results and Discussion. 44. 4–6 Conclusions. 49. CHAPTER 5 A New Small–Signal MOSFET Model and Parameter Extraction Method for RF IC’s Applications. 51. 5–1 Introduction. 51. 5–2 Small Signal RF MOSFET Model. 52. 5–2.1. Approaches and Assumptions. 53. 5–2.2. Analysis for New RF MOSFET Model. 54. 5–3 Parameter–Extraction Method. 59. 5–4 Verification with Experiments and Result Discussion. 63. 5–5 Conclusions. 65. CHAPTER 6 An Efficient Method for Determining Threshold Voltage, Effective Inversion.

(11) Layer Mobility, Series resistance, and Effective Geometries of MOSFETs by S–parameter Measurement. 67. 6–1 Introduction. 67. 6–2 Theory of the Extraction Method. 69. 6–3 Experimental Results and Discussion. 73. 6–4 Conclusions. 76. CHAPTER 7 Conclusions. 77. 7–1 Major Contributions of the Thesis. 77. 7–2 Proposed Future Researches. 78. APPENDICES REFERENCES VITA PUBLICATION LIST.

(12) TABLE CAPTIONS Table 1 List of the boundary conditions for Zone I (front gate oxide region), Zone II (silicon film) and Zone III (bottom oxide region). Table 2 Green’s functions in Zone i, i = 1 ~ 3. Table 3 The expressions of coefficients Dsfm and Dsbm . Table 4 The expressions of threshold voltage related coefficients G m , Fbm , Fdm and Fgm . Table 5 The fitting parameters of an n–channel FD SOI MOSFET under study. Table 6 Summary of the extracted small signal parameters for an n-MOSFET with 105 µm width and 0.18 µm length biased at Vds = 1.4 V and different Vgs. Table 7 Summary of the extracted parameters for devices with different drawn gate lengths..

(13) FIGURE CAPTIONS Fig. 1–1 (a) The cross–section view of the conventional bulk CMOS, in which a latch–up path is shown. (b) The equivalent circuit of the latch–up path. (c) The cross–section view of the SOI CMOS. Fig. 1–2 Illustrations of the parasitic junction capacitances reside in (a) bulk MOSFET and (b) SOI MOSFET. Fig. 1–3 Illustrations of the radiation effects on (a) bulk device and (b) SOI device. Fig. 1–4 Illustrations of the contact formation on the shallow junctions in the case of (a) bulk and (b) SOI MOSFETs. Fig. 1–5 The cross–sections and layouts of the (a) bulk CMOS inverter and (b) SOI CMOS inverter. Fig. 2–1 The schematic diagram of a fully–depleted SOI MOSFET, where the simplified domains for analytically solving the 2–D Poisson’s equation are indicated by the bold lines. Fig. 2–2 The schematic diagram of a fully–depleted SOI MOSFET, where the arrows in (a) represent the average surface normal electric field and the arrows in (b) represent the surface normal electric field and lateral field originating from source/drain junctions. Fig. 2–3 The calculated threshold voltage as a function of effective channel length with the thickness of the Si film as a parameter. Fig. 2–4 The calculated threshold voltage as a function of effective channel length with the thickness of the front gate oxide as a parameter. Fig. 2–5 The calculated threshold voltage as a function of effective channel length with the doping concentration of the bulk Si film as a parameter. Fig. 2–6 The calculated threshold voltage as a function of effective channel length with the back gate bias voltage as a parameter..

(14) Fig. 2–7 The threshold voltage roll–off versus effective channel length for different back gate biases from the present model and the experiment. Fig. 2–8 The calculated threshold voltage as a function of effective channel length with the drain bias voltage as a parameter. Fig. 2–9 The threshold voltage roll–off versus effective channel length for different drain biases from the present model and the experiment. Fig. 2–10 The calculated threshold voltage as a function of effective channel length with (a) VBS, (b). VDS, (c) tfox, and (d) tsi as the parameters. Fig. 3–1 The schematic diagram of a fully–depleted SOI MOSFET operated in the saturation region, where the domains indicated by the dashed lines (1)–(4) are the Gauss boxes in the channel region and drain edge. Fig. 3–2 (a) The IDS–VGS characteristics in the above–threshold region from the model and measurement at Vds = 50 mV and Vbs = 0, –5 V [46] for SOI MOS devices with different effective channel lengths. (b) The IDS–VGS characteristics in the above–threshold region from the model and measurement at Vds = 1 V and Vbs = 0, –5 V [46] for SOI MOS devices with different effective channel lengths. Fig. 3–3 (a) The IDS–VGS characteristics in the subthreshold region from the model and measurement at Vds = 50 mV and Vbs = 0 V [46] for SOI MOS devices with different effective channel lengths. (b) The IDS–VGS characteristics in the subthreshold region from the model and measurement at Vds = 1 V and Vbs = –5 V [46] for SOI MOS devices with different effective channel lengths. Fig. 3–4 (a) The output IDS–VDS characteristics and (b) the output GDS–VDS characteristics from the model and measurements for a SOI MOS device with tfox = 10 nm, tbox = 347 nm, tsi = 94 nm, NB = 1×1016 cm-3, VBS = 0 V, W = 7.83 µm, L = 0.28 µm and Rs = Rd = 140 Ω, [47] where VGFT = VGS – VTH. Fig. 3–5 The output IDS–VDS characteristics from the model and measurements for a SOI MOS.

(15) device with tfox = 27 nm, tbox = 449 nm, tsi = 150 nm, NB = 3.2×1016 cm-3, VBS = 0 V, W = 10 µm, L = 1 µm and Rs = Rd = 40 Ω. [48] Fig. 3–6 The output IDS–VDS characteristics from the model and measurements for a SOI MOS device with tfox = 7 nm, tbox = 400 nm, tsi = 80 nm, NB = 5×1017 cm-3, VBS = 0 V, W = 9.5 µm, L = 0.25 µm and Rs = Rd = 100 Ω. [49] Fig. 4–1 The cross–sectional view of an n–channel fully–depleted SOI MOSFET. The structure has been simplified by the neglect of doping gradients in the y–direction to focus upon the average doping values of NA and NB. Fig. 4–2 The schematic diagrams of a FD SOI MOSFET with halo regions for several channel L: (a) long–channel case for which L > 2L1, (b) L = 2L1, (c) partial overlap of halo regions with the channel region for which L1 < L < 2L1, and (d) complete overlap of halo regions with the channel region for which L ≤ L1. L1 is the length of the halo region, and NA and. NB are the doping concentrations in the halo and channel regions, respectively. Fig. 4–3 Energy band diagram for VGS = 0 V of an n–MOSFET with n+–polysilicon gate and p–type silicon film. The potentials, Ψfs, φ fs , ΨFP and Ψnpoly are defined in the diagram, where qVox is the band bending at SiO2 and Eg is the bandgap of silicon. Fig. 4–4 Surface potential distributions of the fully–depleted SOI MOSFETs obtained by the analytical model and Medici simulation for different drain biases VDS, gate lengths L and halo region lengths L1. (a) L = 0.06 µm, L1 = 0.05 µm, (b) L = 0.09 µm, L1 = 0.05 µm, (c). L = 0.25 µm, L1 = 0.05 µm, (d) L = 0.06 µm L1 = 0.025 µm, and (e) L = 0.1 µm, L1 = 0.025 µm. Fig. 4–5 The surface potential profiles Ψfs (x) against the lateral position in channel x for halo devices with different gate lengths and halo doping profiles. (a) Halo doping concentration N A = 2 × 1018 cm −3 and (b) N A = 5 × 1018 cm −3 . Fig. 4–6 The surface potential profiles Ψfs (x) as a function of normalized position (x/L) along the.

(16) channel length for FD halo–implanted SOI MOSFETs of L = 0.09 µm with the length of the halo region L1 as a parameter. Fig. 4–7 The plot of the threshold voltage versus the gate length for SOI MOSFETs with different silicon film thicknesses tsi. Fig. 4–8 The plot of the threshold voltage versus the gate length for SOI MOSFETs with different front gate oxide thicknesses tf. Fig. 4–9 The graph of the threshold voltage versus the gate length for SOI MOSFETs with the halo doping concentration NA as the parameter. Fig. 4–10 The surface potential distributions of the SOI MOSFETs with different halo doping concentrations NA. (a) L = 0.15 µm and (b) L = 0.05 µm. Fig. 4–11 The graph of the threshold voltage versus the gate length for SOI MOSFETs with the channel doping concentration NB as the parameter. Fig. 4–12 The plot of the threshold voltage versus the gate length for SOI MOSFETs with different substrate bias voltages VSUB. Fig. 4–13 The plot of the threshold voltage versus the gate length for SOI MOSFETs with different drain bias voltages VDS. Fig. 4–14 The plot of the subthreshold current ISUB versus the gate–source voltage VGS for FD halo–implanted SOI MOSFETs of L = 0.06 µm with different drain–source voltages VDS. Fig. 4–15 The plot of the front surface potential Ψfs(x) as a function of normalized position (x/L) along the channel length for FD halo–implanted SOI MOSFETs of L = 0.06 µm with different halo doping concentrations NA. Fig. 4–16 The plot of the subthreshold current ISUB versus the gate–source voltage VGS for FD halo–implanted SOI MOSFETs of L = 0.06 µm with different halo doping concentrations. NA. Fig. 4–17 The plot of the off–state current Ioff versus the gate length L for FD halo–implanted SOI MOSFETs with different halo doping concentrations NA..

(17) Fig. 4–18 (a) The plot of the front surface potential Ψfs(x) as a function of normalized position (x/L) along the channel length for FD halo–implanted SOI MOSFETs of L = 0.06 µm with different channel doping concentrations NB. The figure (b) is the enlargement of a part of the figure (a). Fig. 4–19 The plot of the subthreshold current ISUB versus the gate–source voltage VGS for FD halo–implanted SOI MOSFETs of L = 0.06 µm with different channel doping concentrations NB. Fig. 5–1 Pictorial view of the distributed elements within a MOS transistor along the gate width. Fig. 5–2 Small signal equivalent circuit of an MOSFET for RF modeling. Fig. 5–3 Equivalent circuits of shunt–shunt feedback loops are presented. By feedback theorem [84], feedback loops A and B can be transformed into equivalent loadings on the input and output nodes. Fig. 5–4 Small signal equivalent circuit of an MOSFET after feedback loops transformation. Fig. 5–5 Real and imaginary parts of tanh. (. A ⋅W. )(. A ⋅W. ) as a function of frequency.. Fig. 5–6 The extraction results of transconductance gm and channel conductance gds. (a) gm is obtained from the y–intercept of Re[Y21] versus w2 at low frequency. (b) gds is obtained from the y–intercept of Re[Y22] versus w2 at low frequency. Fig. 5–7 (a) The extraction results of w/Im[Ysub] as a function of w2, where gm can be determined from the y–intercept. (b) The extraction result of w2/Re[Ysub] as a function of w2, where the Cb can be determined from the slope. Fig. 5–8 Frequency dependence of the extracted capacitances for an n–MOSFET with 105 µm width and 0.18 µm length biased at Vgs = 1 V and Vds = 1.4 V. The extracted capacitances remain almost constant with frequency and thus verify that the extraction method is reliable and accurate. Fig. 5–9 Frequency dependence of the extracted resistances for an n–MOSFET with 105 µm width.

(18) and 0.18 µm length biased at Vgs = 1 V and Vds = 1.4 V. Fig. 5–10 Real and imaginary parts of Y–parameters (a) Y11; (b) Y 12; (c) Y 21; and (d) Y 22 as a function of frequency for a device with 105 µm width and 0.18 µm length biased at Vgs = 1 V and Vds = 1.4 V. The simulation results obtained by proposed model have a good agreement to the experimental data. Fig. 5–11 Gate bias dependence of small–signal parameters for an n–MOSFET with 105 µm width and 0.18 µm length biased at Vds = 1.4 V. (a) Capacitances and (b) Resistances. Fig. 5–12 Drain bias dependence of small–signal parameters for an n–MOSFET with 105 µm width and 0.18 µm length biased at Vgs = 1 V. (a) Capacitances and (b) Resistances. Fig. 5–13 The bias dependence of transconductance gm obtained from S–parameters measurement by the proposed extraction method and from the conventional DC measurement for an n–MOSFET with 105 µm width and 0.18 µm length. (a) Gate bias dependence and (b) Drain bias dependence. Fig. 6–1 The small–signal equivalent circuit of a MOSFET, where Rg, Rs and Rd are series resistances, Lg, Ls and Ld represent the interconnection parasitics, the capacitors Cpg and Cpd in series with the resistors Rpg and Rpd model the parasitics of the pads. Fig. 6–2 Equivalent circuit of a MOSFET for gate voltage above pinchoff and zero drain voltage, where a distributed channel resistance Rch' and a distributed gate capacitance C g' are used to model the intrinsic device. Fig. 6–3 Schematic circuit model of a MOS transistor, where g, d and s denote the external nodes, and d’ and s’ denote the internal nodes. Vgs’ and Vgd’ represent the internal gate–source voltage and gate–drain voltage, respectively, and Vd’s’ denotes the internal drain–source voltage. Fig. 6–4 The measured data gdsm as a function of gate bias Vgs for n–MOSFETs with different drawn gate lengths..

(19) Fig. 6–5 The plots of F2(Vgs) versus Vgs for n–MOSFETs with different drawn gate lengths. The symbols represent the experimental data and the solid lines are the best–fit straight line to the experimental data. The intercept on the Vgs axis yields VT, and the slope of the straight–line yields (β0/2)1/3. Fig. 6–6 The plots of F1(Vgs) versus 1/(Vgs–VT)2 for n–MOSFETs with different drawn gate lengths. The symbols represent the experimental data and the solid lines are the best–fit straight line to the experimental data. The intercept on the F1(Vgs) axis yields θ2/β0. Fig. 6–7 The plots of the extracted results of VT obtained by the proposed method and linear extrapolation method [90]. The filled circles represent the VT obtained by the proposed method, and the open circles represent the results obtained by linear extrapolation method. Error bars show the 97%–confidence interval of VT obtained by the proposed method. Fig. 6–8 The plots of (a) experimentally determined β0 versus Wdrawn for devices with different drawn gate widths, and (b) experimentally determined 1/β0 versus Ldrawn for devices with different drawn gate lengths. The open symbols represent the experimental data and the solid lines are the best–fit straight line to the experimental data. The intercepts on the Wdrawn axis and Ldrawn axis yield ∆W and ∆L, respectively. Fig. 6–9 The effective inversion layer mobility µeff for n–MOSFETs with Wdrawn/Ldrawn = 10 µm/0.5 µm. The open symbols are values extracted from intrinsic gds by equation (6–4), the solid lines are values calculated by equation (6–6) with the extracted parameters µ0, θ1 and θ2. The inset shows the intrinsic gds obtained by equation (6–5) as a function of gate bias. Fig. 6–10 The plots of the comparisons of the simulated results obtained by proposed method with the experimental data gdsm of n–MOSFETs with different drawn gate lengths. Fig. 6–11 The plots of the comparisons of the simulated results obtained by proposed method with the experimental data Ids of n–MOSFETs with different drawn gate lengths..

(20) Nomenclature ε si [ε ox ]. The dielectric permittivity of Si [SiO2].. q. The elementary charge.. ρ ( x, y ). The two-dimensional charge density.. t si. The thickness of silicon film.. t fox [t box ]. The thickness of front [back]-gate oxide.. ni. The intrinsic carrier concentration of Si semiconductor.. L[W ]. The effective channel length [width].. C fox [Cbox ]. The capacitance per unit area of the front [back] gate oxide.. Csi. The capacitance per unit area of the silicon film.. [ ]. VGS Vgs. The external [intrinsic] gate-source voltage.. VDS [Vds ]. The external [intrinsic] drain-source voltage.. VBS [Vbs ]. The external [intrinsic] back gate-source voltage.. [ ] [V ]. b VFBf VFB. The flat band voltage of the front [back] gate.. Vgs'. b Vgs' = V gs − VFBf Vbs' = Vbs − VFB .. ' bs. [. ]. Vbi ( y ). The built-in potential of the source [drain]/ body junctions in Zone II.. NB f (y). The doping profile in the Zone II, where f ( y ) is a doping profile function.. ND. The doping concentration in the source/drain region.. k ni. The eigenvalue of Zone i (i = I , II , III ) . k nI = ((n − 1 2)π ) t fox for Zone I,. k nII = nπ t si for Zone II and k nIII = ((n − 1 2 )π ) t box for Zone III. km. The eigenvalue in all Zones. k m = mπ L .. Dsf ( x )[Dsb ( x )]. The electric displacement at the front [back] Si-SiO2 interface.. φ i ( x, y ). The 2-D potential distribution in Zone i (i = I , II , III ) .. E yi ( x, y ). The 2-D vertical electric field distribution in Zone i (i = I , II , III ) ..

(21) φ sfII ( x )[φ sbII (x )]. [ ]. QBn QB0. The front [back] surface potential in Zone II. The Fourier coefficient of the bulk charge density with the integer n [n = 0] in Zone II.. [ ]. Dsfm Dsbm. QBn =. 2 t si. ∫ (− qN f ( y ))cos k. QB0 =. 1 t si. ∫ (− qN f ( y ))⋅ dy. t si. B. 0. II n. y ⋅ dy. t si. B. 0. The Fourier coefficient of the electric displacement at the front [back] surface.. 2 L Dsf ( x )sin (k m x ) ⋅ dx L ∫0 2 L Dsbm = ∫ Dsb ( x )sin (k m x ) ⋅ dx L 0. Dsfm =. [ ]. AnS AnD. The Fourier coefficient of the boundary potential at the source [drain] side in Zone I.. AnS = AnD =. [ ]. BnS B0S. [ ]. t fox. ∫. t fox. 0. 2. ∫. t fox. t fox. 0. φ I (0, y )cos k nI y ⋅ dy φ I (L, y )cos k nI y ⋅ dy. The Fourier coefficient of the source boundary potential with the integer n. BnD B0D. 2. [n = 0]. in Zone II.. BnS =. 2 t si. ∫. t si. B0S =. 1 t si. ∫. t si. 0. 0. Vbi ( y )cos k nII y ⋅ dy Vbi ( y ) ⋅ dy. The Fourier coefficient of the drain boundary potential with the integer n. [n = 0]. n Zone II.. BnD =. 2 t si. ∫ [V ( y ) + V ]cos k. B0D =. 1 t si. ∫ [V ( y ) + V ] ⋅ dy. t si. 0. bi. ds. t si. 0. bi. ds. II n. y ⋅ dy.

(22) [ ]. C nS C nD. The Fourier coefficient of the boundary potential at the source [drain] side in Zone III.. C nS = C nD =. φ f ,inv. 2 tbox 2 tbox. ∫. tbox. 0. ∫. tbox. 0. φ III (0, y )cos k nIII y ⋅ dy φ III (L, y )cos k nIII y ⋅ dy. The front surface potential at the onset of strong inversion.. φ f ,inv = 2φ fp = 2⎛⎜ k BT q ⎞⎟ ln⎛⎜ N B n ⎞⎟ ⎝. ⎠ ⎝. i. ⎠.

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(24) Chapter 1 Introduction 1–1 General Introduction. Since mid–1960s, the Metal–Oxide–Semiconductor Field Effect Transistor (MOSFET) has been treated as the most important electronic device, superseding the Bipolar Junction Transistor (BJT) and initiating a revolution in the Integrated Circuit (IC) industry. According to the statistics, more than 95% of the available microelectronic products are fabricated by the silicon–based technology, among which the bulk–MOS device stands for the most pronounced branch. Nowadays, it has invaded our daily lives by the magic power derived from its simple structure and low fabrication cost. For these reasons, the MOS technologies, especially the Complementary Metal–Oxide–Semiconductor. (CMOS),. are. taken. as. the. major. trend. for. Ultra–Large–Scale–Integration (ULSI) circuit and mass–production product. Other than the compact density, the figures of merit for IC performance also include high speed and low power consumption. In order to increase the packing density and to improve the circuit performance, the geometries of the bulk–MOS device have been continually scaled down [1]–[5]. However, as the bulk–MOS devices shrink to deep–submicrometer regime, several problems such as gate oxide reliability, shallow junction, parasitic capacitance, device isolation and radiation/plasma damage occur, and those limit the further scaling of the bulk–MOS devices [6]–[8]. Therefore, many manufacture techniques have been found to reduce the effects of these problems such as making shallow junction with raised source/drain regions, using deep trench isolation or epitaxial substrate to prevent the occurrence of the latchup, reduce the junction capacitance with Silicon–On–Insulator (SOI) technique, etc [9]–[11]. Among these techniques, the SOI CMOS technique is the most attractive one because it involves less processing steps than the bulk CMOS technique, and suppresses some yield hazard factors present in bulk CMOS. 1.

(25) Recently, the SOI MOSFETs have drawn much attention for its advantages over bulk MOSFETs such as elimination of latch–up problem, excellent device isolation, reduced junction capacitances and improved radiation hardness. The advantages of the SOI MOSFETs are discussed and described as follows.. a) Elimination of latch–up effect In the bulk CMOS technique, the latch–up effect is originated from the parasitic PNP (NPN) structure residing in the CMOS circuit. The latch–up path can be represented by two bipolar transistors (Q1 and Q2) and parasitic resistances (Rs and Rw), as shown in Fig. 1–1(a) and (b). The latch–up can be triggered by several different mechanisms, such as junction avalanche, voltage overshoot and displacement current [10]. The necessary condition for the occurrence of latch–up is that the current gain of the loop formed by these two bipolar transistors is larger than unity. However, in the SOI CMOS circuit, e.g., inverter, due to the existence of the high dielectric isolation between the active regions and substrate, the latch–up path is ruled out because no current path to the substrate exists, as shown in Fig. 1–1(c).. b) Reduced parasitic capacitances In the bulk MOSFETs, the parasitic junction capacitances, i.e., source–to–substrate and drain–to–substrate capacitances, which consist of two components: the capacitance between the source/drain and the substrate regions in the vertical direction, and the capacitance between the source/drain and the channel regions in the lateral direction, as shown in Fig. 1–2(a). These capacitances may increase with the substrate doping concentrations as the devices are shrunk to smaller geometries. However, in SOI MOSFETs, the junction capacitance in the vertical direction is replaced by the capacitance of buried oxide that is typically lower than the junction capacitance in bulk MOSFETs, as shown in Fig. 1–2(b). The reduced parasitic capacitance properties of the SOI MOSFETs make them very suitable for high–speed applications such as RF IC’s and 2.

(26) telecommunication.. c) Excellent radiation hardness Figure 1–3 shows the radiation effects on bulk and SOI MOSFET. From the figure, it is seen that the radiation effects are different for bulk and SOI MOSFETs. In general, when the MOSFETs are exposed in the radiation environment, the silicon volume would absorb the energy of radiation and subsequently the electron–hole pairs would be generated [12]. The radiation–induced electron–hole pairs may be collected by the source/drain junctions and contribute to the leakage current, and consequently soft–error may occurs. For SOI MOS devices, due to that the active region is isolated from the substrate, the radiation–induced electron–hole pairs generated in the substrate would not influence the device performance. Besides, due to that the volume of the active region above the buried oxide for absorbing the radiation energy, and the source/drain junction areas for collecting the radiation–induced electron–hole pairs are very small, the probability of occurring the soft–error for the SOI circuit is much reduced.. d) Simple IC processing Although the process techniques for the fabrication of CMOS circuit in bulk silicon wafer and in SOI wafer are very similar, the SOI fabrication process is simpler than bulk one. Firstly, there is no need to do the essential well implantation (even twin well), which is a necessary in the bulk CMOS process, in the SOI CMOS process. Besides, the guard–ring structure in the bulk CMOS circuit to suppress the latch–up problem is also unnecessary in SOI CMOS process. Secondly, due to the presence of the buried oxide film underneath the active region, the SOI isolation process is more effective in the isolating the active islands from one another. Thirdly, the source/drain shallow junctions are essential in the deep–submicrometer regime to ensure the less short–channel effects, but it is a difficult task for the bulk CMOS process. In the shallow junction processing, a harmful spiking effect may take place between the silicon substrate and metal conductor through the 3.

(27) source/drain junctions, as shown in Fig. 1–4. Such a junction punch–through may give rise to the uncontrolled leakage current. However, the source/drain junctions can be extended to the buried oxide in the SOI CMOS process, and hence the shallow junctions could be obtained.. e) High integration density Generally speaking, the SOI CMOS circuit can offer a higher integration density than bulk CMOS circuit. This can be observed from the layouts of the bulk CMOS inverter and SOI COMOS inverter shown in Fig. 1–5. It is seen that the area of the SOI CMOS inverter is smaller than that of the bulk CMOS inverter. This happens due to the following reasons. The major reason is the absence of the well in SOI CMOS, and consequently the number of the well contact is decreased. The second reason is that the possibility of having a direct contact between the P+ and N+ junctions, such as the drain regions of the p–channel and n–channel devices shown in Fig. 1–5. Moreover, the removal of the guard–ring structure could also increase the integration density. Depending on the relation of the thickness of silicon film to the maximum depletion width while the SOI MOSFET is turned on, two types of SOI MOS devices can be distinguished. One is the Fully–Depleted (FD) SOI MOSFET, where the silicon film is completely depleted, and the other one is the Partially–Depleted (PD) SOI MOSFET, where a neutral region exists other than the depleted region. Except for the advantages of the SOI CMOS technique mentioned above, there are two unique features of SOI MOSFETs needed to be considered and described in the following. 1) Floating–body effect: The most prominent electrical property of the PD–SOI device is that the body is floating, and subsequently the body voltage would vary during switching. The variation of the floating body potential may cause the threshold voltage vary, and consequently the I–V characteristics of the PD–SOI devices are no longer constant. The voltage of the floating body is dependent on the amount of charge contained in the body of the device at any given time. The charge content of the body, and the distribution of the charge are determined by the p–n junction leakage currents, the impact ionization current, and the capacitive coupling from the external 4.

(28) terminals during operation transitions. The variation of the threshold voltage resulting from the content of the charge in the body may cause a “kink effect” in the I–V characteristics of the devices [13]. However, the kink effect is undesirable for analog circuit because of the lower output resistance. Furthermore, due to the parasitic bipolar transistor presented in the SOI MOSFETs, the floating body effect may cause the reduction of the drain–source breakdown voltage. The classical remedy to the floating body problem is the use of a body contact. On the other hand, for the FD–SOI MOSFETs, due to the completely depleted region in the silicon film, the charge storage in not observe. Therefore, to understand, characterize and model the floating–body effect is essential in SOI CMOS technique. 2) Self–heating effect: Due to the presence of the buried oxide film beneath the device active region, SOI CMOS technique owns several advantages over the bulk CMOS one as mentioned in previous subsections. However, the low thermal conductivity of the buried oxide reduces the efficiency in removing the generated heat. In bulk technologies, heat generated by the charge transfer in the device can be readily removed out of the chip backside through the crystalline silicon substrate. The removal of the heat is quick enough that the local device performance change due to the self–heating is negligible. On the other hand, in SOI technique, it seems that the MOS device is encased in a perfect insulated region of its own, with inter–layer dielectric above, shallow trench isolation dielectric to the left and right sides, and buried oxide film underneath. As a result, the heat generated by the charge transfer is hard to be removed out through these dielectric films, and consequently an elevated device temperature is observed [14]. This phenomena is so–called Self–Heating Effect (SHE). The temperature increase induced by the SHE may give rise to some parameter variations such as carrier mobility and threshold voltage, and the further influence on the device performance. It must be emphasized that these effects would take place as the heat is dissipated into the device. In reality, in an operating digital CMOS circuit, there is almost zero current flowing through the devices in the standby mode. Therefore, the self–heating effects are greatly reduced. 5.

(29) From the above discussion, we believe that the SOI technology is a preferable choice for the deep–submicrometer generation in the applications of low power, high speed and high reliable integrated circuits.. 1–2 Organization of the Thesis. In Chapter 2, the 2–D Poisson’s equation is solved for a SOI MOSFET by using the three–zone Green’s function technique with the appropriate boundary conditions. In Section 2–2, the exact solution of the 2–D potential distribution in the silicon film is obtained and a 2–D analytical threshold–voltage model is derived based on the concept of the average electric field. Comparisons between the 2–D numerical analysis, experimental data and the proposed analytical threshold voltage model are shown in Section 2–3. Finally, the conclusions are summarized in Section 2–4. Based on the threshold–voltage model developed in Chapter 2, a new analytical I–V model is derived for fully–depleted SOI MOSFETs in Chapter 3. In Section 3–2, the derived threshold voltage is linearized with respect to the drain voltage to obtain the DIBL factor, which is subsequently incorporated into the I–V model derivation. The new I–V model accounts for the effects of the parasitic series resistances, self–heating effect, channel length modulation, impact ionization and parasitic bipolar junction transistor. The comparisons with the measured data and 2–D numerical simulation results are presented in Section 3–3. Conclusions are given in the final Section 3–4. In Chapter 4, the 2–D Poisson’s equation is solved for a fully–depleted SOI MOSFET with halo or pocket implants by assuming a power series potential distribution in the silicon film with the proper boundary conditions. The derivations of the surface potential model are given in Section 4–2. The derived surface potential model is further implemented to obtain an analytical threshold voltage model in Section 4–3. Moreover, with the derived surface potential model, an analytical subthreshold current is developed in Section 4–4. The calculated results of the subthreshold surface potential distribution, threshold voltage and subthreshold current are compared with the 2–D 6.

(30) numerical analysis in Section 4–5. Conclusions are summarized in Section 4–6. In Chapter 5, a high frequency analytical MOSFETs model is proposed to account for the distributed effects of the gate region, substrate parasitics and nonreciprocal capacitance. Besides, a direct parameter extraction method for the proposed model is also presented. The derivations of the small signal MOSFET model is described in Section 5–2. The details of the extraction method are shown in Section 5–3. The verifications of the small signal MOSFET model and extraction method are presented in Section 5–4. Eventually, the conclusions are given in the section 5–5. In Chapter 6, a simple method based on the small–signal conductance extracted by S–parameters measurements is proposed to accurately extract the threshold voltage, the parasitic series resistance, gain factor, and mobility degradation parameters. In Section 6–2, the parameter extraction method is described in detail. Subsequently, the present extraction method is performed for the parameters of the test devices with different geometries. The comparisons of the results obtained by the proposed method with the experimental data are presented and discussed in Section 6–3. The conclusions are summarized in Section 6–4. In the concluding chapter, the major contribution of the thesis is given is Section 7–1. Future researches deserved further efforts are proposed in Section 7–2.. 7.

(31) Chapter 2 A Simple 2–D Analytical Threshold Voltage Model for Fully–Depleted Short–Channel SOI MOSFETs 2–1 Introduction. The fully depleted (FD) silicon–on–insulator (SOI) CMOS technology has been becoming another major technology for the next generation of VLSI [15–17]. This is because that the FD SOI CMOS transistors provide superior electrical characteristics over bulk CMOS devices [18–20] such as reduced source/drain junction capacitances [21], increased carrier mobility [22], suppressed short channel effect [23], improved subthreshold slope [24], improved latchup immunity [25] and better radiation hardness [26]. However, the coupling effect between the front gate and back gate becomes complicated, especially for short channel devices. Therefore, it is difficult to develop a simple and accurate analytical model for circuit design and device characterization. In general, the threshold voltage of a MOS transistor is a very important physical parameter in the device design. On the other hand, the accuracy of the threshold voltage model plays a more important role in the device optimization and circuit design. The analytical modeling of the threshold voltage of the FD SOI MOS transistor has already been proposed by numerous authors [27–30]. In a paper by Young [27], the potential distribution in the Si film was approximated by a simple parabolic function. This simplified assumption underestimates the coupling effect of the source/drain region and may cause a significant error in the prediction of the threshold voltage when the channel length continues to scale down. In a paper by Veeraraghavan and Fossum [28], the threshold voltage model was developed based on the conventional charge–sharing scheme and it predicted a 1 Leff dependent threshold voltage shift. In the range of submicrometer channel length, the assumption of the constant surface potential of the charge–sharing model is invalid. In a paper. 8.

(32) by Woo et al. [29], the work was done by the decomposition of the 2–D Poisson’s equation into a 1–D Poisson’s equation and a 2–D Laplace equation. In a paper by Guo and Wu [30], an accurate 2–D analytical threshold voltage model was developed by means of a three–zone Green’s function solution technique. Although a closed form of the threshold voltage is derived, the calculation is too complicated to be further implemented in the derivation of the I–V model for a simulator like SPICE. Therefore, to consider an efficient computation, the simplified and explicit expression of the threshold voltage of the FD SOI MOS transistor is necessary. In this chapter, in order to derive the threshold voltage model, the three–zone Green’s function technique [30] is used to solve the 2–D Poisson’s equation. Based on the concept of the average vertical electric field, a simple and closed expression of the threshold voltage is obtained and described in Section 2–2. Comparisons between the 2–D numerical analysis (Medici program), experiments and the proposed analytical threshold voltage model are shown in Section 2–3. Finally, the conclusions are summarized in Section 2–4.. 2–2 Derivation of the Analytical Threshold Voltage Model 2–2.1 Basic Analysis. The conventional structure of a FD SOI MOS transistor for 2–D numerical simulation is presented in Figure 2–1. A simplified domain has been used for solving the 2–D Poisson’s equation and indicated by the bolded lines in Figure 2–1. The domain for solving 2–D Poisson’s equation is further divided into three sub–domains (Zones I, II and III) to avoid the complexity of calculating the equivalent charge density between the regions with different dielectrics. Zone I is the front gate oxide, zone II represents the Si film and zone III is the buried oxide. The boundary conditions used for each zone are enumerated in Table 1. It should be noted that the boundary potential in the y direction in the zones I and III are assumed to vary linearly [29]. Based on the assumption that the front gate oxide and buried oxide well grown and there is no 9.

(33) charge reside. The 2–D Poisson’s equations in the zones I and III can be reduced to two 2–D Laplace equations. Substituting the Green’s function solutions, listed in Table 2, into the Green’s theorem [31], which is given as. ρ (x ' , y ' ) ⋅ G (x, y : x ' , y ' )⋅ dx ' dy ' ε ∂G ∂φ + ∫ G (x, y : x ' , y ' ) ' ds ' − ∫ φ (x ' , y ' ) ' ds '. φ (x, y ) = ∫∫. ∂n. ∂n. (2–1). where G (x, y : x ' , y ' ) is the Green’s function satisfying ∇ 2 G = −δ (x − x ' )δ ( y − y ' ) ; n ' is the outward normal direction on the boundary surface, and neglecting the free carriers, the general form of the 2–D potential distribution in each zone can be obtained as follows [30]: ∞ D m sinh k (t 4Vgs' cosh k m y sf m fox + y ) φ ( x, y ) = ∑ sin k m x − ∑ sin k m x k m cosh k m t fox m =odd mπ cosh k m t fox m =1 ε ox ∞. I. [. ]. cos k nI y ⋅ AnS sinh k nI (L − x ) + AnD sinh k nI x , I n =1 sin k n L ∞. +∑. φ II ( x, y ) =. (2–2). ∞ QB0 Q n cos k nII y ⎡ sinh k nII x + sinh k nII (L − x ) ⎤ x (L − x ) + ∑ B ⋅ ⎢1 − ⎥ 2 2ε si sinh k nII L n =1 ε si k nII ⎦ ⎣. ( ). [. ∞ cos k nII y ⎛ x⎞ D x + B ⎜1 − ⎟ + B0 + ∑ ⋅ BnS sinh k nII (L − x ) + BnD sinh k nII x II L n=1 sinh k n L ⎝ L⎠ ∞ sin k m x +∑ ⋅ Dsfm cosh k m (t si − y ) − Dsbm cosh k m y , m =1 ε si k m sinh k m t si S 0. [. φ III ( x, y ) =. ]. ]. (2–3). ∞ 4Vbs' cosh k m ( y − t si ) Dsbm sinh k m (t box + t si − y ) sin k x sin k m x + ∑ ∑ m cosh k m t box k m cosh k m t box m =odd mπ m =1 ε ox ∞. cos k nIII ( y − t si ) S +∑ ⋅ C n sinh k nIII (L − x ) + C nD sinh k nIII x . III sin k n L n =1 ∞. [. ]. (2–4). where the definitions of the Fourier coefficients Ans , And , B0S , B0D , BnS , BnD , C nS , C nD , Dsfm , Dsbm , QB0 and QBn are given in the Nomenclature. In order to obtain the 2–D analytical solution of the potential distribution at the zone II, Dsfm and Dsbm have to be solved first. Dsfm and Dsbm can 10.

(34) be obtained by equating equations (2–2) and (2–3) at y = 0 and equations (2–3) and (2–4) at y = tsi, respectively. The related expressions are given in Table 3 for details. It should be noted that the above equations are exact in the sense that any arbitrary doping profile in the Si film can be treated. In the following analysis, the uniformly doped Si film is assumed for simplicity. Therefore, the 2–D potential distribution at the zone II can be further repressed as follows [30]:. φ II ( x, y ) = −. [. ∞ sin k m x qN B x(L − x ) + ∑ ⋅ Dsfm cosh k m (t si − y ) − Dsbm cosh k m y 2ε si m =1 ε si k m sinh k m t si. + Vbi +. x ⋅ Vds . L. ] (2–5). 2–2.2 A New Approach for the Development of the Threshold Voltage Model. Since the FD SOI MOS transistor under consideration is normally–off type (enhancement mode), the front surface potential distribution of the Si film is usually used to monitor the turn–on status of FD–SOI MOSFETs. From equation (2–5), the potential distribution along the front surface of the Si film can be derived as:. φ II ( x,0 ) = −. [. ]. ∞ sin k m x qN B x x (L − x ) + ∑ ⋅ Dsfm cosh k m t si − Dsbm + Vbi + ⋅ Vds . 2ε si L m =1 ε si k m sinh k m t si (2–6). The accuracy of the derived front surface potential distribution in the Si film has been verified by the 2–D numerical analysis as shown in [30]. In the paper by Guo [30], to develop an analytical threshold voltage model, the minimum potential along the front surface of the Si film has to be calculated first. By differentiating the equation (2–6), the position of the minimum potential along the front surface of the Si film can be calculated. ∂φ II ( x,0 ) ∂x x= x. =. ∂φ sfII ( x ). mim. ∂x. = 0, x = xmim. (2–7). where xmin is the position of the minimum surface potential and φ sfII ( x ) represents the potential. 11.

(35) distribution along the front surface of the Si film. By introducing the value of xmin into equation (2–6), the minimum surface potential φ sfII ,min can be obtained. However, the position of the minimum surface potential xmin can be only solved iteratively and no explicit form of xmin can be obtained. Therefore, the calculation of the minimum front surface potential is too complicated to be further implemented in the derivations of the analytical I–V model for a circuit simulator like SPICE. The new approach for the development of the threshold voltage model is described in the following. Firstly, by differentiating equation (2–3) with respect to y, the normal electric field along the front Si film surface can be obtained and expressed as: E sf ( x ) = −. ∞ D ∂φ II ( x, y ) sf =∑ sin k m x. ∂y ε = m 1 si y =0 m. (2–8). Then, by integrating equation (2–8) with respect to x from x = 0 to x = L, the total charge density controlled by the front gate can be obtained and expressed as: ∞. Dsfm. m =1. km. Q fg = − ∫ ε si Esf ( x ) ⋅ dx = −∑ L. 0. [1 − (−1) ]. m. (2–9). By applying Gauss’s law at the front SiO2–Si interface, we obtain. E sf ( x ) =. (. ).. C fox Vgs − VFBf − φ sfII ( x ). ε si. (2–10). From equation (2–10), the threshold voltage can be obtained as:. VTH = VFBf + φ f ,inv +. ε si E sf (xmin ) C fox. ,. where the threshold voltage is defined as the value of gate voltage Vgs. (2–11) for which. φ sfII ,min = φ f ,inv = 2φ fp . However, the derivation of the equation (2–11) is still complicated and computationally inefficient due to the calculation of xmin . Therefore, in this work, the average. 12.

(36) normal electric field along the front surface of the Si film E sf is used to substitute the E sf ( xmin ) . From equation (2–9), E sf can be obtained and expressed as: ∞. E sf = ∑ m =1. Dsfm. ε si k m. [1 − (− 1) ]. L m. (2–12). Then, the threshold voltage can be redefined as:. VTH = VFBf + φ f ,inv +. ε si E sf C fox. .. (2–13). Due to the effect of the lateral electric field originating from the source/drain junctions, the average normal electric filed along the front surface of the Si film is expected to be smaller than the normal electric filed at the position of minimum potential. Therefore, in order to compensate the error results from the charge–sharing effect, a modification to the equation (2–13) is necessary. Figure 2–2 shows the normal electric field along the front SiO2–Si interface of the FD SOI MOSFETs, where the case of the average surface normal electric field is shown in (a) and the case of the surface normal electric field accounting for the charge–sharing effect is shown in (b). In Figure 2–2(a), the total depletion charges Qdepl ,1 in the Si film that terminate the average surface normal electric field originating from the gate can be expressed as:. Qdepl ,1 = ε si E sf ⋅ W ⋅ L ⋅ t si .. (2–14). The charge–sharing effect is due to the loss of the control ability of the gate to the depletion charge under it. In other words, the depletion charge controlled by the gate is no longer equal to Qdepl ,bulk ( Qdepl ,bulk = qN B y d max , for bulk MOSFETs, where y d max is the maximum depletion width of the depletion region under the gate), but to a fraction of it. The reduction of the depletion charge is due to the presences of the source/drain junctions and the surface normal electric field is disturbed by the lateral electric field originating from the source/drain junctions, as shown in Figure 2–2(b). According to the charge–sharing scheme shown in Figure 2–2(b), the effective depletion charge controlled by the gate can be obtained as: 13.

(37) L t Qdepl , 2 = W ⋅ ⎛⎜ ∫ ε si E sf ( x ) ⋅ dx ⎞⎟ ⋅ si (2 L − ∆L1 − ∆L2 ) 0 ⎠ 2 ⎝ t = W ⋅ Q fg ⋅ si (2 L − ∆L1 − ∆L2 ) 2. (2–15). where ⎡ 2ε si (Vbi − φ f ,inv )⎤ 2 ∆L1 ≈ Ws = ⎢ ⎥ , qN B ⎣ ⎦ 1. ⎡ 2ε si (Vbi + Vds − φ f ,inv )⎤ 2 ∆L2 ≈ Wd = ⎢ ⎥ . qN B ⎣ ⎦ are the depletion widths of the source– and drain–substrate junctions at the 1. where Ws and Wd surface.. By equating equations (2–14) and (2–15), the relationship between Q fg and E sf can be obtained as. Q fg = ε si Esf ⋅ β . (2–16). where −1. 2L ⎧ ∆L + ∆L2 ⎫ = ⎨1 − 1 β= ⎬ . 2 L − ∆L1 − ∆L2 ⎩ 2L ⎭ Therefore, in order to compensate the errors caused by the charge–sharing effect, we add the modified factor β into equation (2–13) and obtain the final expression of the analytical threshold voltage model:. VTH = VFBf + φ f ,inv +. ε si Esf C fox. ⋅ β. (2–17). After some mathematical manipulations, the equation (2–17) can be further expressed in terms of the terminal voltage as: ⎧⎪ ε β VTH = VFBf + X ⋅ ⎨φ f ,inv + si C fox ⎪⎩ ⎧⎪ ε β X = ⎨1 − si ⎪⎩ C fox. ∞. [. ∞. 1. ∑d m =1. 1 m m Fg 1 − (− 1) ∑ m d m =1 0. m 0. ]. [1 − (− 1) ](G m. −1. ⎫⎪ ⎬ . ⎪⎭. 14. m. ⎫⎪ + FbmVbs' + γFdmVds ⎬, ⎪⎭. ).

(38) (2–18) where the coefficients G m , Fbm , Fdm and Fgm are listed in Table 4 for details and γ is an empirical constant assumed to account for the errors resulting from the drain–induced barrier lowering effect.. 2–3 Verifications and Discussion. In order to verify the accuracy of the derived equations, the analytical model of the VTH , given in the equation (2–18), has been compared with the results obtained by the 2–D numerical device simulator Medici [32] and experimental data [33]. The threshold voltages of the results obtained by the 2–D numerical simulator are defined by the relationship between the drain current and external gate–source voltage as follows. In general, the drain current in the non–saturation region can be expressed as. I DS =. Weff C fox µ eff ⎛ 1 ⎞ ⎜VGS − VTH − VDS ⎟ ⋅ VDS . Leff 2 ⎝ ⎠. (2–19). For the long channel length devices operating at low VDS (e.g., VDS = 50 mV), using the extrapolation method on the I DS – VGS curve at VGS equal to the voltage at which the maximum dI DS dVGS occurs, the threshold voltage can be obtained by the intercept on the VGS –axis.. Additionally, when VGS. 1 (2–20) VTH = VGS ,int ercept − VDS . 2 = VTH , the normalized drain current is defined as a reference current.. I reference = I DS ,normalized = where I reference is the reference current, I DS ,normalized. Leff. I DS ,longL. (2–21). Weff is the normalized drain current and I DS ,longL is. the drain current of the long channel device. When the channel length is very short, the maximum transconductance extrapolation method would fail due to the significant short channel effect. Thus, the threshold voltage of the short channel device is extracted by equating the normalized drain current to the reference current, which is determined by the long channel device. For high VDS 15.

(39) operation, VTH is extracted from the parallel shift of ln(I DS ) versus VGS in the subthreshold region, as mentioned in [33]. The comparisons of the threshold voltage versus effective channel length of the fully depleted SOI MOSFET’s with 11 nm front gate oxide, 330 nm buried oxide and 1×1017 cm −3 bulk doping concentration for different Si film thicknesses are shown in Figure 2–3 when VDS = 0.05V and VBS = 0V . In this figure, it is expected to see that the roll–off of the threshold voltage is severer in the case of thicker Si film due to the short channel effect. In other words, the VTH roll–off starts to occur at larger gate lengths in the MOS transistors with thicker Si film thicknesses. Additionally, it is clearly seen that the calculated results using the present model agree very well with the 2–D numerical analysis. Figure 2–4 shows the comparisons of the threshold voltage versus effective channel length for the devices of 70 nm Si film, 330 nm. buried oxide and 1×1017 cm −3 bulk doping. concentration with front gate oxide as the parameter. From this figure, it is seen that the devices with thinner front gate oxides can significantly retard the roll–off of the VTH as the channel length getting shorter. This is because that with thinner front gate oxide, the ability of control of the gate to the depletion region under it becomes better. It is also seen that a good agreement is obtained between the simulated results and 2–D numerical analysis. Figures 2–5 and 2–6 compare the roll–off of the threshold voltages for different back gate voltages with 2–D numerical analysis and experimental data. As can be seen, the present model correctly predicts the VTH roll–off for different back gate biases. Figure 2–7 shows the effect of the drain voltage on the roll–off of the threshold voltage of the devices with 1.6 nm front gate oxide, 400 nm buried oxide, 21 nm Si film and 1.5 × 1018 cm −3 bulk doping concentration. It is. expected to see that at larger drain bias, the encroachment field from the drain becomes more significant, especially at small channel length. From this figure, the accurate predictions of the severe threshold voltage roll–off by the proposed model are obtained, even for the devices with 0.07 µm channel length. Figure 2–8 shows the comparisons of the threshold voltages obtained by 16.

(40) the present model with the experimental data for the devices biased at different drain voltages. In this figure, it is seen that a good agreement is obtained between the simulated results and the experimental data. Eventually, the present model is compared with the numerical data used in [30] (Figs. 5–7) and the compared results are shown in Figure 2–9. From the figure, it is seen that a good agreement is obtained and evaluates the validity of the modified model.. 2–4 Conclusions. In this chapter, we propose an analytical threshold voltage model for deep–submicrometer FD SOI MOSFET’s using three–zone Green’s function technique to solve the 2–D Poisson’s equation and adopting a new concept of the average electric field to avoid the iterations in solving the position of the minimum surface potential. Firstly, we obtain the 2–D potential distribution in the Si film region by using Green’s function technique to solve the 2–D Poisson’s equation. By applying Gauss’s law at the Si–SiO2 interface, the initial expression of the threshold voltage is obtained. Then, we introduce a modified factor to compensate the errors resulting from the charge–sharing effect in the derivations of the final threshold voltage model. The proposed model is validated against the data obtained from 2–D numerical analysis and experimental data and excellent agreements are obtained. From the above discussion, it can be seen that the present model predicts the threshold voltage well and has no iteration problem in the calculation that exists in the previous work [30].. 17.

(41) Chapter 3 A New Analytical I–V Model for Fully–Depleted Short–Channel SOI MOSFETs 3–1 Introduction. Fully–depleted silicon–on–insulator (FD SOI) MOSFET’s are considered as the possible successors for the bulk MOSFET’s in the applications of low power and high speed circuit designs, as they offer various attractive characteristics such as suppressed short channel effects, reduced junction capacitance, excellent latchup immunity and improved subthreshold swing [15, 17, 19 and 20]]. As a consequence, the SOI circuit design and device simulation are getting increasingly important in the deep submicrometer range of the VLSI technology. Therefore, for the reliable analysis and design of the SOI circuits, accurate and physically based I–V models are needed. As the channel length of the SOI MOS transistor scales down, the effect of the threshold voltage roll–off due to the charge sharing and drain–induced barrier–lowering effects (DIBL) should be taken into account. Besides, due to the low thermal conductivity of the buried oxide, which inhibits the efficient cooling of the active devices, a significant self–heating effect (SHE) of the silicon film [34] arose and should be also considered. The increasing lattice temperature may cause a reduced drain current and even a negative differential conductance at high power inputs [35]. Additionally, as the devices biased at high current level, the parasitic source/drain resistances and impact ionization effect are noticeable and should be accounted for, especially in the saturation region and small gate voltage. Several analytical I–V models for thin–film SOI MOSFETs had been developed in [29, 36–38]. The 2–D analysis of the conduction channel by Woo et al. [29] calculated the channel current by assuming a linearly varied channel surface potential. This assumption would cause a significant error in the prediction of the threshold voltage, especially when the drain bias is large. In a paper by 18.

(42) Hsiao et al. [36], the source/drain series resistances and the effect of the drain induced conductivity enhancement were considered. However, this model may have error in the prediction of the high current level due to the exclusion of the effects of the impact ionization effect and self–heating. In the paper by Hu et al. [37], the above effects mentioned were included in the I–V model derivation, but an additional smooth function was needed to make a smooth transition for VDS between linear and saturation regions. In a paper by Iniguez et al. [38], they improved the continuity through the transition regions based on the charge sheet model, but lacked the effects of self–heating and parasitic series resistances. In this chapter, the model derivations are described in Section 3–2. The simplified analytical threshold voltage model developed in the previous chapter is utilized and it is linearized to obtain the DIBL factor in Section 3–2.1 that is incorporated in the derivations of the analytical I–V model. Then, a complete analytical drain current model for the deep submicrometer SOI MOSFETs is presented in Section 3–2.2 to account for the effects of the parasitic series resistances, drain–induced barrier–lowering, channel length modulation, impact ionization and parasitic bipolar junction transistor. The temperature rise model and temperature dependent parameters are described in Section 3–2.3. The comparisons with the measured data and 2–D numerical simulations for devices with a wide range of parameters in all regions of device operation are presented in Section 3–3. Conclusions are given in the final section.. 3–2 Model Derivations 3–2.1 Analytical Threshold Voltage Model. It is known that the drain–induced barrier–lowering effect has great influences on the I–V characteristics of MOSFETs in both the below– and above–threshold operation regions when the channel lengths of MOS devices become very short. It is beneficial for the designers to predict the device I–V characteristic accurately and efficiently if these short channel effects are well described 19.

(43) and modelled as a simple analytical expression. To simply the derivation of an analytical I–V model, a DIBL factor is introduced to account for the drain bias effect by a linearization of the threshold voltage with respect to the drain bias at very small drain voltage. The DIBL factor can also be incorporated into the electron mobility model. Based on the simplified 2–D threshold voltage model developed in Chapter 2, an analytical I–V model is derived for fully–depleted SOI MOSFETs. The threshold voltage model can be rewritten as:. φ f ,inv + VTH = VFBf +. ε si β 0 C fox. ∞. 1. ∑d m =1. 1−. [1 − (− 1) ](G m. m 0. ε si β C fox. ∞. [. m. + FbmVbs' + γFdmVds. 1 m m Fg 1 − (− 1) ∑ m d m =1 0. ]. ) ,. (3–1). Differentiating eq. (3–1) with respect to drain bias at very low drain voltage, the DIBL factor K can be obtained by taking the negative derivative:. ε si β 0 ' C fox ⎛ dV ⎞ = (− 1) ⋅ K = −⎜⎜ TH ⎟⎟ ⎝ dVds ⎠Vds =0. ⎛ ε si β 0 ' ⎞ ε ⋅ M 3 ⎟ + si M 0 ⋅ (M 1 + φ f ,inv ⋅ M 3 ) M 2 ⋅ ⎜1 − ⎜ ⎟ C C fox fox ⎝ ⎠ , 2 ' ⎛ ε si β 0 ⎞ ⎜1 − M3 ⎟ ⎜ ⎟ C fox ⎝ ⎠. −2. ε si. ⎛ ∆L1 ⎞ ⎛ 2Ws M0 = ⎜1 − ⎟ ⋅ ⎜1 + L ⎠ ⎜⎝ t si 2qN BWs L ⎝ ∞ 1 m M 1 = ∑ m G m + FbmVbs' 1 − (− 1) m =0 d 0. )[. (. [. ∞. 1 γFdm 1 − (− 1)m m m =0 d 0. M2 = ∑ ∞. [. 1 m m Fg 1 − (− 1) m m =0 d 0. M3 = ∑. ⎛ ∆L ⎞ β 0 = ⎜1 − 1 ⎟ L ⎠ ⎝. ]. ⎞ ⎟⎟ ⎠. −1. 2. ]. ]. −1. '. (3–2). Then the threshold voltage of a fully depleted thin film SOI MOSFET can be rewritten as:. VTH = VTH 0 − K ⋅ Vds ,. (3–3). where VTH0 is the threshold voltage of the SOI MOSFET at zero drain bias and is expressed as: 20.

(44) φ f ,inv + VTH 0 = V. f FB. +. ε si β 0 C 1−. ∞. 1. ∑d. m fox m =1 0 ∞ si 0. ε β. C fox. [1 − (− 1) ](G m. [. m. + FbmVbs'. 1 m m Fg 1 − (− 1) ∑ m m =1 d 0. ]. ) .. (3–4). 3–2.2 Analytical I–V model 3–2.2.1 I–V Characteristics in Linear Region (Vgs > VTH, VDS < VDSAT). It is known that the conduction current in the above–threshold region is contributed by the drift motion of the inversion carriers. When the drain voltage is smaller than the drain saturation voltage, the MOS transistor is operated in the linear region and the drive current can be expressed as [39]:. I DS =. W W 1 ⎞ 1 ⎤ ⎛ ⎡ µ eff C fox ⎜V gs − VTH − Vds ⎟ ⋅ Vds = µ eff C fox ⎢V gs − (VTH 0 + KVds ) − Vds ⎥ ⋅ Vds L L 2 ⎠ 2 ⎦ ⎝ ⎣. (3–5). where VTH is the threshold voltage derived in the previous section and is a function of the drain bias, and µeff is the effective mobility and expressed as [40]:. µ eff = 1+. αC fox 2ε si. µn. 1 ⎤ ⎛ β⎞ ⎡ f 2 φ η V V V V + + + − + − ⎟ ⋅Vds ⎜ gs TH FB f , inv ds ⎢⎣ L⎠ 2 ⎥⎦ ⎝. (. ). (3–6). where µn is the maximum low filed mobility in the inversion layer, and the constant α (β, η) is the transverse (longitudinal) electric field degradation factor in the mobility model. Considering the parasitic source and drain resistances RS and RD, the intrinsic gate– and drain–to–source voltages Vgs and Vds can be written in terms of the terminal voltages:. Vgs = VGS − I DS ⋅ RS. Vds = VDS − I DS ⋅ (RS + RD ) 21. (3–7).