5–2. Approaches and Assumptions

To accurately describe the fact that the signal travels across the gate in the form of incident and refle

on remains the same along the gate width.

rim ete

(5–1) network, substrate parasitics and nonreciprocal capacitance is proposed. At first, the relative approaches and assumptions are briefly described and defined, respectively. Then, the derivation details of model equations will be described.

1

cted EM waves [74], we use the concept of transmission line theorem to model the distributed nature of the gate region and the delay it causes in charging the gate capacitance. In addition, for the sake of simplicity and calculation efficiency, we add a lumped resistance to the bulk terminal to account for the substrate coupling effect. We also use the nonreciprocal capacitance to take into account the different effects of the gate and drain on each other in terms of charging currents [80].

In order to describe the distributed nature of the gate region, a MOS transistor is viewed as an array of discrete transistors connected in parallel via gate resistances along the gate region, as illustrated in Fig. 5–1. The related small signal equivalent circuit is shown in Fig. 5–2 which is based on the three–terminal configuration. In a three–terminal configuration, the substrate is tied to the source, as in most high frequency applications [73] and [83]. This model is suitable for the case of zero source–substrate bias in circuit. Before developing expressions for the Y–parameters of the MOS transistors, the following assumptions have to be made:

1) Assumption 1: It is assumed that the DC bias conditi

This means that only AC small signals applied at the gate region needed to be considered. With this assumption, the discrete MOS transistors illustrated in Fig. 5–1 have the same small signal parameters (e.g., transconductance g ; drain–bulk transconductance _m g , etc.). To make the _mb model equations clearly, we use the p e–notation to stand for the param rs per width (i.e., X^’ is used to represent the variable X per unit width).

W R_g R_g^'

=

(5–2) W

C_gd^'

=

C^gd

(5–3) W

=

C C_gs' ^gs

(5–4) g_m^'

=

^gm_W where W is the channel width, R is the gate resistance, _g C and _gd C are the gate–to–drain _gs

tion 2: This assumption states that the electric field along the width of the device is

In order to develop an analytical model easily, the average voltage at the gate

(5–5)

here

capacitance and gate–to–source capacitance, respectively, an g is_mb e transconductance of substrate.

2) Assump

d th

significantly less than the fields existing along the channel length. Note that this condition is valid in most devices used for RF applications where the gate width W is normally larger with respect to the gate length L.

3) Assumption 3:

region is expressed as:

w v is the average voltage at the gate region, and is the voltage at the location x along

(5–6)

–2.2 Analysis for New RF MOSFET Model

In the primary step, we will decouple the feedback loops and find the loadings caused by the feed

5–2 is too complicated to be analyzed directly.

) (x v

the gate region. Thus, the total current flowing in the channel can be expressed as:

. ) 1 (

∫

0 ^⋅

= ^Wv x dx v W

. )

0

(

∫

'

^{⋅ ⋅}

=

^W _m

mv g v x dx

g

5

back networks at the input and output terminals. Then, the derivation of Y–parameters of MOSFETs will be expressed in the secondary step.

1) Step 1: The circuit configuration shown in Fig.

Nevertheless, if the circuit is viewed as a dual–feedback circuit in which

∆

C_gd is the local

shunt–shunt feedback element forms the first feedback loop (i.e., loop A), where C^' x represents the gate–drain capacitance of the section ∆x at the gate region, and C , _db

x

C_gb^'

⋅ ∆

are the local shunt–shunt feedback elements form the second feedback loop (i.e., loop B), x

C

C ^' represents the gate–substrate capacitance of the section ∆x at the gate region, becomes much easier to solve. The feedback loops A and B are illustrated in Fig. 5–3, where V

C_gd

=

_gd

⋅ ∆

∆

C , sb R and_sub

then the circuit

(5–7)

(5–11)

(5–12)

tr e a substrate capacitance, respectively

Th al s nt– eed ck theory mentioned above, the circuit in Fig. 5–2 can where

∆

_gb

=

_gb

⋅ ∆

1 and V2 represent the output voltage relative to ground (e.g., Vds) and the voltage along the gate width shown in Fig. 5–2, respectively. By local shunt–shunt feedback theory [84], the loading effects at the input and output terminals caused by the feedback networks shown in Fig. 5–3 can be expressed in the Y–parameter representation as follows.

Y_11,loopA

=

sC_gd

where, C , _db C and_sb C _gb are the drain–to–subs at cap citance, source–to–substrate capacitance

and gate– – , ^' and ^' are the gate–to–drain capacitance

per unit width and gate–to–substrate capacitance per unit width, R is the substrate resistance, _sub and C is the sum of _b C , _gb C and _db C . _sb

be tr

compo nts and presse

(5–13)

(5–16)

here ∆x is an infinitesimal section of the gate width.

eters, the complete small–signal equivalent

(5–17)

(5–18)

hich are subject to the boundary conditions

ansformed into the one in Fig. 5–4. In Fig. 5–4, some components (i.e., Y_{12 loopA}^'_, , Y_{21 loopA}^'_, ,

3) Step 2: In the derivation procedure of Y–param

circuit of Fig. 5–4 is analyzed as a two–port circuit with input at the gate and output at the drain and both the source and substrate terminals are grounded. Then, due to the distributed RC network along the gate region, the equivalent circuit can be analyzed by transmission line theory.

Along the gate width, we have the transmission line equations in frequency domain as follows:

(5–19)

hen, according to th ters of the equivalent small signal

(5–25)

the average voltage at the gate region and total current in the channel can be expressed as:

(5–24)

T e two–port circuit model, the Y–parame circuit can be solved as follows:

(

^' ₂₂^'_{, 22}^' _,

)

^'

(

^{' ' '}

)

^{' '} The above result clearly indicates that three coupling path influence the in a . They are the ways from gate to source, gate to drain and gate to substrate through C_gs, C_gd a d

, respectively. Then, the parameter can be expressed as:

Y11

Cgb Y₁₂

o

here is the transcapacitance (i.e.,

( )

( )

(5–26) Equation (5–26) provides useful insight on the coupling paths of drain voltage to gate current. Tw terms (term M and term N) in equation (5–26) describe the paths. Term M: the voltage applied to the drain couples to the distributed gate region through C . Term N: the drain voltage couples to _gd

the distributed substrate region and makes current flow through C into gate region. In addition, _gb the parameter Y₂₁ can be expressed as:

Similar the signal coupling paths are d e term pressed in equation (5–27). Term O: the voltage applied to the gate makes the current flowing in the channel, but due to the existence of C , the current flowing from the drain end must subtract the current flowing through _gd C _gd

from ate region. Term P: the gate voltage makes current flow through C and voltage d_gb across R , _sub v , which is multiplied by _bs g to make current flowing into the channel. Term Q: _mb the gate voltage makes the current flow through C and voltage drop on _gb R , _sub v , which makes _bs current flowing through C into the drain en in the opposite direct_db of . Finally, the

g rop

( ) ( ) ^{( ) ( )}

(5–28) here is the conductance of drain–to–source. In equation (5–28), four terms describe the

e

在文檔中 完全空乏型單晶矽在絕緣層上之短通道金氧半場效電晶體的二維分析及新解析模式 (頁 76-82)