Since mid–1960s, the Metal–Oxide–Semiconductor Field Effect Transistor (MOSFET) has been treated as the most important electronic device, superseding the Bipolar Junction Transistor (BJT) and initiating a revolution in the Integrated Circuit (IC) industry. According to the statistics, more than 95% of the available microelectronic products are fabricated by the silicon–based technology, among which the bulk–MOS device stands for the most pronounced branch. Nowadays, it has invaded our daily lives by the magic power derived from its simple structure and low fabrication cost. For these reasons, the MOS technologies, especially the Complementary Metal–Oxide–Semiconductor (CMOS), are taken as the major trend for Ultra–Large–Scale–Integration (ULSI) circuit and mass–production product. Other than the compact density, the figures of merit for IC performance also include high speed and low power consumption. In order to increase the packing density and to improve the circuit performance, the geometries of the bulk–MOS device have been continually scaled down [1]–[5]. However, as the bulk–MOS devices shrink to deep–submicrometer regime, several problems such as gate oxide reliability, shallow junction, parasitic capacitance, device isolation and radiation/plasma damage occur, and those limit the further scaling of the bulk–MOS devices [6]–[8]. Therefore, many manufacture techniques have been found to reduce the effects of these problems such as making shallow junction with raised source/drain regions, using deep trench isolation or epitaxial substrate to prevent the occurrence of the latchup, reduce the junction capacitance with Silicon–On–Insulator (SOI) technique, etc [9]–[11]. Among these techniques, the SOI CMOS technique is the most attractive one because it involves less processing steps than the bulk CMOS technique, and suppresses some yield hazard factors present in bulk CMOS.
Recently, the SOI MOSFETs have drawn much attention for its advantages over bulk MOSFETs such as elimination of latch–up problem, excellent device isolation, reduced junction capacitances and improved radiation hardness. The advantages of the SOI MOSFETs are discussed and described as follows.
a) Elimination of latch–up effect
In the bulk CMOS technique, the latch–up effect is originated from the parasitic PNP (NPN) structure residing in the CMOS circuit. The latch–up path can be represented by two bipolar transistors (Q1 and Q2) and parasitic resistances (Rs and Rw), as shown in Fig. 1–1(a) and (b). The latch–up can be triggered by several different mechanisms, such as junction avalanche, voltage overshoot and displacement current [10]. The necessary condition for the occurrence of latch–up is that the current gain of the loop formed by these two bipolar transistors is larger than unity.
However, in the SOI CMOS circuit, e.g., inverter, due to the existence of the high dielectric isolation between the active regions and substrate, the latch–up path is ruled out because no current path to the substrate exists, as shown in Fig. 1–1(c).
b) Reduced parasitic capacitances
In the bulk MOSFETs, the parasitic junction capacitances, i.e., source–to–substrate and drain–to–substrate capacitances, which consist of two components: the capacitance between the source/drain and the substrate regions in the vertical direction, and the capacitance between the source/drain and the channel regions in the lateral direction, as shown in Fig. 1–2(a). These capacitances may increase with the substrate doping concentrations as the devices are shrunk to smaller geometries. However, in SOI MOSFETs, the junction capacitance in the vertical direction is replaced by the capacitance of buried oxide that is typically lower than the junction capacitance in bulk MOSFETs, as shown in Fig. 1–2(b). The reduced parasitic capacitance properties of the SOI MOSFETs make them very suitable for high–speed applications such as RF IC’s and
telecommunication.
c) Excellent radiation hardness
Figure 1–3 shows the radiation effects on bulk and SOI MOSFET. From the figure, it is seen that the radiation effects are different for bulk and SOI MOSFETs. In general, when the MOSFETs are exposed in the radiation environment, the silicon volume would absorb the energy of radiation and subsequently the electron–hole pairs would be generated [12]. The radiation–induced electron–hole pairs may be collected by the source/drain junctions and contribute to the leakage current, and consequently soft–error may occurs. For SOI MOS devices, due to that the active region is isolated from the substrate, the radiation–induced electron–hole pairs generated in the substrate would not influence the device performance. Besides, due to that the volume of the active region above the buried oxide for absorbing the radiation energy, and the source/drain junction areas for collecting the radiation–induced electron–hole pairs are very small, the probability of occurring the soft–error for the SOI circuit is much reduced.
d) Simple IC processing
Although the process techniques for the fabrication of CMOS circuit in bulk silicon wafer and in SOI wafer are very similar, the SOI fabrication process is simpler than bulk one. Firstly, there is no need to do the essential well implantation (even twin well), which is a necessary in the bulk CMOS process, in the SOI CMOS process. Besides, the guard–ring structure in the bulk CMOS circuit to suppress the latch–up problem is also unnecessary in SOI CMOS process. Secondly, due to the presence of the buried oxide film underneath the active region, the SOI isolation process is more effective in the isolating the active islands from one another. Thirdly, the source/drain shallow junctions are essential in the deep–submicrometer regime to ensure the less short–channel effects, but it is a difficult task for the bulk CMOS process. In the shallow junction processing, a harmful spiking effect may take place between the silicon substrate and metal conductor through the
source/drain junctions, as shown in Fig. 1–4. Such a junction punch–through may give rise to the uncontrolled leakage current. However, the source/drain junctions can be extended to the buried oxide in the SOI CMOS process, and hence the shallow junctions could be obtained.
e) High integration density
Generally speaking, the SOI CMOS circuit can offer a higher integration density than bulk CMOS circuit. This can be observed from the layouts of the bulk CMOS inverter and SOI COMOS inverter shown in Fig. 1–5. It is seen that the area of the SOI CMOS inverter is smaller than that of the bulk CMOS inverter. This happens due to the following reasons. The major reason is the absence of the well in SOI CMOS, and consequently the number of the well contact is decreased.
The second reason is that the possibility of having a direct contact between the P+ and N+ junctions, such as the drain regions of the p–channel and n–channel devices shown in Fig. 1–5. Moreover, the removal of the guard–ring structure could also increase the integration density.
Depending on the relation of the thickness of silicon film to the maximum depletion width while the SOI MOSFET is turned on, two types of SOI MOS devices can be distinguished. One is the Fully–Depleted (FD) SOI MOSFET, where the silicon film is completely depleted, and the other one is the Partially–Depleted (PD) SOI MOSFET, where a neutral region exists other than the depleted region. Except for the advantages of the SOI CMOS technique mentioned above, there are two unique features of SOI MOSFETs needed to be considered and described in the following.
1) Floating–body effect: The most prominent electrical property of the PD–SOI device is that the body is floating, and subsequently the body voltage would vary during switching. The variation of the floating body potential may cause the threshold voltage vary, and consequently the I–V characteristics of the PD–SOI devices are no longer constant. The voltage of the floating body is dependent on the amount of charge contained in the body of the device at any given time. The charge content of the body, and the distribution of the charge are determined by the p–n junction leakage currents, the impact ionization current, and the capacitive coupling from the external
terminals during operation transitions. The variation of the threshold voltage resulting from the content of the charge in the body may cause a “kink effect” in the I–V characteristics of the devices [13]. However, the kink effect is undesirable for analog circuit because of the lower output resistance. Furthermore, due to the parasitic bipolar transistor presented in the SOI MOSFETs, the floating body effect may cause the reduction of the drain–source breakdown voltage. The classical remedy to the floating body problem is the use of a body contact. On the other hand, for the FD–SOI MOSFETs, due to the completely depleted region in the silicon film, the charge storage in not observe. Therefore, to understand, characterize and model the floating–body effect is essential in SOI CMOS technique.
2) Self–heating effect: Due to the presence of the buried oxide film beneath the device active region, SOI CMOS technique owns several advantages over the bulk CMOS one as mentioned in previous subsections. However, the low thermal conductivity of the buried oxide reduces the efficiency in removing the generated heat. In bulk technologies, heat generated by the charge transfer in the device can be readily removed out of the chip backside through the crystalline silicon substrate. The removal of the heat is quick enough that the local device performance change due to the self–heating is negligible. On the other hand, in SOI technique, it seems that the MOS device is encased in a perfect insulated region of its own, with inter–layer dielectric above, shallow trench isolation dielectric to the left and right sides, and buried oxide film underneath. As a result, the heat generated by the charge transfer is hard to be removed out through these dielectric films, and consequently an elevated device temperature is observed [14].
This phenomena is so–called Self–Heating Effect (SHE). The temperature increase induced by the SHE may give rise to some parameter variations such as carrier mobility and threshold voltage, and the further influence on the device performance. It must be emphasized that these effects would take place as the heat is dissipated into the device. In reality, in an operating digital CMOS circuit, there is almost zero current flowing through the devices in the standby mode. Therefore, the self–heating effects are greatly reduced.
From the above discussion, we believe that the SOI technology is a preferable choice for the deep–submicrometer generation in the applications of low power, high speed and high reliable integrated circuits.