經過量測及分析結果後，有下列幾點建議提供作為未來可改進之方向：
因 為 整 體 電 路 架 構 複 雜 又 有 些 演 算 法 是 由 FPGA 實 現 ， 且因 為 運 用 到 Correlation-based 的 概 念 ， 模 擬 上 需 要 的 資 料 量 過 於 龐 大 ， 僅 能 做 Behavior-simulation 而無法進行電路的 post-simulation，故可在各級之間加入測 試電路（Design-for-Testability，DfT）單獨量測各級，在除錯（Debug）時才 能更精確掌握問題發生之原因。
設法解決當 Backend ADC 或 Sub_ADC 存在 Offset 時，可能會對後續 Estimation 和 Calibration 演算法產生的影響。
可將導入之隨機校正訊號±N , Nd 1 ± d 2的振幅縮小，則當 Sub_ADC 中的比較器 產生偏移誤差或是增益級產生增益誤差時，增加 MDAC 可容許錯誤範圍，不 過相對來說缺點是這樣會使校正參數的收斂時間拉長。
雖然此論文所提的校正方法可用在多級校正級，但設計的 12-bit Pipelined ADC 前二級均為校正級，使得架構複雜度大為提升，故初步階段可考慮僅先使用 單一級校正級，確保電路可校正成功後再往下發展。
為追求低功率消耗的設計本論文 MDAC 採用 Open-Loop 的架構設計，亦可考 慮以低開迴路增益之 Close-Loop 架構實現，再評估二種架構的功率消耗和穩 定度之表現。
圖 5-3 Bootstrapped Switch 電路中電晶體 M0的基板（Body），可藉由提供的
Deep N-well 製程技術，將基板電壓接至源極（Source）端以消除基板效應（Body
Effect），使開關具有更為線性的導通阻值進而提升整體 S/H 電路效能，圖 7-1
為消除 Body Effect 後 S/H 電路 pre-simulation 的頻譜分析結果，ENOB 可由原 來的 11.8 bits 提升至 12.5 bits。
Power Spectral Density (dBFS/bin)
Power Spectrum 4096 points FFT
Fi = 10MHz , Fs = 100MHz
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