未來展望

第五章結論與未來展望

5.2 未來展望

為了突破電晶體次臨界擺幅(SS) < 60 mV/dec 的熱限制，NCFET 元件結構已漸漸被大家重視。本論文鰭寬度最大只到 400nm，表現出對鐵電層影響不明顯，希望未來研究方面能增加更多的鰭寬度並觀察是否影響NCFET 元件之鐵電層。

並且在經過熱載子注入(HCI)靠度實驗後，我們發現施加能量會導致晶格轉換，

希望研究未來能加入晶格轉換對NCFET 元件電性影響更深入的探討。

另外在快速熱退火實驗中，我們發現氫離子(H⁺)受到 HCI 施壓後鍵結被電子電動對打斷而逸散到元件中形成和移動電荷類似的機制，因此希望未來能去了解氫離子 (H⁺)是如何在元件中運動，進而破壞元件導致元件衰退。

圖2-1 探針座量測系統

圖2-2 半導體參數分析儀(Agilent B1500A)

圖2-3 熱載子效應示意圖

圖2-4 NCFET 元件 Gate 端經過熱載子注入後介面缺陷示意圖

圖3-1 NCFET 結構示意圖

圖3-2 NCFET 元件在 Fresh 狀態時之 TEM 圖

Drain Cu rr ent (A)

Gate Voltage (V)

Fwd NCFET HZO N-type Rvs

W=20nm,L=40nm,H=20nm Vth(Fwd)=370mV

V_th(Rvs)=580mV hysteresis=210mV

NCFET HZO N-type W=20nm,L=40nm,H=20nm

Drain Cu rr ent (A)

Drain Voltage (V)

Fwd Rvs

圖 3-4 鰭寬度 20nm 之 ID-VD曲線

NCFET HZO N-type W=20nm,L=40nm,H=20nm

Gate Voltage (V)

Fwd

Drain Cu rr ent (A)

Gate Voltage (V)

Fwd Rvs

NCFET HZO N-type

W=400nm,L=40nm,H=20nm Vth(Fwd)=220mV

Vth(Rvs)=390mV Hysteresis=170mV

NCFET HZO N-type

W=400nm,L=40nm,H=20nm

Drain Cu rr ent (A)

Drain Voltage (V)

Fwd Rvs

圖 3-10 鰭寬度 400nm 之 ID-VD曲線

NCFET HZO N-type

W=400nm,L=40nm,H=20nm

G

(A/V)

Gate Voltage (V)

Fwd

Drai n C urre nt (A)

Gate Voltage (V)

W=20nm(Fwd) NCFET HZO N-type L=40nm,H=20nm

SS=88 SS=121 SS=151

圖3-12 不同鰭寬度之 ID-VG比較圖

Drai n C urre nt (A)

Drain Voltage (V)

W=20nm(Fwd)

NCFET HZO N-type L=40nm,H=20nm

Gate Voltage (V)

W=20nm(Fwd) NCFET HZO N-type

L=40nm,H=20nm

圖 3-14 不同鰭寬度之 GM-VG比較圖

圖3-15 熱載子注入(HCI)實驗流程圖

圖3-16 NCFET 元件經過 5000 秒 HCI 之 TEM 圖

-2 -1 0 1 2

10^-12 10^-10 10^-8 10^-6 10^-4

Drain Cu rr ent (A)

Gate Voltage (V)

neg~pos pos~neg NCFET HZO N-type

W=20nm,L=40nm,H=20nm HCI: V

G=V

D=2.3V Vth(Fwd)=770mV V_th(Rvs)=1000mV Hysteresis=230mV SS(Fwd)=112.2mV/dec SS(Rvs)=118.4mV/dec

圖3-17 鰭寬度 20nm 經過 5000 秒 HCI Stress 之 ID-VG曲線

NCFET HZO N-type W=20nm,L=40nm,H=20nm HCI: V

G=V

D=2.3V Vth(Fwd)=770mV V_th(Rvs)=1000mV Hysteresis=230mV SS(Fwd)=112.2mV/dec SS(Rvs)=118.4mV/dec

Drain Cu rr ent (A)

Drain Voltage (V)

Fwd

NCFET HZO N-type W=20nm,L=40nm,H=20nm HCI: V

G=V

D=2.3V Vth(Fwd)=770mV V_th(Rvs)=1000mV Hysteresis=230mV SS(Fwd)=112.2mV/dec SS(Rvs)=118.4mV/dec

Drain Cu rr ent (A)

Gate Voltage (V)

Fwd Rvs

圖3-19 鰭寬度 20nm 經過 5000 秒 HCI Stress 之 GM-VG曲線

Drain Cu rr ent (A)

Gate Voltage (V)

Fwd Rvs

NCFET HZO N-type

W=400nm,L=40nm,H=20nm

NCFET HZO N-type

W=400nm,L=40nm,H=20nm

Drain Cu rr ent (A)

Drain Voltage (V)

Fwd

NCFET HZO N-type

W=400nm,L=40nm,H=20nm

Gate Voltage (V)

Fwd Rvs

圖3-25 鰭寬度 400nm 經過 5000 秒 HCI Stress 之 GM-VG曲線

Drai n C urre nt (A)

Gate Voltage (V)

W=20nm(Fwd) NCFET HZO N-type

L=40nm,H=20nm

Drai n C urre nt (A)

Drain Voltage (V)

W=20nm(Fwd)

NCFET HZO N-type L=40nm,H=20nm HCI:V_G=V_D=2.3V

圖3-27 不同鰭寬度經過 5000 秒 HCI Stress 之 ID-VD曲線比較圖

Gate Voltage (V)

W=20nm(Fwd) NCFET HZO N-type

L=40nm,H=20nm

Drai n C urre nt (A)

Gate Voltage (V)

W=20nm(Fresh) NCFET HZO N-type

L=40nm,H=20nm

Drai n C urre nt (A)

Drain Voltage (V)

W=20nm(Fresh)

NCFET HZO N-type L=40nm,H=20nm

Gate Voltage (V)

W=20nm(fresh) NCFET HZO N-type L=40nm,H=20nm HCI:V

G=V

D=2.3V

圖3-31 不同鰭寬度經過 5000 秒 HCI 與 Fresh 之 GM-VG曲線比較圖

1 10 100 1000 10000

0 NCFET HZO N-type L=40nm,H=20nm HCI:V_G=V_D=2.3V

圖3-32 不同鰭寬度經過 5000 秒 HCI Stress 之 ΔSS(Fwd)-Time 比較圖

1 10 100 1000 10000

-5

1 10 100 1000 10000

0 100 200 300 400 500 600

NCFET HZO N-type L=40nm,H=20nm HCI:V_G=V_D=2.3V

 Vt h (mV )

Time (S)

W=20nm(Fwd) W=20nm(Rvs) W=30nm(Fwd) W=30nm(Rvs) W=400nm(Fwd) W=400nm(Rvs)

圖3-34 不同鰭寬度經過 5000 秒 HCI Stress 之 ΔVth-Time 比較圖

圖3-35 不同鰭寬度兩側壁距離示意圖

1 10 100 1000 10000

120 140 160 180 200 220 240 260 280 300

Hyster esi s (mV)

Time (S)

W=20nm W=30nm W=400nm NCFET HZO N-type

L=40nm,H=20nm HCI:V

G=V

D=2.3V

圖3-36 不同鰭寬度經過 5000 秒 HCI Stress 之 Hysteresis-Time 比較圖

圖3-37 NCFET 元件 Fresh 之晶格

圖3-38 NCFET 元件經過 5000 秒 HCI Stress 後之晶格

100 150 200 250 300

80 100 120 140 160

W=20nm W=30nm W=400nm

SS (Fwd) (mV /dec )

Hysteresis (mV)

NCFET HZO N-type L=40nm,H=20nm HCI:V_G=V_D=2.3V

圖3-39 不同鰭寬度經過 5000 秒 HCI Stress 之 SS(Fwd)-Hysteresis 比較圖

150 200 250

100 120 140 160

W=20nm W=30nm W=400nm

SS (R v s) (mV /dec )

Hysteresis (mV)

NCFET HZO N-type L=40nm, H=20nm HCI:V

G=V

D=2.3V

圖3-40 不同鰭寬度經過 5000 秒 HCI Stress 之 SS(Rvs)-Hysteresis 比較圖

圖4-1 未經過快速熱退火之 NCFET Gate 端結構示意圖

圖4-2 經過快速熱退火後之 NCFET Gate 端結構示意圖

0 1

10^-12 10^-10 10^-8 10^-6

Drain Cu rr ent (A)

Gate Voltage (V)

W/O RTA(Fwd) W/O RTA(Rvs) W/ RTA(Fwd) W/ RTA(Rvs)

NCFET HZO N-type

W=400nm,L=40nm,H=20nm RTA: After 5min with 95%N₂,5%H₂ in 400C

Hysteresis(W/O RTA)=170mV Hysteresis(W/ RTA)=120mV SS=125

SS=151

圖4-3 鰭寬度 400nm 下 RTA 前後之 ID-VG曲線

NCFET HZO N-type

W=400nm,L=40nm,H=20nm RTA: After 5min with 95%N2,5%H

2 in 400C

Hysteresis(W/O RTA)=170mV Hysteresis(W/ RTA)=120mV

Drain Cu rr ent (A)

Drain Voltage (V)

W/O RTA(Fwd)

NCFET HZO N-type W=400nm,L=40nm,H=20nm RTA: After 5min with 95%N₂,5%H₂ in 400C Hysteresis(W/O RTA)=170mV Hysteresis(W/ RTA)=120mV

G

(A/V)

Gate Voltage (V)

W/O RTA(Fwd) W/O RTA(Rvs) W/ RTA(Fwd) W/ RTA(Rvs)

圖4-5 鰭寬度 400nm 下 RTA 前後之 GM-VG曲線

NCFET HZO N-type

W=400nm,L=40nm,H=20nm HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C

Hysteresis(W/O RTA)=230mV Hysteresis(W/ RTA)=170mV

Drai n C urre nt (A)

Gate Voltage (V)

W/O RTA(Fwd)

NCFET HZO N-type

W=400nm,L=40nm,H=20nm HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C

Drain Cu rr ent (A)

Drain Voltage (V)

W/O RTA(Fwd) W/O RTA(Rvs) W/ RTA(Fwd) W/RTA(Rvs)

圖4-7 鰭寬度 400nm 下 RTA 前後經過 5000 秒 HCI Stress 之 ID-VD曲線

0 1 2 3

0.0 5.0x10^-6 1.0x10^-5

1.5x10^-5 NCFET HZO N-type

W=400nm,L=40nm, H=20nm

HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C

GM (A/V)

Gate Voltage (V)

W/O RTA(Fwd)

NCFET HZO N-type

W=400nm,L=40nm,H=20nm HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C

Drain Cu rr ent (A)

Gate Voltage (V)

W/O RTA(fresh) W/O RTA(5000s) W/ RTA(fresh) W/ RTA(5000s) SS=151

SS=156 SS=125

SS=134

圖4-9 鰭寬度 400nm 下 RTA 前後 Fresh 與經過 5000 秒 HCI 之 ID-VG曲線比較圖

NCFET HZO N-type

W=400nm,L=40nm,H=20nm HCI:V_G=V_D=2.3V

RTA: After 5min with 95%N₂,5%H₂ in 400C

Drain Cu rr ent (A)

Drain Voltage (V)

W/O RTA(fresh) W/O RTA(5000s) W/ RTA(fresh) W/RTA(5000s)

1.5x10^-5 NCFET HZO N-type

W=400nm,L=40nm, H=20nm

HCI:V_G=V_D=2.3V RTA: After 5min with 95%N₂,5%H₂ in 400C

GM (A/V)

Gate Voltage (V)

W/O RTA(fresh) W/O RTA(5000s) W/ RTA(fresh) W/ RTA(5000s)

圖4-11 鰭寬度 400nm 下 RTA 前後 Fresh 與經過 5000 秒 HCI 之 GM-VG曲線比較圖

1 10 100 1000 10000

0 4 8 12 16

NCFET HZO N-type

W=400nm,L=40nm,H=20nm HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C

 SS (mV /dec )

Time (S)

W/O RTA(Fwd) W/O RTA(Rvs) W/ RTA(Fwd) W/ RTA(Rvs)

圖4-12 鰭寬度 400nm 下 RTA 前後經過 5000 秒 HCI Stress 之 ΔSS-Time 圖

圖4-13 電子電動攻擊 H⁺示意圖

圖4-14 H⁺離子鍵結被打斷逸散到元件示意圖

1 10 100 1000 10000

-40 0 40 80

NCFET HZO N-type

W=400nm,L=40nm,H=20nm HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C

 Hyster esis (mV )

Time (S)

W/O RTA W/ RTA

圖4-15 鰭寬度 400nm 下 RTA 前後經過 5000 秒 HCI 之 Hysteresis-Time 圖

120 160 200 240

135 150 165

NCFET HZO N-type W=400nm,L=40nm, H=20nm

HCI:V

G=V

D=2.3V RTA: After 5min with 95%N2,5%H

2 in 400C W/O RTA W/ RTA

SS (mV /dec )

Hysteresis (mV)

圖4-16 鰭寬度 400nm 下 RTA 前後經過 5000 秒 HCI 之 SS-Hysteresis 分布圖

參考文獻

[1] Cheng-Li Lin, Po-Hsiu Hsiao, Wen-Kuan Yeh, Han-Wen Liu, Syuan-Ren Yang, Yu-Ting Chen, Kun-Ming Chen, Wen-Shiang Liao, “Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs”, IEEE Transactions on Electron Devices, vol. 60, pp.3639-3644, 2013.

[2] M. O. Thomyson, "Rapid thermal annealing in the microsecond regime," 10th IEEE International Conference of Advanced Thermal Processing of Semiconductors, Vancouver, BC, Canada, 2002, pp. 193-, doi:

10.1109/RTP.2002.1039460.

[3]

W. Yeh, W. Zhang, C. Shih and Y. Yang, "Effects of fin width on performance and reliability for N- and P-type FinFETs," 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, 2016, pp. 361-364, doi: 10.1109/EDSSC.2016.7785283.

[4]

P. Sung et al., "Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 474-480, 2020, doi:

10.1109/JEDS.2020.2987005.

[5] C. H. Cheng and A. Chin, “Low-voltage steep turn-on p-MOSFET using ferroelectric high-k gate dielectric,” IEEE Electron Device Lett., vol. 35, pp. 274–

276, 2014.

[6] G. C. Tettamanzi, A. Paul, S. Lee, S. R. Mehrotra, N. Collaert, S. Biesemans, G.

Klimeck, and S. Rogge, “Interface trap density metrology of state-of-the-art undoped Si n-FinFETs,” IEEE Electron Device Lett., vol. 32, no. 4, Apr. 2011.

[7] Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J.Liu, J.Shi, H.J. Kim, R. Sporer, C. Serrao, A.Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, and S. Banna , “14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications,” in Proc.

IEEE IEDM, 2017.

[8] P. J. Sung, C. J. Su1, Y. J. Lee, D. D. Lu, S. X. Luo, K. H. Kao et al., “Fabrication

of Ω-gated negative capacitance FinFETs and SRAM,” in Proc. IEEE VLSI-TSA, 2019.

[9] J. S. Lee, Y. K. Choi, D. Ha, "Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs," IEEE Electron Device Lett., vol. 24, no.

3 , Mar. 2003.

[10] M. Hoffmann, B. Max, T. Mittmann, U. Schroeder, S. Slesazeck and T. Mikolajick,

"Demonstration of High-speed Hysteresis-free Negative Capacitance in Ferroelectric Hf0.5Zr0.5O2," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 31.6.1-31.6.4, doi:

10.1109/IEDM.2018.8614677.

[11] Z. Yu et al., "Negative capacitance 2D MoS2 transistors with sub-60mV/dec

subthreshold swing over 6 orders, 250 μA/μm current density, and nearly-hysteresis-free," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 23.6.1-23.6.4, doi: 10.1109/IEDM.2017.8268448.

[12] C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin and C. Hu, "Low power negative

capacitance FETs for future quantum-well body technology," 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2013, pp. 1-2, doi: 10.1109/VLSI-TSA.2013.6545648.

[13] H. Lee, K. Tseng and P. Su, "Interface discrete trap induced variability for negative

capacitance FinFETs," 2018 International Symposium on VLSI Technology,

Systems and Application (VLSI-TSA), Hsinchu, 2018, pp. 1-2, doi:

10.1109/VLSI-TSA.2018.8403836.

[18] 林孟琰，民 108，功函數對於多鰭數 p-FinFET 之電性分析及 NBTI 可靠度研究，國立高雄大學電機工程研究所碩士論文

[19] 陳詩堯，民 105，不同金屬閘極對多重鰭數 N 型鰭式場效電晶體之可靠度研究，國立高雄大學電機工程研究所碩士論文

[20] 許值誠，民 107，熱載子效應及定電壓應力對不同主動區面積 Tri-Gate FinFET 元件之可靠度研究，國立高雄大學電機工程研究所碩士論文 [21] 鍾思行，民 96，以快速熱退火加強金屬側向誘發結晶速率之研究，國立交

通大學材料科學與工程研究所碩士論文

在文檔中快速熱退火及不同鰭寬度的NCFET 之電性分析及HCI可靠度研究 (頁 31-65)

第五章 結論與未來展望

5.2 未來展望

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

Gate Voltage (V)

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

G

(A/V)

Gate Voltage (V)

Drai n C urre nt (A)

Gate Voltage (V)

Drai n C urre nt (A)

Drain Voltage (V)

Gate Voltage (V)

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

Gate Voltage (V)

Drai n C urre nt (A)

Gate Voltage (V)

Drai n C urre nt (A)

Drain Voltage (V)

Gate Voltage (V)

Drai n C urre nt (A)

Gate Voltage (V)

Drai n C urre nt (A)

Drain Voltage (V)

Gate Voltage (V)

 Vt h (mV )

Time (S)

Hyster esi s (mV)

Time (S)

SS (Fwd) (mV /dec )

Hysteresis (mV)

SS (R v s) (mV /dec )

Hysteresis (mV)

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

G

(A/V)

Gate Voltage (V)

Drai n C urre nt (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

GM (A/V)

Gate Voltage (V)

Drain Cu rr ent (A)

Gate Voltage (V)

Drain Cu rr ent (A)

Drain Voltage (V)

GM (A/V)

Gate Voltage (V)

 SS (mV /dec )

Time (S)

 Hyster esis (mV )

Time (S)

SS (mV /dec )

Hysteresis (mV)

參考文獻

W. Yeh, W. Zhang, C. Shih and Y. Yang, "Effects of fin width on performance and reliability for N- and P-type FinFETs," 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, 2016, pp. 361-364, doi: 10.1109/EDSSC.2016.7785283.

P. Sung et al., "Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 474-480, 2020, doi:

10.1109/JEDS.2020.2987005.

"Demonstration of High-speed Hysteresis-free Negative Capacitance in Ferroelectric Hf0.5Zr0.5O2," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 31.6.1-31.6.4, doi:

10.1109/IEDM.2018.8614677.

第五章結論與未來展望