第六章 總結與未來展望
6.2 未來展望
在本論文中，主要提出之架構，使得 DAC 中電容充放電之耗能可有效降低。
另外，實現了兩個基於浮動開關電容技術下的電路架構，其一為部分式開關電容 技術之差動 SAR ADC，另一為分裂式 SAR ADC。而電路元件的設計，盡可能簡 化數位邏輯以及低功率的類比電路配合，讓系統的整體效能最佳化。
以下將提出幾點可精進 SAR ADC 性能的電路設計方案之臆測，並論述所提 出之浮動開關電容技術可進行改良的想法。
1. SAR ADC 因具備低耗能的長處而日益受到重視，僅需一個比較器完成所有資 料處理，此特點雖為低耗能最主要之因素，卻為 SAR ADC 帶來速度上的限 制；然而，在製程技術的演進後，高速的 SAR ADC 架構已陸續在文獻上可窺 知一二；除此之外，SAR ADC 也可與時間插敘(time-interleaved)技術作結合，
對速度的提升都是相當有幫助的。
2. 能量的損耗，絕多數來自於電容的充放電過程，其耗能正比於電容值的大小。
根據 KT/C 的熱雜訊影響，此電容值 C 是遠小於實際電路設計的單位電容數十 或數百倍以上，但在 TSMC 0.18-μm 1P6M 標準製程下，受限於電路佈局 DRC 的設計規範，MIM 電容設計最小約為 20-fF，若能謹慎地採用穩定的 Metal 電 容或是其他先進製程的 MOM 電容技術，使得單位電容降低，不僅更能節省能 量損失，其佈局的面積也可大幅縮小，速度進而提升。
3. 二進制電容排列的 SAR ADC 在近期文獻中，已被提出許多方案來解決傳統架 構能量浪費的問題，目前的設計方向轉朝向高速的電路邁進，而電容式 DAC 開始有串聯的架構被提出，但在精確度而言，仍然不及二進制電容排列方式，
故各式不同的校正電路也一併被提出也驗證其可行性，這將是未來電容式 DAC 的電路設計趨勢，若能與浮動開關電容技術合併，效能應能提升不少。
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