第五章 浮動開關電容式 SAR ADC 實現
4. 濾波槽電路
6.2 未來展望
在本論文中，主要提出了浮動開關電容技術的新型切換技巧，使得 DAC 中 電容充放電之耗能可有效降低。另外，實現了兩個基於浮動開關電容技術下的新 穎電路架構，其一為部分式開關電容技術之差動 SAR ADC，另一為雙部分式開 關電容技術之單端 SAR ADC，皆是利用所提出之架構特性，來達到能量的最有 效利用。而電路元件的設計，盡可能簡化數位邏輯以及低功率的類比電路配合，
讓系統的整體效能最佳化。
以下將提出幾點可精進SAR ADC 性能的電路設計方案之臆測，並論述所提 出之浮動開關電容技術可進行改良的想法。
1. 在眾多類比數位轉換器中，SAR ADC 因具備低耗能的長處而日益受到重視，
僅需一個比較器完成所有資料處理，此特點雖為低耗能最主要之因素，卻為 SAR ADC 帶來速度上的限制；然而，在製程技術的演進後，高速的 SAR ADC 架構已陸續在文獻上可窺知一二；除此之外，SAR ADC 也可與時間插敘 (time-interleaved)技術作結合，對速度的提升都是相當有幫助的。
2. 能量的損耗，絕多數來自於電容的充放電過程，其耗能正比於電容值的大小。
根據KT/C 的熱雜訊影響，此電容值 C 是遠小於實際電路設計的單位電容數十 或數百倍以上，但在TSMC 0.18-μm 1P6M 標準製程下，受限於電路佈局 DRC 的設計規範，MIM 電容設計最小約為 20-fF，若能謹慎地採用穩定的 Metal 電 容或是其他先進製程的MOM 電容技術，使得單位電容降低，不僅更能節省能 量損失，其佈局的面積也可大幅縮小，速度進而提升。
3. 在 SAR ADC 中，除了取樣保持電路以及比較器，大部分構成其內部電路皆為
數位電路，由實作SAR ADC 可發現，暫存器的能量損耗其實占了一大部分，
而數位邏輯主要在於區分最高以及最低電位，假使能將數位電源降低，且不影 響高低電位的判斷準確性，總能量損耗勢必能被縮減。
4. 對於完整的浮動開關電容技術來說，已可由數學證明得知能量能達到極有效能 的利用，但是在電路的實現方面，實際上會遭遇到許多非理想的特性，如開關 浮動時，寄生電容對整體的DAC 電路充放電。使得所完成的真實架構都僅為 部分的浮動開關電容技術，在電路設計的過程中，曾有思考採用負電容的技術 來克服寄生的效應，但最終因效果不彰而作罷。另外，數位自我補償的機制或 許可以解決此一設計上困難。
5. 二進制電容排列的 SAR ADC 在近期文獻中，已被提出許多方案來解決傳統架 構能量浪費的問題，目前的設計方向轉朝向高速的電路邁進，而電容式 DAC 開始有串聯的架構被提出，但在精確度而言，仍然不及二進制電容排列方式，
故各式不同的校正電路也一併被提出也驗證其可行性，這將是未來電容式 DAC 的電路設計趨勢，若能與浮動開關電容技術合併，效能應能提升不少。
參 考 文 獻
[1] B. Razavi,
Design of Analog CMOS Integrated Circuits, McGraw-Hill Companies, Inc.,
2002.[2] D. A. Johns and K. Martin, Analog CMOS Integrated Circuit Design, John Wiley &
Sons, Inc., 1997.
[3] K.-L. Lin, A. Kemna, and B. J. Hosticka, Modular low-power, high-speed CMOS
analog-to-digital converter for embedded systems, Kluwer Academic Publishers, 2003.
[4] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, John Wiley &
Sons, Inc., 2008.
[5] M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition, Kluwer Academic Publishers, 2001.
[6] J. McCreary and P. R. Gray, “A high-speed, all-MOS successive-approximation weighted capacitor A/D conversion technique,” IEEE Int. Solid-State Circuits Conf., Feb. 1975, pp. 38–39.
[7] S. Mortezapour and E. K. F. Lee, “A 1-V, 8-Bit successive approximation ADC in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642–646, Apr.
2000.
[8] G. Promitzer, “12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s,” IEEE J. Solid-State Circuits, vol. 36, no.
7, pp. 1138–1143, Jul. 2001.
[9] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultralow-energy ADC for smart dust,”
IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1223–1229, Jul. 2003.
[10] T. Yoshida, M. Sasaki, and A. Iwata, “A 1-V supply successive approximation ADC with rail-to-rail input voltage range,” IEEE Int. Symp. Circuits Syst., May 2005, pp.
192–195.
[11] H. P. Le, J. Singh, L. Hiremath, V. Mallapur, and A. Stojcevski, “Ultra-low-power variable-resolution successive approximation ADC for biomedical application,”
Electron. Lett., vol. 41, no. 11, May 2005.
[12] J. Sauerbery, T. Tille, D. S. Landsiedel, and R. Thews, “A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology,” IEEE J.
Solid-State Circuits, vol. 37, no. 12, pp. 1662–1669, Dec. 2002.
[13] G.-C. Ahn, D.-Y. Chang, M. E. Brown, N. Ozaki, H. Youra, K. Hamashita, K.
Takasuka, G. C. Temes, and U.-K. Moon, “A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp.
2398–2407, Dec. 2005.
[14] J. Shen and P. Kinget, “A 0.5-V 8-bit 10-Msps pipelined ADC in 90-nm CMOS,” IEEE
Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 202–203.
[15] M. Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE J.
Solid-State Circuits, vol. 36, no. 1, Jan. 2001.
[16] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-μW successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261–1265, Jul.
2003.
[17] H.-C. Hong and G.-M. Lee, “A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp.
2161–2168, Oct. 2007.
[18] C.-H. Kuo and C.-E. Hsieh, “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,” IEEE Eur. Solid-State Circuits Conf., Sep.
2011, pp. 475–478.
[19] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” IEEE Int. Symp. Circuits Syst., May 2005, pp. 184–187.
[20] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.
[21] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500-KS/s low power SAR ADC for bio-medical applications,” IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp.
228–231.
[22] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010.
[23] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no.
9, pp. 620–621, Apr. 2010.
[24] T. Anand, V. Chaturvedi, and B. Amrutur, “Energy efficient asymmetric binary search switching technique for SAR ADC,” Electron. Lett., vol. 46, no. 22, pp. 1487–1488, Oct. 2010.
[25] Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90-nm CMOS,” IEEE J. Solid-State
Circuits, vol. 45, no. 6, pp. 1111–1121, Jun. 2010.
[26] C.-H. Kuo and C.-E. Hsieh, “Floating capacitor switching SAR ADC,” Electron. Lett., vol. 47, no. 13, pp. 742–743, Jun. 2011.
[27] M. Dessouky and A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349–355, Mar. 2001.
[28] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” Electron. Lett., vol. 35, no. 1, pp. 8–10, Jan.
1999.
[29] H. T. Russell and JR., “An improved successive-approximation register design for use in A/D converters,” IEEE Trans. Circuits Syst., vol. 25, no. 7, pp. 550–554, Jul. 1978.
[30] A. Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055–1057, Jun. 1996.
[31] J. Yuan and C. Svensson, “New TSPC latches and flipflops minimizing delay and power,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 160–161.
[32] D. Schinkel, E. Mensink, E. Kiumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps setup+hold time,” IEEE Int. Solid State
Circuits Conf., Feb. 2007, pp. 314–605.
[33] M. Elzakker, E. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9-μW at 1-MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007–1015, May 2010.
[34] A. Nikoozadeh and B. Murmann, “An analysis of latch comparator offset due to load capacitor mismatch,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 12, pp.
1398–1402, Dec. 2006.
[35] J. He, S. Zhan, D. Chen, and R. L. Geiger, “Analyses of static and dynamic random offset voltages in dynamic comparators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.
56, no. 5, pp. 911–919, Jul. 2009.
[36] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta
Modulators, Kluwer Academic Publishers, 1999.
[37] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and J. Craninckx,
“An 820-μW 9b 40-MS/s noise tolerant dynamic SAR ADC in 90-nm digital CMOS,”
IEEE Int. Solid-State Circuits Conf., Feb. 2008, pp. 238–610.
[38] N. Verma and A. P. Chandrakasan, “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196–1205, Jun. 2007.
[39] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1-V 3.8-μW 100-kS/s SAR ADC with time-domain comparator,” IEEE Int. Solid State Circuits
Conf., Feb. 2008, pp. 245–247.
[40] W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, “A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications,”
IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 149–152.
[41] G. Yin, U-F. Chio, H.-G. Wei, S.-W. Sin, S.-P. U, R. P. Martins, and Z. Wang, “An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications,” IEEE
Int. Conf. Electron. Circuits Syst., Dec. 2010, pp. 878–881.
[42] J.-H. Cheong, K.-L. Chan, P. B. Khannur, K.-T. Tiew, and M. Je, “A 400-nW 19.5-fJ/conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18-μm CMOS,” IEEE Trans.