本論文第一部分使用 TSMC rf-0.18um 製程設計了一個應用在非整數除頻器之 多級 1-1-1 三角積分調變器,擁有 16-bit 的解析度,最大操作速度可達 80 MHz,
功耗 970 uW。
第二部分使用 TSMC 0.35um 製程設計了一個 D 類音頻放大器,D 類放大器被 大量應用在手持式電子裝置,主要好處在功率效率高,在對於音質沒有特別高要 求的情況下可以大幅提升電池續航力,並且相對於線性放大器而言面積可以縮小,
並減少過大功率損耗造成的散熱問題。我們採用三階三角積分調變應用在 D 類切 換放大器上面,相對於 D 類放大器常見的脈衝寬度調變而言,可以改善在脈衝寬 度調變之切換頻率附近以及倍頻處的電磁干擾問題。採用三角積分調變的同時亦 可以減少調變中產生的非線性項,以達到較佳的總諧波失真效能。最終模擬出開 回路功率效能 89.6 %、最大輸出功率 343 mW、總諧波及雜訊失真 0.064 %、訊噪 比(SNR) 96.4 dB、訊號對雜訊及失真項比(SNDR)為 73.89 dB;閉迴路功率效能 83.3%、最大輸出功率 357 mW、總諧波及雜訊失真 0.056 %、訊噪比(SNR) 94.12 dB、
訊號對雜訊及失真項比(SNDR)為 78.5 dB 之 D 類功率放大器。
參考文獻.
[1] D. A. Stone, and B. Chambers, "Effect of spread-spectrum modulation of
switched mode power converter PWM carrier frequencies on conducted EMI, "
Electronic Letters, vol. 31, issue 10, pp.769-770, May, 1995.
[2] Steven R. Norsworthy, Richard Schreier and Gabor C. Theme, Delta-Sigma Data Converters, Theory, Design, and Simulation, Piscataway, NJ: IEEE Express, 1997.
[3] Rudolf Koch, Franz Eckbauer, Eduard Engelhardt, John A. Fisher, and Dranz Parzefall "A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate," IEEE J. of Solid-State Circuits, vol. 21, no. 6, pp.1003-1010, Dec. 1986.
[4] ApplicationNote2031, "DC-DC converter tutorial,"
http://www.maxim-ic.com/app-notes/index.mvp/id/2031
[5] Jun-woo Lee, Jae-shin Lee, Gun-sang Lee, and Sulu Kim, "A 2W BTL single chip class d power amplifier with very high efficiency for audio applications,"
in Proc. IEEE ISCAS, vol. 5, May, 2000, pp. 493-496.
[6] Jorge Varona, Anas A. Hamoui, and Ken Martin, "A low-voltage fully-monolithic Delta Sigma based class-D audio amplifier," in Proc. IEEE ESSCIRC, 2003, pp. 545-578.
[7] Eric Gaalaas, Bill Yang Liu, Naoaki Nishimura, "Integrated stereo delta-sigma class d amplifier," in ISSCC Dig. Tech. Papers, pp. 120-121, Dec. 2005.
[8] Kyoungsik Kang, Jeongjin Roh, Youngkil Choi, Hyungdong Roh, Hyunsuk Nam, and Songjun Lee, "Class-d audio amplifier using 1-bit fourth-order delta-sigma modulation," IEEE Tran. on Circuits Syst. II, Exp. Briefs, vol. 50, no. 11, pp. 728-732, Aug. 2008.
[9] Lukas Dorrer, Franz Kuttner, Patrizia Greco, Patrick Torta, and Thomas Hartig, "A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC With a Tracking ADC Quantizer in 0.13-m CMOS," IEEE J. of Solid-State Circuits, vol. 40, no. 12, pp. 2416-2427, Dec. 2005.
[10] Yasuyuki Matusuya, Kuniharu Uchimura, Atsushi Iwata, and Tsutomu Kobayashi, "A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping," IEEE J. of Solid-State Circuits, vol. 22, no. 6, pp. 921-929, Dec. 1987.
[11] David A. Johns, and Ken Martin, Analog Integrated Circuit Design. Wiley, Chapter 9, 1997.
[12] Alan V. Oppenhem, Alan S. Willsky, and S. Hamid Nawab, Signals & Systems, Second Edition. Prentice Hall Signal Processing Series.
[13] Bernard Widrow, "A study of rough amplitude quantization by means of nyquist sampling theory," IEEE Trans. Circuit Theory, vol. 3, pp. 266–276, no.4, Dec.
1956.
[14] JAMES C. Candy and Oconnell J. Benjamin, "The structure of quantization noise from sigma-delta modulation," IEEE Trans. Communications, vol. 29, no. 9, pp. 1316-1323, Sept. 1981.
[15] R.W. Stewart, and E. Pfann, "Oversampling and sigma-delta strategies for data conversion," IET J. Electronic and Communication Engineering, vol. 10, issue1, pp.37-47, 1998.
[16] Ian Galton, and Henrik T. Hensen, "Oversampling parallel delta-sigma modulator a/d conversion," IEEE Tran. on Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 12, Dec. 1996.
[17] C. Budsabathon and A. Nishihara, "Design of high order stable delta sigma modulator with state space approach," in IEEE Tecon, vol. A, Nov. 2004.
pp.523-526
[18] W.L. Lee, "A novel interpolative modulator topology for high resolution oversampling a/d converters," Master’s Thesis, Massachusetts Institute of Technology, Cambridge, MA, June 1987.
[19] G. Troster, P. Ferguson, K. Schoppe, A. Wedel, E. Zocher, J. Arndt, H-J. Dressler, H-J Golberg and W. Schardein, "An interpolative bandpass converter on a 1.2mm bi-cmos analog/digital array," IEEE J. of Solid-State Circuits, vol. 28,
no.4, pp.471-477, Apr. 1993.
[20] G. I Bourdopouos, A. Pnevmatikakis, V. Anastassopouos and T. L Deliyannis, Delta-Sigma Modulators: Modeling, Design and Application. Imperial College Press, 2006.
[21] W. Chou, P. Wong, R. Gray, "Multi-stage sigma-delta modulation," IEEE Trans.
Information Theory, vol. 35, pp. 784-796, July 1989.
[22] Eric J. Van der Zwan and E. Carel Dijkmans, "A 0.2mW cmos delta sigma modulator for speech coding with 80dB dynamic range," IEEE J. of Solid-State Circuits, Vol.31, No. 12, pp.1873-1880, Dec. 1996.
[23] Richard scherier, and Gabor C. Themes, Understanding Delta Sigma Data Converters. , Wiley, IEEE Press, 2004.
[24] 劉深淵, 楊清淵, 鎖相迴路 , in Chapter 3, 滄海書局, Nov. 2006.
[25] N. Christoffers, R. Kokozinski, S. Kolnsberg, and B.J. Hosticka, "High loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in
frequency-hopping spread-spectrum communication-systems," in Proc. IEEE ISCAS, May, 2003, pp.216-219.
[26] Tom A. D. Riley, Miles A. Copeland, "Delta-sigma modulation in fractional-n frequency synthesis," IEEE J. of Solid-State Circuits, vol. 28, No. 5,
pp.553-559, May 1993.
[27] Terrence p. Kenny, Thomas A.D. Riley, Norman M. Filiol, and Miles A. Copeland.
"Design and realization of a digital ΔΣ modulator for fractional-n frequency synthesis," IEEE Trans. Vehicular Technology, vol. 48, No. 2, pp. 510-521, March 2009.
[28] Chun-Pang Wu, Hen-Wai Tsao, and Jingshown Wu, "A novel sigma-delta fractional-n synthesizer architecture with fractional spur and quantization noise cancellation," in Proc. IEEE ISCAS, May 2010, pp. 1117-1120.
[29] Eric Gaalaas, Bill Yang Liu, Naoaki Nishimura, Robert Adams, and
Karl Sweetland, "Integrated stereo ΔΣ class d amplifier," IEEE J. of Solid-State Circuits, vol. 40, No. 12, pp.2388-2396, Dec. 2005.
[30] Jun Honda, and Jonathan Adams, "Class d audio amplifier basics," Application Note AN-1071, International Rectifier.
[31] Joseph S. Chang, Meng-Tong Tan, Zhihong Cheng, and Yit-Chow Tong, "Analysis and design of power efficient class d amplifier output stages," IEEE Trans. Circuits Syst., vol. 47, no. 6, pp.897-902, June 2000.
[32] Kirk C. H. Chao, Shujaat Nadeem, Wai L. Lee, and Charles G. Sodini, "A higher order topology for interpolative modulators for oversampling a/d converters,"
IEEE Trans. Circuits Syst, vol. 37, no. 3, pp.196-205, March 1990.
[33] http://www.mathworks.com/matlabcentral/fileexchange/19
[34] Behzad Razavi, Design of Analog CMOS Integrated Circuits. MaGraw-Hill, 2002.
[35] Richard Schreier, and Trevor Caldwell, Advanced Analog Circuits Notes.
[36] http://www.national.com/mpf/LM/LM4665.html#Overview [37] http://www.national.com/mpf/LM/LM4666.html#Overview [38] http://www.national.com/mpf/LM/LM4667.html#Overview [39] http://www.national.com/mpf/LM/LM4670.html#Overview
[40] C. W. Lin, Y. P. Lee, and W. T. Chen, "A 1.5 bit 5th order ct/dt delta sigma class d amplifier with power efficiency improvement," in Proc. IEEE ISCAS, May 2008, pp. 280-283.
[41] A. Matamura, N. Nishinmura, and B. Y. Liu, "Filterless multi-level delta-sigma class-d amplifier for portable applications," in Proc. IEEE ISCAS, May 2009, pp.
1177-1180.
[42] Yang Boon Quek, "Application report, SLOA119A- April,"
http://focus.tij.co.jp/jp/lit/an/sloa119a/sloa119a.pdf, T.I. INC. 2006.
[43] J. S. Chang, B. H. Gwee, Y. S. Lon, and M. T. Tan, "A novel low-power
low-voltage class d amplifier with feedback for improving thd power effiency and gain linearity," in Proc. IEEE ISCAS, May 2001, pp. 635-638.