本論文實現了一個可以應用在 EPON 系統中的多頻帶且快速鎖定的時脈資料 回復電路，其可操作的頻帶範圍是 625Mbps 到 3.125Gbps，鎖定的速度是 16 的 位元時間。此電路使用 0.18µm 1P6M CMOS 製程來實現的。
本論文提出的時脈資料回復電路的是採用 1/4 速率的架構，即時脈信號的頻 率是輸入資料頻率的 1/4 倍，目的是讓電路可以不必直接操作在高速，讓電路的 實現更加的容易，除此之外，更可以節省功率的消耗。此外本論文中的時脈資料 回復電路架構是採用 2 倍速超取樣的的技術，而本論文使用的 8 種相位的時脈信 號都是由一種環形震盪器所產生的，相位內插器再擷取彼此相位相差 90 度的信 號合成出八組的取樣相位，在相位偵測器中再利用此合成相位對輸入的資料作取 樣。而為了達到快速鎖定的目標，在迴路濾波器的的地方採用了二位元搜尋法的 演算法，只要比對四次取樣信號和輸入資料的相位關係，便可以找到最佳的取樣 相位。傳統的數位迴路濾波器是以加法器實現的，在本論文中提出以移位暫存器 取代了加法器，如此便可以使得操作速度大幅的提升。
表 5- 1 所示為本設計與國際各大期刊的比較，集合近年來相關製程及高速的 時脈資料回復電路的比較，在本次設計利用 0.18µm CMOS 製程實現，除在晶片 面積上不及其他的設計，在其它方面都是一流的表現，故有達到高效能、高傳輸 速率、高整合性、低功率消耗、快速鎖定及多頻帶操作之串列傳輸介面等目標。
Fig 5.1 為晶片的照相圖，Fig 5.2 為測試環境的設定，E8257D 提供了 PLL 的 參考信號，PLL 產生的時脈信號頻譜可以由 8563E 觀察得到，N4901B 可以量測 時脈資料回復電路的錯誤率。
表 5- 1 時脈資料回復電路之國際指標
Fig 5.1 晶片照相圖
Fig 5.2 晶片測試環境的設定
參考文獻
[1] Masafumi Nogawa, et al, “A 10 Gb/s burst-mode CDR IC in 0.13 μm CMOS, ” in ISSCC Digest of Technical Papers, pp. 228-229 , Feb. 2005.
[2] Chih-Kong Ken Yang, et al. , “A 0.5μ m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” in IEEE J. Solid-State
Circuits, vol. 33, pp. 713-722, May. 1998.
[3] Wei-Zen Chen and Chin-Yuan Wei, “High-speed clock and data recovery circuit,” U.S. and R.O.C. patent pending.
[4] Rainer Kreienkamp, et al, “A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator,” in IEEE J. Solid-State Circuits, pp. 736-743, March 2005.
[5] Rong-Jyi Yang,Shang-Ping Chen,and Shen-Iuan Liu,”A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet,”IEEE JSSC, VOL.39,NO.8,AUGUST 2004.
[6] Toru Iwata,Takashi Hirata,Hirokazu Sugimoto,Hiroshi Kimura,and Takefumi Yoshikawa,”A 5Gbps CMOS Frequency Tolerant Multi Phase Clock Recovery Circuit,”IEEE SOVC 2002.
[7] Alan Li,Julien Faucher,and David V. Plant,”Burst-Mode Clock and Data Recovery in Optical Multiaccess Networks Using Broad-Band PLLs,”IEEE PHOTONICS TECHNOLOGY LETTERS,VOL.18,NO.1,JANUARY 1,2006.
[8] Kun-Yung Ken Chang,Jason Wei,member,IEEE,Charlie Huang, Simon Li,Kevin Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos,” A 0.4-4-Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs,”IEEE JSSC VOL.38,NO5,MAY,2003.
[9] C.-H.Park et al.,” Alow-noise 900MHz VCO in 0.6um CMOS,”IEEE JSSC,vol.34,pp.586-591,MAY 1999.
[10] M.Lee et al., Low-power area-efficieent high-speed I/O circuit techniques,IEEE J.
Solid-state Circuits,vol.35,pp.1591-1599,nov.2000.
[11] S.Sidiropoulos et al., A semi-digital DLL,IEEE J. Solid-State Circuits,vol.32,pp.1683-1692,Nov.1997.
[12] J. Maneatis , Low-jitter process independent DLL and PLL bases on self-biased techniques,IEEE J. Solid-State Circuits,vol.31,pp.1723-1732,Nov.1996.
[13] T. LEE et al., Cascode voltage switch logic : A differential CMOS logic family,in IEEE JSSC Conf.Dig.Tech.Papers,Feb.1984,pp.16-17.
[14] J.D.H. Alexander, Clock recovery from random binary signals, Electron. Lett., vol.11,pp.541-542,Oct.1975.
[15] J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit With a Half-Rate Binary Phase/Frequency Detector,” IEEE Journal of Solid-State Circuits, vol.38, No. 1, pp. 13-21, 2003.
[16] S. Jonathan E. Rogers, and John R. Long, “A 10Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18µm CMOS,” IEEE ISSCC, pp. 254-255, 2002.
[17] M. Meghelli et al., “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuits for 10-Gb/s Serial Transmission System,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1992-1995, Dec. 2000.
[18] Y. M. Greshishchev et al., “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application,” IEEE Journal of Solid-State Circuits, vol.35, No. 9, pp. 1353-1359, September 2000.
[19] S. G. Georgiou, Y. Baeyens et al., “Clock and Data Recovery IC for 40-Gb/s Fiber-Optical Receiver,” IEEE Journal of Solid-State Circuits, vol.37, No. 9, pp.
1120-1125, September 2002.
[20] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of Solid-State Circuits, VOL. 31, NO.3, pp. 331-343, March 1996.
[21] J. –H. You, “Clock Multiplier Unit and Clock/Data Recovery for OC-192 Transceiver “ Master’s thesis, National Central University, Institute of Electronics Engineering, June 2003.
[22] C. –C. Liu, “ A 1.8V CMOS OC-192 Transmitter “ Master’s thesis, National Central University, Institute of Electronics Engineering, June 2003.
[23] R. E. Best, “Phase-Locked Loops: Design, Simulation, and Applications,” New York: McGraw-Hill, Fourth Ed., 1999.
[24] S. –J. Lee et al., “A fully integrated Low-noise 1-GHz frequency synthesizer design for mobile communication application,” IEEE Journal of Solid-State Circuits, VOL. 32, NO.5, pp. 760-765, May 1997.
[25] S. –J. Lee et al., “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme ,” IEEE Journal of Solid-State Circuits, VOL. 32, NO.2, pp. 289-291, Feb. 1997.
[26] Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu, “10 GHz quadrature-phase voltage controlled oscillator and prescaler ,” ESSCIRC 2003, 16-18 Sept. 2003.
[27] Fiber Channel-Methodologies for jitter specification,T11.2/Project 1230/Rev 10,June.1999.