本論文探討如何於電子構裝基板上訊號線路被佈局並兼顧訊號完整性(SI)前，
先行顧全電源完整性(PI)的設計與驗證，確保相關電源受雜訊的干擾能降到最低同時 使電源能穩定的供應與傳輸，進而確保IC與系統的正常運作。於是當收集完成IC與 封裝基板等相關資訊後，首先需評估與決定封裝基板的層數與導電層的設計，透過 相關電子輔助模擬軟體(如: HFSS、ADS等等)的驗證，可得知探討於電源層與接地 層兩平行板間在未有任何傳輸線穿層經時的自然共振特性，此即為頻域的模擬分 析。再來則進一步設計引入較具干擾雜訊的數位週期訊號傳輸線(包含PCI單端週期 訊號與DDR2差動週期訊號)並穿層經過電源層與接地層，觀測其整個電源層面與接 地層面間受此穿層訊號所引發的雜訊情形，並針對於所應用的頻段(一般為工作頻率) 內何處的雜訊影響最為嚴重，則可避免重要且較容易受到干擾之傳輸訊號及相關的 供應電源設計經過於此處，以得到相當程度的保護，此即為時域的模擬分析。最後 引入降低雜訊干擾的解決方案如解耦合電容的設計應用，並設法找出最佳擺放解耦 合電容的位置與適當的電容值，以期望達到最佳的雜訊抑制效結果。於是可以整理 出電源完整性設計與驗證的相關流程，如圖5-1所示。同時可以得到以下幾點總結:
1. 基板線路佈局時，應先顧全電源完整性(Power Integrity, PI)的設計。
2. 訊號穿層經過電源層(P)與接地層間(G)，會在P/G層間各點處造成不同程度
的雜訊干擾，尤其以數位單端週期訊號所造成的雜訊干擾最嚴重。3. 穿層時所造成的雜訊，以較低頻段(窄頻)的雜訊而言，距離穿層點(Via)越近
的雜訊干擾越嚴重，於是在穿層點附近擺放解耦合電容去降低干擾雜訊的效 果會優於較遠處。然而當雜訊是具有較高頻的成份時(寬頻)，除了時域 (T-Domain)的模擬外，同時須具備頻域(F-Domain)的模擬驗證，加以重覆驗 證，於是須先確定所關心與想要解決的頻段後，之後透過頻域與時域的模擬 驗證，則可更精準的預測干擾雜訊分佈的狀態。未來展望則為製作實際樣品(Package Sample)與建立實際運作系統並加以運 作驗證以及量測比對之。
IC與構裝基板的相關資訊取得與分析
1. 決定構裝基板的架構與層數 2. 決定構裝基板的導電層別 3. 電源層面(P)與接地層面(G)的設計 4. 選擇並佈局高速、具干擾性質的傳輸訊號
結束
1. 建立所設計的模組(Model) (如用HFSS) 2. 平均設定多個觀測埠(Port)於P/G間 3. 模擬該模組的S參數(S-Parameter)
1. 由電路模擬器(如ADS)模擬時域(T-Domain)的結果 2. 由電路模擬器(如ADS)模擬頻域(F-Domain)的結果
3. 分析與取得較具干擾的觀測埠(Port)
1. 導入解耦合電容(Decoupling Capacitor)的解決方案 2. 於具干擾的觀測埠(Port)處加入解耦合電容
是否成功與正確的找出關鍵埠 並有效達到雜訊的抑制?
否
是
圖 5-1：電源完整性設計與驗證流程圖
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