In this dissertation, several types of poly-Si NWTFT with MG configurations, including independent double-gate (DG), tri-gate (TG) and gate-all-around (GAA) were fabricated and characterized. In addition, various applications involving NVM and biosensors by using MG NWTFT are also demonstrated.
This dissertation comprises six chapters. Chapter 1 introduces the background and motivation of this study. Chapter 2 is basically an extension of our previous work [1-82], and more comprehensive investigation and understanding of physical phenomena in independent DG poly-Si NWTFT devices are discussed. Chapter 3 proposes a simple but novel method to fabricate MG NW devices. Chapter 4 shows and compares the impacts of MG configuration on the characteristics of poly-Si NW TFT-SONOS memory. Chapter 5 proposes and discusses a new sensor scheme using poly-Si NWTFT with extended-gate structure for various sensing applications. And Chapter 6 is the conclusions and suggested future work. The detailed content of each chapter is described as follows.
In Chapter 1, an overview of NWs and related potential applications are briefly introduced, including MG transistors, variability issues, NVM devices, and solid-state sensors. The motivation part describes the incentive of utilizing several modified schemes of poly-Si NWTFTs to deal with the problems existing in previous structures, and also to explore their capability for possible applications.
In Chapter 2, the characteristics of a poly-Si NWTFT device with an independent DG configuration under different operation modes are investigated and compared. In the device, the tiny NW channels are surrounded by an inverse-T-shaped gate and a top gate. It is found that the device under DG mode exhibits significantly
better performance in comparison with the two single-gate (SG) modes in terms of a higher current drive over the combined sum of the two SG modes and a smaller subthreshold swing (SS) of less than 100 mV/dec. Origins of such improvement are identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with DG operation.
Moreover, the VTH fluctuation of poly-Si NWTFT devices is also studied in this chapter. The defects existing in the NW channels are identified as one of the major sources for the VTH fluctuation. The passivation of these defects by plasma treatment is shown to be effective for reducing the VTH fluctuation. It is also found that the fluctuation is closely related to the operation modes. When only one of the gates is employed as the driving gate to control the device‟s switching behavior, an optimum bias for the other gate can be found for minimizing the VTH fluctuation.
In Chapter 3, several types of poly-Si NWTFTs with various MG configurations are demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated tri-gated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 108. These results indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel but different gate configurations. The results show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate.
In Chapter 4, we propose a simple and novel way to fabricate poly-Si NW-SONOS devices with various gate configurations. Three types of devices having various gate configurations, namely, side-gated (SG), -shaped gated (G) and
gate-all-around (GAA), are successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest P/E efficiency, largest memory window and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.
In Chapter 5, results of the preliminary study using a novel NWFET sensing scheme featuring an extended sensing gate for various sensing purposes including pH sensing, gas sensing and bio-molecules detection are presented and described. In one of the embodiments of the proposed scheme, the NW channel is gated with two gates, namely, the SENSE-gate and the READ-gate. An antenna-like extended-gate structure acting as a sensing area is connected to the SENSE-gate of the NW device. During measurement the SENSE-gate is used for detecting the targets entities in the test solution. A change in the amount of sensing charges would promptly affect the characteristics of the NW devices which can be effectively monitored with the READ-gate. This scheme takes advantages of EGFET‟s effective isolation of device from chemical and biological environment, and NWFET‟s good switching properties.
The high manufacturability, low fabrication cost and improved reliability make this scheme extremely useful and potential for practical biosensor applications.
Finally, we summarize the conclusions and our major achievements, and also the suggested future work in Chapter 6.
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[1.82] H. H. Hsu, “Fabrication and Characterizations of Poly-Si Nanowire Thin-Film Transistor and SONOS Memory Featuring Inverse-T Gate,” Thesis, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, ROC (2008).
Fig. 1-1 Schematic structures and energy band diagrams of planar single-gated MOSFET (left) and gate-all-around (GAA) NW MOSFET (right).
Apparently the GAA NW structure can provide much better electrostatic control to prevent the lateral electric field penetrating from the drain into the channel region [1.25].
Fig. 1-2 Evolution of the new transistor structure to improve the electrostatics of a MOSFET [1.26].
Fig. 1-3 Schematics of conventional transistor with a top-mounted gate (left) and Intel’s tri-gate transistors with body-tied Si-fin structure (right) [1.28].
Fig. 1-4 Cross-sectional TEM images of gate-all-around twin silicon nanowire SONOS memory [1.54].
Fig. 1-5 Cross-sectional TEM images of (a) Tri-gate structure of the TFT device, (b) Channel-length direction of double-layer TFT NAND devices [1.60].
Fig. 1-6 Schematic cross-section of Toshiba’s BiCS flash memory (right) and its vertical SONOS cell (left) [1.62, 1.63].
Fig. 1-8 Table of ISFET, ChemFET and EnFET structures, detectable analytes, and sensitive membranes with bio-receptors [1.70].
Fig. 1-7 Schematic representation of (a) MOSFET and (b) ISFET [1.68].
Fig. 1-9 An illustrative representation of a sensor scheme built on extended gate field-effect transistor (EGFET).
Fig. 1-10 Size of several nano-materials as compared to the size of some biological entities, such as nucleic acids, proteins, virus, and cells [1.74].