Comparisons of output characteristics normalized to the effective channel width (W) between SG and DG modes are shown in Fig. 2-15 (a). The long-channel device
(L = 5 m) is chosen here in order to eliminate the effect of series resistance on the drain current. It can be noticed that the drain current under DG mode is substantially larger than that of either SG mode. To more carefully illustrate this observation, Fig.
2-15 (b) shows the ratio of drain current of DG mode to the sum of the two SG modes against drain voltage (without normalizing to W). The ratio is found to increase with increasing drain voltage from a value around 1.2, and becomes saturated at around 2.4.
Moreover, the saturation occurs at a smaller drain voltage as VGVTH is reduced.
Similar measurements were also performed on the planar devices having a 50-nm-thick channel, and the results (not shown) show that the ratio is around unity. This suggests that, due to the thick channel film, the two opposite channels in the planar device essentially do not have any coupling during DG operation. In other words, the overlap of wave functions of the induced electrons (or electrostatic potential) in one of the channel with that of the other channel is negligible (as shown in Fig. 2-16 (a)).
In such case, DG operation is simply the combination of two independent SG MOSFETs in parallel. In contrast to the characteristics of the planar device, the tremendous enhancement in current drive of the NW device shown in Fig. 2-15 (a) with DG operation is speculated to originate from the strong coupling effect of the two opposite gates on account of the use of ultra-thin NW channels, as illustrated in Fig. 2-16 (b).
To gain insight into the above phenomenon, we have re-checked the output characteristics of the NW device. In Fig. 2-15 (a), it can be noticed that the drain voltage at the onset of pinch-off (i.e., the saturation drain voltage, VDsat) [2.17] is smaller in SG modes than in DG mode under the same VGVTH condition. We re-plot the ID-VD curves at VGVTH = 4 V in Fig. 2-17 and specify the position of VDsat for each mode as an example. Apparently the abnormally high drain current ratio could
be partly attributed to the lower VDsat in the two SG modes which would limit the saturation current. Such “early saturation” phenomenon in SG modes could also be described by the aforementioned back-gate effect [2.18]. Although previously some analytical I-V models for thin-film SOI devices with back-gate have already been proposed in literatures [2.18-2.20], here we utilize a different approach with the potential distribution diagrams under SG1-mode operation illustrated in Fig. 2-18 to help elucidate thee cause in a much simpler way.
As stated in Table 2-1, in SG1 mode, G2 is grounded while G1 serves as the driving gate. Fig. 2-18 (a) shows the potential distribution in the channel at the source end as VG1 is above VTH. The surface potential (S) of the channel would be pinned at
TH which is the level corresponding to the onset of strong inversion [2.17] and the voltage drop is mainly across G1 oxide. On the other hand, the inversion condition for the onset of pinch-off at the drain side of the channel is S ~ TH + VDsat due to the shift of quasi-Fermi potential with the applied drain bias, as shown in Fig. 2-18 (b) [2.17]. Consequently, VDsat could be easily derived by using the similarity of the triangles formed by the potential line in Fig. 2-18 (a), expressed as:
γ and Table 2-2. VDsat for SG2 mode can be analogically derived with the form similar to Eq. (2-5) except
corresponding to the region (iii) shown in Fig. 2-14 and Table 2-2. By using the gradual-channel and charge-sheet approximation [2.17], the inversion charge density (Qi) along the channel can be described as:
γ)V]
where Cox is the gate oxide capacitance per unit area, and V is the location-dependent quasi-Fermi potential due to the drain bias. Subsequently, by integrating Qi(V) through the entire channel with the integral equation form:
then the drain current (ID) at ON state can be derived and written as:
D back-gate effect under DG operation as long as the channel body is floating. Although the above derivation is based on the simple potential diagrams shown in Fig. 2-18, the result is actually consistent with the theoretical models presented previously [2.19, 2.20]. As compared with the commonly used drain current equation for bulk MOSFETs [2.17], Eq. (2-8) and Eq. (2-9) only replace the body-effect coefficient (m) with 1 + . Since it has been known that m and 1 + correlate to subthreshold swing in a same manner (~dVG/dS) [2.13, 2.17], the above derivation indicates that the impact of back-gate effect on the fully-depleted DG SOI device characteristics is similar to that of the body-effect on the conventional bulk MOSFET.
In addition, by applying the value (extracted from the point of VTH-control gate = 0 V in Fig. 2-19) for each SG mode into Eq. (2-8) and Eq. (2-9), interestingly, it is found that the measured output characteristics can be well fitted by the equations
as an appropriate K value is used in each operation mode. Such treatments are shown in Fig. 2-20, in which the output characteristics measured under different operation modes are compared with the computational I-V curves based on Eq. 8) and Eq. (2-9). The K values used in the computational I-V curves are 4.9×10-8, 4.65×10-8, and 1.15×10-7 S/V, for SG1, SG2, and DG modes, respectively. As can be seen in the figures, the calculation results well describe the experimental data.
The above analysis clearly explains the reason for the much higher VDsat of DG