Retention characteristics of SG, ΩG and GAA NW-SONOS devices after single and 10k P/E cycles at room temperature (25 ºC) are shown in Figs. 4-23 (a), (b), and (c), respectively. The P/E bias conditions in the retention test are identical to those in the endurance test. Among the three types of NW devices, GAA split retains the largest memory windows of about 1.7 V and 1 V, respectively, after 10 years for the devices after single and 10k P/E cycles of operation. The major reason for the shrinkage in window size is the lowering in VTH of the programmed state. Since the VTH decay rate in the programmed state for 10k P/E-stressed device shows similar trend compared with that for the singly-stressed device at room temperature, the trap-to-band tunneling is considered to be the major charge loss mechanisms in the excess electron state (programmed state) rather than trap-to-trap tunneling [4.19]. On the other hand, the VTH of the erased state for the device after 10k P/E cycles shows larger positive shift with time than that of the device after single cycle of P/E operation. This is attributed to the de-trapping of trapped holes in the tunneling oxide near the channel surface resulted during the P/E operations [4.27].
Fig. 4-24 shows the retention behaviors of GAA devices at 85 ºC. The VTH
decay rate in the programmed state is observed to be greater than that at room
temperature, leading to a reduced memory window for the 10-year projection. This indicates the emission of trapped electrons from the storage nitride is accelerated by the thermal-activated process [4.28]. Since the energy level of the hole traps is relatively deep in the nitride and the de-trapping of holes contained in the tunneling oxide is mainly via tunneling mechanism [4.28], the VTH shift rate of the erased state should be insensitive to the temperature for both singly and 10k P/E-stressed devices, as shown in Figs. 4-23 (c) and 4-24.
4-7 Summary
In this chapter, we have investigated the characteristics of poly-Si NW-SONOS devices with various gate configurations fabricated with an ingenious scheme. As compared with the planar counterpart, the NW devices can be operated with a much reduced P/E voltage which is essential for the demand of green electronics. This is attributed to the enhanced gate controllability with MG configuration as well as the use of ultra-thin NW structure with a reduced amount of defects in the channel.
Among the three types of NW devices, GAA split shows the best performance in terms of the highest ON-current, the steepest SS, the highest P/E efficiency, the largest memory window, as well as the best endurance and retention characteristics.
This is ascribed to the increase in the electric field strength at the NW/tunneling oxide interface resulting from the large curvature as well as the reduced variation in the curvature value. Hence GAA device possesses the most prominent performance among the different types of devices characterized in the study.
More importantly, the NW-SONOS fabrication process used in this study can be
easily implemented in modern flat-panel manufacturing without resorting to costly advanced lithography. Based on the results obtained in this chapter, the proposed method for fabricating MG poly-Si NW-SONOS devices appears to be very promising for the realization of SOP in the future.
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Fig. 4-1 (a) Schematic structure of a conventional n-type SONOS memory device.
(b) Influence of trapped charges on VTH of the SONOS memory device.