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Since the independent gate configuration is capable of providing more than one operation mode, in this sub-section we also address the VTH fluctuation issues under these different operation modes. The bias conditions of the two independent gates for the three operation modes studied in this sub-section are given in Table 2-1. Fig. 2-35 shows and compares the mean values and standard deviations of VTH and SS for plasma-treated devices with channel length of 2 m under three different operation modes. It is evident that the device operating in DG mode has the smallest variation among the three operation modes in terms of VTH and SS. This is due to the fact that the DG operation mode can further reduce the effective depletion width WDeff in

the NW channel. As illustrated in Fig. 2-36 [2.31], for a fully-depleted poly-Si channel with SG configuration (Fig. 2-36 (b)), the WDeff in Eq. (2-19) and Eq. (2-20) can be replaced by the channel thickness Tsi. As for MG configuration, WDeff could be even smaller. For example, in the DG configuration shown in Fig. 2-36 (c), WDeff is equal to half the Tsi, thus leading to more improved fluctuation characteristics.

Consequently, the experimental results shown in Fig. 2-35 essentially reflect the importance of gate controllability as well as channel thickness to device variation properties.

In addition, with regards to the flexible device operation, it is intriguing to investigate VTH fluctuation characteristics under SG mode with various VTH-control gate biases. Fig. 2-37 (a) shows typical ID-VG curves of 20 devices measured in SG1 mode with different applied G2 voltages (VG2). Fig. 2-37 (b) summarizes the VTH as a function of VG2 for devices with channel length ranging from 0.8 m to 5 m. It is observed that the smallest fluctuation is achieved as VG2 is in the range between 0 V and -1 V, while the fluctuation worsens as VG2 shifts toward either more negative or positive direction. This is because when VG2 is shifted away from the optimum bias condition, the transverse electric field inside the NW would increase and thus the impact of channel film-thickness variation on the modulation of the channel potential would be magnified, leading to a larger VTH variation [2.32]. Moreover, the fluctuation under large VG2 also worsens as the channel length shortens (Fig. 2-37 (b)).

The reason is that, when applying a sufficiently high positive VG2, the position of the onset of inversion layer formation would move toward the channel surface adjacent to G2, and it requires a more negative G1 bias to turn the device off (e.g., see Fig. 2-37 (a)). Under this situation, G1 oxide and the fully depleted channel body form the effective gate dielectric, which is certainly thicker than the nominal gate oxide. Hence,

the aggravated short-channel effects combined with the enhanced influence of channel thickness variation bring about a much greater VTH fluctuation in short-channel devices. As a result, it is concluded that the optimum bias condition occurs as the transverse electric field in the NW channel approaches zero [2.32].

2-6 Summary

In this chapter, characteristics of poly-Si NW devices featuring an independent DG configuration are characterized and analyzed. In the devices the ultra-thin NW channels are surrounded by an inverse-T gate and a top gate. With the independent DG scheme, several modes including DG and two SG modes can be implemented in the device operation. In addition, because of the strong gate-to-gate coupling due to ultra-thin NW channels, the transfer characteristics of the device driven by one of the gates are profoundly affected by the bias condition of the other gate. Therefore the DG-NWTFT can act as a functional device by applying separate biases to the two gates simultaneously, allowing the flexibility to adjust VTH. The experimental results point out that the DG mode outperforms either of the two SG modes. For example, transfer curves with SS less than 100 mV/dec are only seen with the DG mode. The anomalous leakage current shown in SG1 and DG mode is attributed to GIDL mechanism. A simulation analysis with gate/drain overlap structure and vertically non-uniform S/D doping profile is performed to clarify this outcome. The simulation result shows that BTBT occurs more significantly in the drain region with lower doping concentration. According to the corresponding structure and doping condition, the experimental result of OFF-state leakage can be properly explained by the

simulation analysis.

Extraordinary enhancement in the current drive with DG mode is also observed.

Based on the analysis, the above current enhancement with DG mode is mainly because of the elimination of the back-gate effect encountered in SG mode, as well as the improved effective mobility. Beside, the impacts of operation mode on device’s series resistance are also investigated. The effect of grain-boundary barrier lowering may also reduce the spreading resistance, leading to a lower series resistance under DG mode.

For device variability, it is confirmed that defects contained in the channel are the dominant source for the fluctuation observed in NW DG-TFTs. Experimental results in this study also show that these defects can be effectively passivated with NH3 plasma treatment, therefore reducing the device fluctuation in terms of VTH. Additionally, it is found that the fluctuation is closely related to the operation modes.

When only one of the gates is employed as the driving gate to control the device’s switching behavior, suppressing the VTH fluctuation by optimizing the bias to the VTH -control gate under SG mode is demonstrated in this study.

References

[2.1] D. Hisamoto, W. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asana, T.

King, J. Bokor, and C. Hu, “A Folded Channel MOSFET for Deep-Sub-Tenth Micron Era,” IEDM Tech. Dig., pp.1032-1034 (1998).

[2.2] J. Fu, N. Singh, C. Zhu, G. Q. Lo, and D.-L. Kwong, “Integration of High-k Dielectrics and Metal Gate on Gate-All-Around Si-Nanowire-Based Architecture for High-Speed Nonvolatile Charge-Trapping Memory,” IEEE Electron Device Lett., vol. 30, no. 6, pp.662-664 (2009).

[2.3] E. Stern, A. Vacic, and M. A. Reed, “Semiconducting Nanowire Field-Effect Transistor Biomolecular Sensors,” IEEE Trans. Electron Devices, vol. 55, no.

11, pp.3119-3130 (2008).

[2.4] Y. Cui, Q. Wei, H. Park, and C. M. Lieber, “Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species,”

Science, vol. 293, no. 5533, pp.1289-1292 (2001).

[2.5] Y. Wu, Y. Cui, L. Huynh, C. J. Barrelet, D. C. Bell, and C. M. Lieber,

“Controlled Growth and Structures of Molecular-Scale Silicon Nanowires,”

Nano Lett., vol. 4, no. 3, pp.433-436 (2004).

[2.6] F. L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, S. D. Liu, C. C. Huang et al.,

“5nm-Gate Nanowire FinFET,” Tech. Dig. VLSI Technol., pp.196-197 (2004).

[2.7] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H.

Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 nm) Gate-All-Around CMOS Devices,” IEEE Electron Device Lett., vol. 27, no. 5,

pp.383-386 (2006).

[2.8] H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, “A Simple and Low-Cost Method to Fabricate TFTs with Poly-Si Nanowire Channel,” IEEE Electron Device Lett., vol. 26, no. 9, pp.643-645 (2005).

[2.9] H. C. Lin, M. H. Lee, C. J. Su and S. W. Shen, “Fabrication and Characterization of Nanowire Transistors with Solid-Phase Crystallized Poly-Si Channels,” IEEE Trans. Electron Devices, vol. 53, no. 10, pp.2471-2477 (2006).

[2.10] M. Im, J.-W. Han, H. Lee, L.-E.. Yu, S. Kim, S. C. Jeon, k. h. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y.-K. Choi, “Multiple-Gate CMOS Thin-Film Transistor with Polysilicon Nanowire,” IEEE Electron Device Lett., vol.

29, no. 1, pp.102-104 (2008).

[2.11] H. C. Lin, H. H. Hsu, C. J. Su and T. Y. Huang, “A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate,”

IEEE Electron Device Lett., vol. 29, no. 7, pp.718-720 (2008).

[2.12] H. K. Lim and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-On-Insulator (SOI) MOSFET's,” IEEE Trans. Electron Devices, vol. 30, no. 10, pp.1244-1251 (1983).

[2.13] M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T.

Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki,

“Demonstration, Analysis and Device Design Considerations for Independent Double-Gate MOSFETS,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp.2046-2053 (2005).

[2.14] J. G. Fossum and A. Ortiz-Conde, “Effects of Grain Boundaries on the Channel Conductance of SOI MOSFET's,” IEEE Trans. Electron Devices, vol.

30, no.8, pp.933-940 (1983).

[2.15] F. J. G. Ruiz, A. Godoy, F. Gámiz, C. Sampedro, and L. Donetti, “A Comprehensive Study of the Corner Effects in Pi-Gate MOSFETs Including Quantum Effects,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp.3369-3377 (2007).

[2.16] ISE TCAD Rel. 10.0 Manual, DESSIS, Zurich, Switzerland (2004).

[2.17] Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices,”

Cambridge University Press (1998).

[2.18] J. P. Colinge, “Silicon on Insulator Technology: Materials to VLSI,” Boston, MA: Kluwer Academic Publishers (1997).

[2.19] H. K. Lim and J. G. Fossum, “Current-Voltage Characteristics of Thin-Film SOI MOSFET’s in Strong Inversion,” IEEE Trans. Electron Devices, vol. 31, no. 4, pp.401-408 (1984).

[2.20] D. D. Lu, M. V. Dunga, C. H. Lin, A. M. Niknejad and C. Hu, “A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation,” IEDM Tech. Dig., pp.565-568 (2007).

[2.21] John Y. W. Seto, “The Electrical Properties of Polycrystalline Silicon Films,”

J. Appl. Phys., vol. 46, pp.5247-5254 (1975).

[2.22] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.

Rider, “Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors,” J. Appl. Phys., vol. 53, pp.1193-1202 (1982).

[2.23] F. V. Farmakis, J. Brini, G. Kamarinos, C. T. Angelis, C. A. Dimitriadis, and M. Miyasaka, “On-Current Modeling of Large-Grain Polycrystalline Silicon Thin-Film Transistors,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp.701-706 (2001).

[2.24] G. Ghibaudo, “Critical MOSFETs Operation for Low Voltage & Low Power IC's: Ideal Characteristics, Parameter Extraction, Electrical Noise and RTS Fluctuations,” Microelectrronic Engineering, vol.39, pp.31-57 (1997).

[2.25] Z. M. Lin, H. C. Lin, W. C. Chen and T. Y. Huang, “Insight into the Performance Enhancement of Double-Gated Polycrystalline Silicon Thin-Film Transistors with Ultrathin Channel,” Appl. Phys. Lett., vol. 91, 202113 (2007).

[2.26] A. Asenov, “Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1μm MOSFET’s: A 3-D Atomistic Simulation Study,”

IEEE Trans. on Electron Devices, vol. 45, no. 12, pp.2505-2513 (1998).

[2.27] K. Takeuchi, T. Tatsumi and A. Furukawa, “Channel Engineering for the Reduction of Random-Dopant-Placement-Induced Threshold Voltage Fluctuation,” IEDM Tech. Dig., pp.841-844 (1997).

[2.28] H. C. Lin, K. L. Yeh, M. H. Lee, W. Lee, W. J. Lin and T. Y. Huang,

“Ambipolar Schottky Barrier Poly-Si Thin-Film Transistors with Narrow Channel Width for Improved Performance,” Proceedings of AMLCD, pp.247-250 (2003).

[2.29] F. S. Wang, M. J. Tsai, and H. C. Cheng, “The Effects of NH3 Plasma Passivation on Polysilicon Thin-Film Transistors,” IEEE Electron Device Lett., vol.16, no.11, pp.503-505 (1995).

[2.30] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp.1433-1439 (1989).

[2.31] Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi and A. Nitayama, “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory,” IEDM Tech. Dig., pp.449-452 (2007).

[2.32] K. Takeuchi, R. Koh and T. Mogami, “A Study of the Threshold Voltage Variation for Ultra-Small Bulk and SOI CMOS,” IEEE Trans. on Electron Devices, vol. 48, no. 9, pp.1995-2001 (2001).

Fig. 2-1 (a) Top view and (b) 3-D structure of the novel poly-Si NWTFT featuring spacer-like NW channels and single side-gate configuration.

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