The S/D of sample B was activated by 900℃ for 60 seconds, and Id-Vg curve and Is-Vg curve of multi-bit operation are shown in Fig. 4-4. It is found that this memory device can be operated by the Vt modulation and the GIDL current modulation. It should be noted that the Vt modulation on sample B is the movement of the whole subthreshold curve. We infer that there is no barrier between the S/D and the channel while applying +16V to the gate so that a lot of electrons pass through the tunneling oxide into the trapping layer above the channel center. The S/D of sample A was activated at 900℃ for 20 seconds. The Id-Vg curve and Is-Vg curve of the multi-bit operation are shown in Fig. 4-5. It should be noted that the Vt modulation is the movement of the upper half subthreshold curve. According to the simulated results of chapter 3, we can infer that the stored charges in the trapping layer are positioned above the channel and near the S/D junctions. We suspect that there is an electron barrier between the S/D and the inverted channel while applying +14V to the gate so that only few electrons can pass through this barrier and be injected to the trapping
layer above the channel center.
Therefore, we can infer that the S/D junctions do not overlap with the gate electrode on sample A because the S/D annealing time is only 20 seconds so that the lateral diffusion of the S/D dopants is not long enough. On the other hand, the S/D junctions overlap with the gate electrode on sample B because the S/D annealing time is 60s so that the S/D dopants diffuse to the underneath of the gate electrode.
The modulation of the whole subthreshold curve, the modulation of the upper half subthreshold curve and the modulation of the GIDL current are presented by combining the I-V curves of sample A with sample B. Therefore, we can demonstrate the effects of the stored-charge distribution on the device characteristics as shown in chapter 3. In addition, we demonstrate that this multi-bit operation is practicable.
4-3-1 Sample B and C: Sufficient gate to source/drain overlap
At the beginning, the trapping layer on sample B was divided into 3 regions laterally as shown in Fig. 4-6. They are Region 1 “above drain junction”, Region 2
“above channel center”, and Region 3 “above source junction”.
The Id-Vg curve and Is-Vg curve of the multi-bit operation on sample B have been shown in Fig. 4-4. How to operate this 3-bits memory device is explained as follows. First, we let the electrons from the gate tunnel into the trapping layer by applying -16V to the gate and 0V to the S/D, and then we call it the 1st state. The electrons are stored at Region 1 and 3, so the GIDL current increase largely on the forward read operation or the reverse read operation. However, only few electrons were injected into Region 2 which resulted in small Vt shift. Then, the voltage (+11V) was applied to the drain and the voltage (0V) was applied to the gate and the source so that the 2nd state can be obtained. During the 2nd operation, the electrons stored at Region 1 tunneled through the tunneling oxide into the drain due to the high drain
voltage (+11V) so the GIDL current on the forward read could be reduced. Next, the 3rd state was achieved by applying +11V to the source and 0V to the gate and the drain, and then the stored charges at Region 3 could tunnel through the tunneling oxide to the source which results in the reduction of the GIDL current on the reverse read. Afterward, in order to restore charges at Region 1 and 3, the gate was biased at -16V, and the S/D was biased at 0V. After that, the voltage (+11V) biased to the source to reduce charges stored at Region 3, and then we obtained the 4th state which the GIDL current was large on the forward read and was small on the reverse read.
Then, the drain was biased at +11V to reduce the charges stored at Region 1. Next, the gate was biased at +16V and the S/D were biased at 0V. The electrons were injected from the S/D into Region 1, 2 and 3, and then the 5th state was achieved.
Since the S/D overlap with the gate, there is no barrier between the S/D and the channel while applying +16V to the gate so that a lot of electrons passed through the tunneling oxide into the center of trapping layer, Region 2. It is obvious that whole subthreshold curve was moved to the right because of the charges stored at Region 2.
Then, we apply voltage (+11V) to the drain or the source to decrease the charges stored at Region 1 or 3 respectively, and then it resulted in the 6th, 7th and 8th state.
In addition, the charges stored at Region 2 can be reduced by applying high negative voltage to the gate and 0V to the S/D. Table 4-1 summarizes the 8 states of Id-Vg and Is-Vg characteristic of the memory device on sample B.
The S/D of sample C activated by 900℃ for 180 seconds, and Id-Vg curve of multi-bit operation is shown in Fig. 4-7. Since the S/D annealing time for sample C is 180s, the S/D junctions overlap with the gate. Therefore, the Id-Vg characteristics of sample C are similar to sample B so that we demonstrated the basic memory performances only for sample B.
4-3-2 Sample A: Insufficient gate to source/drain overlap
At the beginning, we divided the trapping layer on sample A into five regions laterally such as shown in Fig. 4-8. They are Region 1 “above drain junction”, Region 2 “above channel and near drain junction”, Region 3 “above channel center”, Region 4 “above channel and near source junction”, and Region 5 “above source junction”.
The Id-Vg curve and Is-Vg curve of the multi-bit operation on sample A have been shown in Fig. 4-5. The operation of the 3-bits memory device is explained as follows. First, due to the crystallized Al2O3 blocking layer, we let electrons from the gate tunnel into the trapping layer by applying -16V to the gate and 0V to the S/D, and then we call it the 1st state. Because the electric field between the gate and the S/D is larger than the electric field between the gate and the channel, the electrons were injected from the gate into Region 1 and 5. Since the electrons are stored at Region 1 and 5, the GIDL current increase largely on both forward read operation and reverse read operation. However, only few electrons were injected into Region 1, 2, and 3 and then resulted in small Vt shift. Then, the voltage (+10V) was applied to the drain and the voltage (0V) was applied to the gate and the source so the 2nd state can be obtained.
During the 2nd operation, the electrons stored at Region 1 tunneled through the tunneling oxide into the drain due to the high drain voltage (+10V) so the GIDL current of the forward read could be reduced. Next, the 3rd state was achieved by applying +10V to the source and 0V to the gate and the drain, and then the stored charges at Region 5 could tunnel through the tunneling oxide into the source which resulted in the reduction of the GIDL current on the reverse read. Afterward, in order to let Region 1 and 5 restore charges, the gate was biased at -16V, and the S/D was biased at 0V. After that, the voltage (+10V) biased to the source to reduce charges stored at Region 5, and then we obtained the 4th state which the GIDL current was large on the forward read and was small on the reverse read. Then, the drain is biased
to +10V to reduce the charges stored at Region 1. Next, the gate was biased at +14V and the S/D were biased at 0V. The electrons were injected from the S/D into Region 1, 2, 4 and 5, and then the 5th state was achieved. Since the S/D does not overlap with the gate, there is the electron barrier between the S/D and the channel while applying +14V to the gate. Therefore, only few electrons passed through this barrier into the center of trapping layer, Region 3. From the results of the simulations in chapter 3, it is obvious that the upper half subthreshold curve is moved to the right because of the charges stored at Region 2 and 4. Then, we applied the voltage (+10V) to the drain or the source to decrease the charges stored at Region 1 or 5 respectively, and it resulted in the 6th, 7th and 8th state.
In addition, the charges stored at Region 2 and 5 can be reduced by applying high negative voltage to the gate and 0V to S/D. Table 4-2 summarizes the 8 states of Id-Vg and Is-Vg characteristic of the memory device on sample A.