Although the feasibility of 3-bit per cell memory is proved, the device dimension with the gate length of 2μm is too large in this study. Nowadays, the memory device is already scaled down to 45nm in the production. Therefore, the device dimension of this 3-bit per cell memory requires scaling down.
To improve the retention performance of the GIDL current modulation, there are three possible solutions. First one is extending the Al2O3 blocking layer to the underneath of the spacer. It can prevent the vertical escape of the stored charges.
Second one is replacing the HfO2 trapping layer by HfAlO because HfAlO shows
better retention performance than HfO2 [42]. The last one is changing the trapping layer into nano-crystal structure.
The poor endurance performance also requires improvement. If the degradation of the endurance performance is due to the change of the stored charges distribution after every P/E cycle, one possible solution is to increase the S/D junction breakdown voltage. Therefore, the higher S/D voltage can be adopted during the erase operation, and then the stored charges can be totally removed. The other method is by varying the thickness of the gate dielectric and modulating the position of S/D junctions to optimize the endurance performance.
Finally, in order to reduce the drain disturbance effect, the gate voltage needs to increase. Therefore, how to reduce channel hot electron injection is an issue needed to be solved.
References
[1] Y. S. Shin, “Non-volatile memory technologies for beyond 2010,” in Proc. Symp.
VLSI Circuits Tech. Dig., 2005, pp. 156-159.
[2] J. M. Slaughter, R. W. Dave, M. Durlam, G. Kerszykowski, K. Smith, K. Nagel, B. Feil, J. Calder, M. DeHerrera, B. Garni, and S. Tehrani, “High speed toggle MRAM with MgO-based tunnel junctions,” in IEDM Tech. Dig., 2005, pp.
873-876.
[3] C. C. Hung, Y. S. Chen, D. Y. Wang, Y. J. Lee, W. C. Chen, Y. H. Wang, C. T.
Yen, S. Y. Yang, K. H. Shen, C. P. Chang, C. S. Lin, K. L. Su, H. C. Cheng, Y. J.
Wang, D. D. L. Tang, M. J. Tsai, and M. J. Kao, “Adjacent-reference and self-reference sensing scheme with novel orthogonal wiggle MRAM cell,” in IEDM Tech. Dig., 2006, pp. 334-337.
[4] T. Nakamura, Y. Fujimori, N. Izumi, and A. Kamisawa, “Fabrication technology of ferroelectric memories,” Jpn. J. Appl. Phys., vol. 37, no. 3B, pp. 1325-1327, Mar. 1998.
[5] R. Moazzami, “Ferroelectric thin film technology for semiconductor memory,”
Semicond. Sci. Technol., vol. 10, no. 4, pp. 375-390, Apr. 1995.
[6] N. Yamada, E. Ohno, K. Nishiuchi, N. Akahira, and M. Takao, “Rapid-phase transitions of GeTe-Sb2Te3 pseudobinary amorphous thin films for an optical disk memory,” J. Appl. Phys., vol. 69, no. 5, pp. 2849-2856, Mar. 1991.
[7] S. Lai and T. Lowrey, “OUM – a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications,” in IEDM Tech. Dig., 2001, pp. 803-806.
[8] I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D. S. Suh, J. C. Park, S. O.
Park, H. S. Kim, I. K. Yoo, U. I. Chung, and J. T. Moon, “Highly scalable
non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses,” in IEDM Tech. Dig., 2004, pp. 587-590.
[9] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D. S. Suh, Y. S. Joung, I. K. Yoo, I. R.
Hwang, S. H. Kim, I. S. Byun, J. S. Kim, J. S. Choi, and B. H. Park,
“Reproducible resistance switching in polycrystalline NiO films,” Appl. Phys.
Lett., vol. 85, no. 23, pp. 5655-5657, Dec. 2004.
[10] S. Seo, M. J. Lee, D. H. Seo, S. K. Choi, D. S. Suh, Y. S. Joung, I. K. Yoo, I. S.
Byun, I. R. Hwang, S. H. Kim, and B. H. Park, “Conductivity switching characteristics and reset currents in NiO films,” Appl. Phys. Lett., vol. 86, no. 9, p. 093509, Feb. 2005.
[11] M. Fujimoto, H. Koyama, M. Koyama, M. Konagai, Y. Hosoi, K. Ishihara, S.
Ohnishi, and N. Awaya, “TiO2 anatase nanolayer on TiN thin film exhibiting high-speed bipolar resistive switching,” Appl. Phys. Lett., vol. 89, no. 22, p.
223509, Nov. 2006.
[12] D. Lee, H. Choi, H. Sim, D. Choi, H. Hwang, M. J. Lee, S. A. Seo, and I. K. Yoo,
“Resistance switching of the nonstoichiometric zirconium oxide for nonvolatile memory application,” IEEE Electron Device Lett., vol. 26, no. 10, pp. 719-721, Oct. 2005.
[13] C. Y. Lu, T. C. Lu, and R. Liu, “Non-volatile memory technology-today and tomorrow,” in Proc. IEEE-IPFA, 2006, pp. 18-23.
[14] W. N. Papian, “The MIT magnetic-core memory,” in Proc. Eastern Joint Comp.
Conf., Dec. 1953, pp. 37-42.
[15] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, no. 4, pp. 1288-1295, 1967.
[16] J. D. Blauwe, “Nanocrystal nonvolatile memory devices,” IEEE Trans.
Nanotechnol., vol. 1, no. 1, pp. 72-77, Mar. 2002.
[17] P. Pavan, R. Bez, P. Olivo, and E. Zanomi, “Flash memory cells—an overview,”
Proc. IEEE, vol. 85, no. 8, pp. 1248-1271, Aug. 1997.
[18] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22-31, Jul. 2000.
[19] Process Integration, Devices and Structures in International Technology Roadmap for Semiconductors, pp. 35-36, 2007.
[20] D. Frohman-Bentchkowsky, and M. Lenzlinger, “Charge transport and storage in metal-nitride-oxide-silicon (MNOS) structures,” J. Appl. Phys., vol. 40, no. 8, pp.
3307-3319, Jul. 1969.
[21] D. Frohman-Bentchkowsky, “The metal-nitride-oxide-silicon (MNOS) transistor
－characterisctics and applications,” Proc. IEEE, vol. 58, no. 8, pp. 1207-1219, Aug. 1970.
[22] J. Bu, and M. H. White, “Effects of two-step high temperature deuterium anneals on SONOS nonvolatile memory devices,” IEEE Electron Device Lett., vol. 22, no. 1, pp.17-19, Jan. 2001.
[23] K. T. Chang, W. M. Chen, C. Swift, J. M. Higman, W. M. Paulson, and K. M.
Chang, “A new SONOS memory using source-side injection for programming,”
IEEE Electron Device Lett., vol. 19, no. 7, pp. 253-255, Jul. 1998.
[24] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-k charge trapping layer,” in VLSI Symp. Tech. Dig., 2003, pp. 27-28.
[25] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. J. King, “FinFET SONOS flash memory for embedded applications,” in IEDM Tech. Dig., 2003, pp. 609-613.
[26] C. H. Lee, J. Choi, C. Kang, Y. Shin, J. Sel, J. Sim, S. Jeon, B. I. Choe, D. Bae, K.
Park, and K. Kim, “Multi-level NAND flash memory with 63 nm-node TANOS (Si-Oxide-SiN-Al2O2-TaN) cell structure,” in VLSI Symp. Tech. Dig., 2006, pp.
21-22.
[27] H. T. Luo, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J.
Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, “BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability,” in IEDM Tech. Dig., 2005, pp. 547-550.
[28] H. T. Luo, S. Y. Wang, Y. H. Hsiao, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Reliability model of bandgap engineered SONOS (BE-SONOS),” in IEDM Tech. Dig., 2006, pp. 495-498.
[29] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/A12O3 with TaN metal gate for multi-giga bit flash memories,” in IEDM Tech. Dig., 2003, pp. 613-616.
[30] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories- Part I: device design and fabrication,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606-1613, Sep. 2002.
[31] T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, “Design optimization of metal nanocrystal memory- Part I: nanocrystal array engineering,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3095-3102, Dec.
2006.
[32] J. J. Lee and D. L. Kwong, “Metal nanocrystal memory with high-κ tunneling barrier for improved data retention,” IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 507-511, Apr. 2005.
[33] S. Choi, S. S. Kim, M. Chang, H. Hwang, S. Jeon, and C. Kim, “Highly thermally stable TiN nanocrystals as charge trapping sites for nonvolatile memory device applications,” Appl. Phys. Lett., vol. 86, no. 12, p. 123110, Mar.
2005.
[34] M. She and T. J. King, “Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1934-1940, Sep. 2003.
[35] S. T. Kang, J. Yater, C. Hong, J. Shen, N. Ellis, M. Herrick, H. Gasquet, W.
Malloch, and G. Chindalore, “Si Nanocrystal Split Gate Technology Optimization for high performance and reliable embedded microcontroller applications,” in Proc. Non-Volatile Semiconductor Memory Workshop, 2008, pp.
59-60.
[36] K. Kim, J. H. Choi, J. Choi, and H. S. Jeong, “The future prospect of nonvolatile memory,” in Proc. Int. Symp. VLSI-TSA, 2005, pp. 88-94.
[37] R. Waser, “Resistive non-volatile memory devices (Invited Paper),”
Microelectronic Engineering, vol. 86, no. 7-9, pp. 1925-1928, 2009.
[38] A. Padilla, S. Lee, D. Carlton, and T. J. K. Liu, “Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method,” in VLSI Symp. Tech. Dig., 2008, pp. 142-143.
[39] E. Lusky, Y. Shacham-Diamand, G. Mitenberg, A. Shappir, I. Bloom, and B.
Eitan, “Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 444-451, Mar. 2004.
[40] A. Padilla, K. Shin, T. J. K. Liu, J. W. Hyun, I. Yoo, and Y. Park, “Dual-bit gate-sidewall storage FinFET NVM and new method of charge detection,” IEEE Electron Device Lett., vol. 28, no. 6, pp. 502-505, Jun. 2007.
[41] A. Padilla and T. J. K. Liu, “Dual-bit SONOS FinFET non-volatile memory cell and new method of charge detection,” in Proc. Int. Symp. VLSI-TSA, 2007, pp.
24-25.
[42] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-κ HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp. 889-892.
[43] C. H. Lai, A. Chin, H. L. Kao, K. M. Chen, M. Hong, J. Kwo, and C. C. Chi,
“Very low voltage SiO2/HfON/HfAlO/TaN memory with fast speed and good retention” in VLSI Symp. Tech. Dig., 2006, pp. 44-45.
[44] C. H. Lee, K. C. Park, and K. Kim, “Charge-trapping memory cell of SiO2/SiN/high-k dielectric Al2O3 with TaN metal gate for suppressing backward-tunneling effect,” Appl. Phys. Lett., vol. 87, no. 7, p. 073510, Aug.
2005.
[45] S. Maikap, P. J. Tzeng, L. S. Lee, H. Y. Lee C. C. Wang, P. H. Tsai, K. S.
Chang-Liao, W. J. Chen, K. C. Liu, P. R. Jeng, and M. J. Tsai, “High-κ Hf-based charge trapping layer with Al2O3 blocking oxide for high-density flash memory,”
in Proc. Int. Symp. VLSI-TSA, 2006, pp. 36-37.
[46] S. Maikap, P. J. Tzeng, S. S. Tseng, T. Y. Wang, C. H. Lin, H. Y. Lee, C. C.
Wang, T. C. Tien, L. S. Lee, P. W. Li, J. R. Yang, and M. J. Tsai, “High-κ HfO2/TiO2/HfO2 multilayer quantum well flash memory devices,” in Proc. Int.
Symp. VLSI-TSA, 2007, pp. 18-19.
[47] S. Maikap, H. Y. Lee, T. Y. Wang, P. J. Tzeng, C. C. Wang, L. S. Lee, K. C. Liu, J. R. Yang, and M. J. Tsai, “Charge trapping characteristics of atomic-layer-deposited HfO2 films with Al2O3 as a blocking oxide for high-density non-volatile memory device applications,” Semicond. Sci. Technol., vol. 22, no. 8, pp. 884-889, Aug. 2007.
[48] Sentaurus-TCAD Mannuls
[49] B. Y. Tsui and C. P. Lin, “A novel 25-nm modified Schottky-barrier FinFET with high performance,” IEEE Electron Device Lett., vol. 25, no. 6, pp. 430-433, Jun.
2004.
[50] J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, “Subbreakdown drain leakage current in MOSFET,” IEEE Electron Device Lett., vol. 8, no. 11, pp.
515-517, Nov. 1987.