The initial memory window of the Vt modulation is divided into the small memory window and the large memory window. The large memory window means that the crowded charges are stored in the trapping nodes. The crowded charges easily encounter strong Coulomb repulsive force between the charges. The strong Coulomb repulsive force will discharge the charges stored in the trapping nodes quickly and increase the charge loss rate. Therefore, when we evaluate the retention performance by extrapolating to 10 years, the large memory window may have worse performance.
For this reason, we also evaluate retention performance of the small memory window.
4-5-1 Sample B: Sufficient gate to source/drain overlap
Fig. 4-18 shows the retention characteristics of the Vt on sample B at 25℃
and 85℃. The small memory window was achieved by the low program voltage, and
the retention performances were evaluated at both 25℃ and 85℃. After 105 seconds, the small memory window still maintained the same level at 25℃, and the stored charges were almost reserved while extrapolating to 10 years. The retention characteristic of the small memory window at 85 ℃ showed poorer retention performance than at 25℃, but it is still good. Only 27% charges were lost at 85℃
after 105 seconds. Extrapolating to 10 years, more than 55% charges are reserved at 85℃.
The large memory window is about 4.5V and is achieved by the high program voltage. After 105 seconds, the large memory window narrowed 14% at 25℃. After 10 years retention time at 25℃, the remained memory window is about 3V. On the other hand, 35% charges were lost at 85℃ after 105 seconds, and the remained memory window is about 1.5V while extrapolating to 10 years.
The Vt shift on sample B is as a result of the charges stored in trapping layer above the channel center, so the lateral charge migration effect [24] is small.
Therefore, the retention performance of the Vt on sample B is very good.
The retention characteristics of the GIDL current on sample B are evaluated at both 25℃ and 85℃ as shown in Fig. 4-19. The GIDL current is measured at constant gate voltages of -7V as the drain voltage is fixed at +1V. Then, we can have the initial memory window about two orders of magnitude. At the beginning, the current ratio between the program state and the erase state was about 90. After 105 seconds, the current ratio reduced to 20 at 25℃. Extrapolating to 10 years, the current ratio is only 2. In addition, the retention performance at 85 ℃was much poorer than at 25℃. In summary, the retention performance of the GIDL current on sample B is poor. The possible reasons are discussed as follows. As we have inferred, the S/D junctions overlap with the gate on sample B. However, the overlap region is quite small because the S/D annealing time is only 60 seconds. In order to modulate the GIDL current, the
positions of the stored charges must be above S/D junctions so they may be near the corner of the spacer. At the corner of the spacer, there are a lot of defects generated from the device fabrication process. These defects will enhance the charge loss rate.
The other reason is due to “lateral charge migration” [24]. When the charges are stored in the HfO2 trapping layer at the source side or the drain side, the charges will move toward the trapping site above the channel center, and then the retention performance will degrade [24].
4-5-2 Sample A: Insufficient gate to source/drain overlap
Fig. 4-20 shows the retention characteristics of the Vt on sample A at 25℃ and 85℃. The small memory window is about 3.2V and is achieved by the low program voltage. The retention characteristics at 25℃ and 85℃ are shown in the figure. After 105 seconds, the small memory window narrowed 31% at 25℃. Extrapolating to 10 years, the small memory window vanishes at 25℃. The retention characteristics of the small memory window at 85℃ showed much poorer performance than at 25℃. The large memory window was about 4.6V and achieved by the high program voltage.
After about 105 seconds, the memory window narrowed 40% at 25℃. The large memory window also vanishes after 10 years retention time at 85℃.
The retention characteristics of the GIDL current on sample A at 25℃ is shown in Fig.4-21. The GIDL current is measured at constant gate voltage of -5V as the drain voltage is fixed at +1V. Then, we can have the initial memory window of about two orders of magnitude which is as same as sample B. At the beginning, the current ratio between the program state and the erase state is 150. After 105 seconds, the current ratio reduces to 40. Extrapolating to 10 years, the memory window vanishes.
Both the Vt and the GIDL current showed poor retention characteristics. There
are two possible reasons. The one is the escape of the charges which are stored in the trapping layer. As we have mentioned, the S/D junctions do not overlap with the gate on sample A. On sample A, the positions of the stored charges are near S/D junctions or above S/D junctions so they must be under the spacer or near the corner of the spacer. There is no Al2O3 blocking oxide under the spacer or near the corner of the spacer so the charges can easily escape from the trapping layer. Moreover, above the charge trapping positions on sample A, there are a lot of defects generated from the device fabrication process. These defects will enhance the charge loss rate. The other reason is due to “lateral charge migration” [24]. When the charges are stored in the HfO2 trapping layer at the source side or the drain side, the charges will move toward the trapping site above the channel center, and then the retention performance will degrade [24].