4-4-1 Sample B: Sufficient gate to source/drain overlap
The Id-Vg characteristics after applying different gate voltages with pulse width 1ms are shown in Fig. 4-9. The Vt shifts after program and erase operations at different gate voltages with different pulse widths are shown in Fig. 4-10 and Fig.
4-11, respectively. It can be found that the program and erase speed increase apparently when the gate voltage increases. The maximum memory window is about 7V. The programming time could be as short as 1μs at Vg = +18V, and the memory window is about 1.7V. However, the erase speed is slower than the program speed, so the memory device requires pulse width 100μs at Vg = -18V to erase the 1.7V memory window. The electrons are injected into the trapping layer from the channel under the
program operation. The holes are injected into the trapping layer from the channel under the erase operation. Because the hole barrier between the channel and tunneling oxide is larger than the electron barrier, the erase speed is slower than program speed.
When the pulse width increases, the saturation phenomenon of erase threshold voltage occurs due to some electrons injected from the gate into the trapping layer. On the other hand, the saturation phenomenon of program threshold voltage occurs due to some holes injected from the gate into the trapping layer when the pulse width increases.
The GIDL current is measured at constant gate voltages of -7V as the drain voltage is fixed at +1V. The increase of the GIDL current after programming at different gate voltages with different pulse widths is shown in Fig. 4-12. Then, as shown in Fig. 4-13, the erase speed diagram is evaluated by applying different drain voltages with different pulse widths to reduce the GIDL current on the forward read. It is observed that the program and erase speed increase apparently when the operation voltage increases. The maximum memory window is about two orders of magnitude and can be obtained by applying -18V to gate for 10ms. However, at gate voltage -14V, -16V and -18V, the memory window after programming with pulse width 1s is narrower than those with pulse width 0.1s. The possible reason of this phenomenon is that the holes generated from the substrate are injected into the trapping layer to eliminate some electrons stored in the trapping layer. This memory device can be programmed with pulse width 1μs at Vg = -18V, and the increase of the GIDL current is about one order. However, this memory device requires pulse width 100μs to erase one order memory window at Vd = +11V. Generally, in order to erase the maximum memory window of the GIDL current, Vd requires +11V, and pulse width requires 10ms. When the pulse width is longer than 10ms at Vd = +11V, the level of the GIDL current would not change anymore because all stored charges are already detraped. It
should be noted that the maximum Vd is limited by the drain junction breakdown voltage. Therefore, the allowable erase voltage would be lower than the program voltage typically. The erase speed at Vd = +10V is much faster than Vd = +9V. The possible reason is that stored electrons are detraped from the trapping layer into the drain by direct tunneling when drain voltage is lower than +9V. On the contrary, some stored electrons can be detraped by FN tunneling while drain voltage is higher than +10V.
4-4-2 Sample A: Insufficient gate to source/drain overlap
The Vt shift after the program and erase operation at different gate voltages with different pulse widths is shown in Fig. 4-14 and Fig. 4-15, respectively. It is observed that the program and erase speed increase dramatically when the gate voltage increases. The maximum memory window is about 5.5V. The programming time could be as short as 1μs at Vg = +18V, and the memory window is about 1.4V.
However, the erase speed is slower than program speed so the memory device requires a pulse width of 100μs at Vg = -18V to erase the 1.7V memory window. The saturation phenomenon of program and erase threshold voltage occurs when the pulse width increases, and it is due to same reason explained on sample B.
The GIDL current is measured at constant gate voltages of -5V as the drain voltage is fixed at +1V. The increase of the GIDL current after programming at different gate voltages with different pulse widths is shown in Fig. 4-16. Then, as shown in Fig. 4-17, the erase speed is evaluated by applying different drain voltage with different pulse widths to reduce the GIDL current on forward read. It is observed that the program and erase speed increase dramatically when the operation voltage increases. The maximum memory window is about two orders of magnitude and can be obtained by applying -18V to V for 10ms. However, at gate voltage -14V, -16V
and -18V, the memory window after programming with pulse width 1s is always narrower than those with pulse width 0.1s. It is similar to sample B. This memory device can be programmed with pulse width of 1μs at Vg = -18V, and the increase of the GIDL current is about 6 times. However, this memory device requires a pulse width of 100μs at Vd = +10V to erase the program state. Generally, in order to erase the maximum memory window of the GIDL current, Vd requires +10V, and the pulse width requires 10ms. When the pulse width is longer than 10ms at Vd = +10V, the level of the GIDL current would not change anymore because all stored charges are already detraped. As on sample B, the maximum Vd on sample A is also limited by the drain junction breakdown voltage. When Vd is +10V, the erase speed increases largely.
It confirms our inference discussed on sample B.