For state-of-the-art Si/SiO2, Si/SiON and even Si/SiO2/high-k MOS capacitors, interface traps have a negligible contribution to the C-V characteristic and do not interfere with the common parameters extraction. However, this is no longer the case when Si/SiO2 interface has been replaced by high-k/Ge or III-V structure.
Interface traps alter the admittance characteristic in two ways. Firstly, the interface traps modify the relationship between the gate voltages and interface Fermi level positions, causing so-called stretch-out of the C-V characteristic. Since capacitance is directly determined by band bending (band bending determines Cs), a stretch-out of the C-V results. Secondly, the interface traps contribute admittance to the MOS admittance. Based on the equivalent circuit, the relation between Dit and parallel conductance divided by frequency (Gp/ ) is derived.
2.3.1 CV Characteristics of Ge MOSCAP
Relative to the Si MOS capacitor, high frequency measurement of low band gap Ge MOSCAPs shows low frequency CV characteristics, as predicted by Nicollian and Brews several decades ago. Fig 2.2 depicts the multi frequency and quasi-static CV for different passivation Ge MOSCAPs, with EOT and Vfb calculated. Also, minority carrier response times [10] are calculated to be 0.07μs and 0.16μs, and the transition frequency
, at which the capacitance in inversion is midway between Cox and HF capacitance CHF, are 167KHz and 79KHz for P-Ge and N-Ge respectively.
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2.3.2 Conductance Method to Extract D
itThe common approaches toward extracting the value of Dit for Si MOS capacitors, namely the Terman and high–low frequency capacitance methods cannot be applied to Ge devices adequately because the frequently observed ―minority carrier response‖ causes humps in the CV curve, which largely overestimates the Dit value. On the other hand, conductance method is more accurate to extract since the substrate conductance is only contributed from interface density, as seen in equivalent circuit model of Fig 2.3 [11].
The band diagram of a typical MOS structure is shown in Fig 2.3(e), where a gate voltage VG is applied between the metal and the semiconductor, which fixes the value of the surface Fermi level. The C-V measurements consist in applying on top of the static gate bias voltage a small sinusoidal voltage with frequency f and amplitude of 25 mV. This small periodic gate voltage causes the bands and the surface potential in the semiconductor to periodically move up and down, causing the interface traps lying around the value of the surface potential to fill and empty. Only if the traps around the surface potential have a characteristic response time that is of the order of the measurement frequency f can they interact with the measurement ac signal and affect the total impedance of the MOS capacitor.
The capture and emission of carriers by interface traps is an energy dissipating process due to the time lag of the interface trap occupation compared to the required equilibrium trap occupation, and the lossy capture-emission process of carriers is modeled as a resistor (Rit) in series with Cit. The circuit can be simplified as in Fig. 2.2 (b),
way to extract Dit than capacitance based methods, since it is not necessary to know the exact value of semiconductor capacitance CS. From the circuit model, an important prerequisite is
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that capture and emission behavior only occur between the trap and majority carrier band edge; in other words, it is invalid to extract Dit when VG is biases at weak inversion region and will be discuss later in details. Therefore, p-Ge and n-Ge are required to extract the lower half and upper half bandgap, respectively, of the Dit profile.
By utilizing (2.2), can be determined from the measurement ( ) by eliminating the oxide capacitance.
(2.2) Equation (2.1) is valid for an interface trap with single energy level in the bandgap; in reality, interface traps are continuously distributed across the bandgap. If the time constant dispersion and trap energy level distribution across bandgap are taken into account, eq. (2.1) is modified:
Gp/ plots are repeated at different gate voltages to scan trap energies to obtain an interface state density distribution across the bandgap.
It is worthy to note that according to the emission time constant (
), the behavior of interface trap time constant as a function of temperature determines the part of interface traps in the bandgap observable in the MOS admittance characteristic. That is, traps located nearer to midgap become observable for higher temperatures while traps more located toward the band edges become observable for lower temperature. For small band gap Ge, midgap traps are able to be observed at room temperature; if decreasing the temperature, the observable energy windows shift toward the band edges as shown in Fig 2.4, where the effective density of states of the conduction (Nc) and the valence (Nv) bands, electron and hole
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thermal velocity, change in Ge bandgap with temperature are all taken into account.
Fig 2.5 illustrates the G
p/ versus f plots of our GeO2 passivation Ge MOSCAPs, and measurement is performed at room temperature. Gp/ curves are shown at the gate voltages Fermi level is near the midgap where interface states are able to capture and emission with the small signal AC bias. The peak value of each Gp/ curve corresponds to the interface state density and thus Dit as a function of gate voltage can be plotted. A tricky issue then arises, how to transform the Dit (VG) into Dit (E) plot? We are able to do so by two different approaches. A first way is to utilize frequency corresponding to the maximum Gp/ ; by the equation π combined with the value of maximum value of Gp/ , Dit across the bandgap can be obtained by repeated at different gate voltages to scan trap energies. The second way is to directly find the relation between gate voltage and surface potential by quasi-static CV measurement and Berglund integral, and the surface potential can be converted to energy in the bandgap by eq. (2.5) and (2.6)
(2.5)
(2.6) We chose the latter one eventually because in the first approach neither the value of
capture cross section nor its dependence on energy were known, in spite of the value of is assumed to be a constant of 10-15cm2 in some papers. The results for integration of the QSCV are shown in Fig 2.6. Then, the Dit profile of each sample near midgap before FGA is demonstrated in Fig 2.7. We get the following conclusions: 1. 550°C GeO2 passivation is obviously better than 500°C GeO2 passivation before FGA. 2. It exhibits symmetric Dit distribution for GeO2 passivation, which is different from the asymmetric profile of Si passivation (larger Dit in upper half bandgap) [13]. 3. The result shows more interface states in the midgap due to larger Gp/ peak value as more band bending in the depletion region.
This phenomenon is indeed so-called ―weak inversion response‖, for which the equivalent
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circuit in Fig 2.2(a) is not valid anymore; instead, the circuit should be modified as shown in
Fig 2.8[14]. In the weak inversion regime, interface traps can communicate with both the
majority and minority carrier bands because of the much smaller minority carrier time constant as Fermi level located near the midgap, and the ―dual communication‖ leads to a larger conductance response than the typical depletion response. For the Si/SiO2 interface, this effect does not occur at room temperature in the 1 kHz to 1 MHz frequency window because the time constants of that interaction are too large to happen. By contrast, small bandgap materials like germanium, the weak inversion response is shown to be present in the 1 kHz to 1 MHz measurement range. Therefore, directly applying conductance technique to Ge MOSCAPs will lead to overestimation of interface trap density.Whether or not weak inversion response is observed within the typical measurement window depends on the bandgap of the semiconductor, capture cross section of the trap, and the temperature. From the emission time constant (
), it is concluded that smaller bandgap material, larger capture cross section, and higher temperature make the weak inversion response more significant. In our case of Ge MOSCAPs, low temperature measurement is needed to alleviate the dual communication.
Although frequency corresponding to the maximum is not employed in determining the position in the bandgap, it can be used to estimate the capture cross section [15] by eq. (3.7), as shown in Fig 2.9.
(2.7) From our results, are extracted from n-Ge and p-Ge respectively with the extrapolation of plot, and larger (2.7-4.2 10-16 cm2) is obtained compared with (7.8-9.6 10-16 cm2). The derived capture cross section is substituted into the emission time constant so that Fig 2.4 can be illustrated. This value is extremely important since it offers us the information about the part of interface states observable in the 1 kHz to 1
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MHz frequency window. However, the value of will be double checked by charge pumping measurement of Ge MOSFET to see if it is reasonable.
Parasitic series resistance arising from low substrate doping and contact resistances or leakage through gate dielectric, can contribute measured admittance. They need to be included in the equivalent circuit model as Rs and Gt (Fig. 2.2 (d)) to extract the accurate value of interface trap conductance and capacitance. In this thesis, however, we assumed the two effects to be negligible because gate dielectric is quite thick (80 cycles ALD-Al2O3), and no significant frequency dispersion is observed in the accumulation region of CV curve.