Charge Trapping Behavior of Ge n-MOSFETs

The slow trapping can occur via bulk traps of high-k dielectric or border traps between interfacial transition oxide and high-k dielectric, where the traps are so slow that they can respond only to DC sweep but not AC frequency. GeO₂ has its a potential problem due to low conduction band offset (0.6eV for CB offset and 3.8eV for VB offset) with Ge[2], which can cause severe charge trapping in bulk traps of Al₂O₃ and the slow traps at GeO₂/Al₂O₃ interface.

For our Ge n-MOSFETs, either thicker GeO₂ passivation or thinner GeO₂ passivation show more severe charge trapping under static stress compared with Ge p-MOSFETs as expected because of much lower conduction band offset and the preference of electron trapping (Fig. 4.9a). Besides, the γ value of zafar model is extracted to be 0.15 and 0.17 for 550°C 10s and 550°C 60s GeO₂ passivation sample respectively. Smaller γ represents wider distribution of the capture time and more short time constant slow traps existed, indicating ratio of early traps is larger for 550°C 10s GeO₂ passivation sample, as depicted in Fig. 4.9b.

Thinner GeO2 sample exhibits more Vth shift in the beginning, because tunneling into GeO₂/Al₂O₃ interface is faster. However, thicker GeO₂ sample eventually shows more V_th shift than the thinner one as stress time becomes longer which is attributed to more total amount of slow traps (traps in GeO₂ layer). Therefore, a crossover point is observed. From

Figs. 4.9(a) and (c), it is observed that the crossover point shifts to lower stress time

(18.5s1.5s) as static stress voltage increases. We believe the effect of different capture rate at GeO2/Al2O3 interface in the beginning diminishes for larger stress voltage.

Besides, thicker GeO₂ passivation sample shows better subthreshold swing due to better interface quality, while not much difference in swing degradation is observed. Also, it’s intuitive to expect that more severe swing degradation occurs for larger stress voltage for each sample (Fig. 4.10).

73

4.4 Conclusions

In Chapter 4, we investigated the characteristics of Ge n⁺p junction with different isolation and thermal budget. It was concluded that SiO₂/GeO₂ isolation as well as 700°C 30s annealing enable us to obtain the lowest reverse bias junction leakage of 1.9×10^-2 A/cm² at 2V and magnitudes of the rectifying ratios reaching 4.2 orders. On/off ratio of our n-FETs (W/L

=100μm/10μm) reached 3 orders but series resistance larger than 1.7kΩ was attained which strongly affected the subthreshold swing and mobility extraction. The slightly higher effective mobility for thicker GeO2 passivation sample was due to better interface quality, which was reconfirmed by lower I_gen,s from gated-diode measurement and better subthreshold swing.

However, both of our samples had their mobility much lower than the electron universal curve, which could be explained by fast trapping at Ge/GeO₂ interface, slow trapping by GeO₂/Al₂O₃ border traps and parasitic S/D series resistance.

74

References (Chapter 4)

[1] R. Xie, T. H. Phung, W. He, Z. Sun, M. Yu, Z. Cheng and C. Zhu, ―High Mobility High-k/Ge pMOSFETs with 1 nm EOT -New Concept on Interface Engineering and Interface Characterization‖, IEDM Tech. Dig, pp. 393-396, 2008.

[2] Duygu Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H. S-. P. Wong and K. Saraswat, ―Experimental Demonstration of High Mobility Ge NMOS‖, IEDM

Tech. Dig, pp.453-456, 2009.

[3] M. Posselt, B. Schmidt, W. Anwand, R. Grotzschel, V. Heera, A. Mucklich, C.

Wundisch, W. Skorupa, H. Hortenbach, S. Gennaro et al., ―P implantation into preamorphized germanium and subsequent annealing: solid phase epitaxial regrowth, P diffusion, and activation,‖ J. Vac. Sci. Technol. B, vol. 26, p. 430, 2008.

[4] A. Satta, E. Simoen, R. Duffy, T. Janssens, T. Clarysse, A. Benedetti, M. Meuris, and W.

Vandervorst, ―Diffusion, activation, and recrystallization of high dose P implants in Ge,‖

Appl. Phys. Lett., vol. 88, p. 162118, 2006.

[5] C. H. Lee, T. Nishimura, N. Saido1, K. Nagashio, K. Kita and A. Toriumi, ―Record-high Electron Mobility in Ge n-MOSFETs exceeding Si Universality‖, IEDM Tech. Dig, pp.457-460, 2009.

[6] W. Zhu, J. P. Han, and T.P. Ma, ―Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-K dielectrics,‖ IEEE Transactions on Electron

Devices, 51:98-105, 2004.

75

Fig. 4.1 Process flow of Ge n-MOSFETs and their device structure.

76

-2 -1 0 1 2

10

^-6

10

^-4

10

^-2

10

⁰

10

²

10

⁴

SiO² isolation SiO²/GeO² isolation

no FGA, 700

^o

C 30s activation

Current Density, J(A/cm2 )

Voltage (volt)

2 orders

(a)

(b)

Fig. 4.2 (a) Junction IV is compared for different isolation. (b) Illustrations to explain the junction characteristic in (a).

77

-2 -1 0 1 2

10

^-5

10

^-3

10

^-1

10

¹

10

³

SiO

2/GeO2

isolation, no FGA

Current Density, J(A/cm2 )

Voltage (volt)

500

^o

C 60s activation 700

^o

C 30s activation

(a)

-2 -1 0 1 2

10

^-5

10

^-3

10

^-1

10

¹

10

³

⁷⁰⁰

^o

C 30s activation RTO 550

^o

C 60s RTO 550

^o

C 10s SiO

2/GeO2

isolation, no FGA

Current Density, J(A/cm2 )

Voltage (volt) 4.2 orders

(b)

Fig. 4.3 (a) Junction IV is compared for different activation temperature. (b) Junction characteristic of n-MOSFETs with different GeO2 thickness (different thermal budget) is compared.

78

0 1 2 3 4

0 10 20 30

700^oC 30s activation 550^oC 10s GeO2

L=10m VG-V^th=0~4V

Drain Current, I D (A/m)

Drain Voltage, V

_D

(V) Ge NMOSFET, w/o FGA

(a)

0 1 2 3 4

0 10 20 30

Ge NMOSFET, w/o FGA

700^oC 30s activation

550^oC 60s GeO2

L=10m V^G-Vth=0~4V

Drain Current, I D (A/m)

Drain Voltage, V

_D

(V)

(b)

Fig. 4.4 ID-VD characteristics of Ge n-MOSFETs are plotted. (a) 550°C 10s GeO2

passivation (b) 550°C 60s GeO2 passivation (W/L=100μm/10μm)

79

-2 -1 0 1 2 3

0.01 0.1 1 10

550

^o

C 10s GeO

2

passivation

700^oC 30s activation L=10m, before FGA V_D=0.1~1.6V, Vstep=0.5V Drain Current, I D (A/m)

Gate Voltage, V

_G

(V)

(a)

-2 -1 0 1 2 3

0.01 0.1 1 10

550

^o

C 60s GeO

2

passivation

700^oC 30s activation L=10m, before FGA V_D=0.1~1.6V, Vstep=0.5V Drain Current, I D (A/m)

Gate Voltage, V

_G

(V)

(b)

Fig. 4.5 ID-VG characteristics of Ge n-MOSFETs are plotted. (a) 550°C 10s GeO2

passivation (b) 550°C 60s GeO2 passivation (W/L=100μm/10μm)

80

Fig. 4.6 Series resistances of Ge n-MOSFETs are extracted by Terada and Muta method. (a) 550°C 10s GeO2 passivation (b) 550°C 60s GeO2 passivation

81

-1.5 -1.0 -0.5 0.0

2.07 2.10 2.13

Ge NMOSFET, no FGA

RTO 550^oC 10s no FGA

VD=VS=0.2V I_gen,S=4.32E-8A

Drain/Source Current (A)

Gate Voltage, V

_G

(V)

(a)

-1.5 -1.0 -0.5 0.0

2.07 2.10 2.13 2.16 2.19 2.22

RTO 550

^o

C 60s no FGA

V

^D

=V

^S

=0.2V I

_gen,S

=3.97E-8A Ge NMOSFET, no FGA

Drain/Source Current (A)

Gate Voltage, V

_G

(V)

(b)

Fig. 4.7 Gated-diode measurement detects the interface state density of Ge n-MOSFETs roughly. (a) 550°C 10s GeO2 passivation (b) 550°C 60s GeO2 passivation

82

0 3x10

¹²

6x10

¹²

9x10

¹²

0

200 400 600 800

550^oC 60s GeO2

550^oC 10s GeO2

universal curve Toriumi,IEDM 2009 Standford,IEDM 2009

Mobility(cm2 /Vs)

Inversion Charge, Q

_inv

(cm

^-2

)

(a)

0 2x10

¹²

4x10

¹²

6x10

¹²

200 400 600

550

^o

C 60s GeO

2

passivation

mobility with Rs eliminated mobility from Split CV

universal curve

Mobility(cm2 /Vs)

Inversion Charge, Q

_inv

(cm

^-2

)

(b)

Fig. 4.8 (a) Effective mobility of our samples as a function of Qinv and other published data are shown. (b) Effective inversion mobility with RSD eliminated is demonstrated.

83

700^oC 30s dopant activation

V^T=VMAX[1-exp(-(t/o)

700^oC 30s dopant activation

V^T=VMAX[1-exp(-(t/o)

passivation sample under static stress. (a) VG-Vth =3.5V. (b) Ratio of early traps. (c) VG-Vth =3.9V.

84

10

⁰

10

¹

10

²

10

³

400 600 800

550^oC 10s GeO2

Vstr.=V^G-V^th=3.9V Vstr.=V^G-V^th=3.5V

700^oC 30s dopant activation

, no FGA

Swing (mV/dec)

Stress Time (s)

550^oC 60s GeO2

Vstr.=V^G-V^th=3.9V Vstr.=V^G-V^th=3.5V

Fig. 4.10 Characteristic of subthreshold swing degradation of two stress voltages for each sample is illustrated.

85

Chapter 5

Conclusions and Suggestions for Future Work

5.1 Conclusions of this study

In this thesis, firstly, we had shown that Dit can be reduced effectively through 300°C 30 minutes FGA from MOSCAP analysis, with value about 5×10¹¹ cm^-2eV^-1 near the midgap from either conductance or Fermi-level efficiency method. By extrapolation of

plot, and were 2.7-4.2 10^-16cm² and 7.8-9.6 10^-16 cm² respectively.

Secondly, from the experiences in high-k/GeO2/Ge capacitors, we successively demonstrated the device characteristics of the inversion-mode Ge p-FETs with ALD-Al₂O₃ gate dielectrics. GeO2 passivation as well as no passivation sample had their high field mobility 1.7X and 1.3X higher than the Si universal curve respectively. Also, better on/off ratio (3.8 orders) and subthreshold swing (170mv/dec) were attained for Ge p-FET after 300°C 30 minutes FGA, resulted from lower reverse bias junction leakage and better interface quality. Then, charge pumping was applied to reconfirm the results obtained from Chapter two. after FGA between and is 4.2×10¹¹cm^-2eV^-1 and was 5.4×10^-16 cm² for 500°C GeO2 passivation sample. Furthermore, pros and cons of adding the GeO₂ layer were summarized: lower D_it value verified from either charge pumping or gated diode measurement made the mobility higher for GeO2 passivation sample, while it suffered from more carrier-trapping due to border traps at the GeO₂/Al₂O₃ interface and more severe subthreshold swing degradation.

Finally, device characteristics of inversion-mode Ge n-FETs with ALD-Al₂O₃ gate dielectrics were also demonstrated. SiO2/GeO2 isolation as well as 700°C 30s dopant activation did we obtain the lowest reverse bias junction leakage of 1.9×10^-2 A/cm² at 2V and magnitudes of the rectifying ratios reached 4.2 orders. On/off ratio of our n-FETs (W/L =

86

100μm/10μm) reached 3 orders but series resistance larger than 1.7kΩ was extracted. The slightly higher effective mobility for thicker GeO₂ passivation sample was due to better interface quality, which was reconfirmed by lower Igen,s from gated-diode measurement and better subthreshold swing. However, both of them were still much lower than the Si universal mobility for electrons. It was concluded that much severe n-FET performance degradation compared with p-FET could be explained in terms of fast trapping at Ge/GeO₂ interface, slow trapping by GeO2/Al2O3 border traps and parasitic S/D series resistance.

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