Conclusions

GeO2 passivation Ge PMOS and NMOS capacitors with different GeO2 growing temperature were fabricated. Theory of the conductance method was discussed in detail, and utilizing it to extract the interface state density for different passivation samples. Dit of each sample was effectively reduced through FGA. Not only from G_p/ value but from Fermi level efficiency did we attain similar result, Dit near midgap was about 5×10¹¹ and 1×10¹² cm^-2eV^-1 with and without FGA respectively. Also, (2.7-4.2 10^-16cm²) and

(7.8-9.6 10^-16 cm²) could be extracted by extrapolation of plot.

Low temperature measurement was performed to extract D_it near band edges, with the normally observed U-shaped distribution derived. However, the reason for unobservable peaks was still unclear and further investigation was needed. We also utilized the G_sub biasing in strong inversion to make the Arrhenius plot, proving that activation energy equal to Eg/2 at lower temperature (<45°C). Generation-recombination induced inversion response is the dominating mechanism that causes low frequency CV characteristics for high frequency measurement at room temperature.

22

References (Chapter 2)

[1] S. K. Kim, S. W. Lee, C. S. Hwang, Y.-S. Min, J. Y. Won, and J. Jeong, ―Low temperature (<100°C) deposition of aluminum oxide thin films by ALD with O3 as oxidant,‖ J. Electrochem. Soc. vol. 153, p. F69, 2006.

[2] M. D. Groner, F. H. Fabreguette, J. W. Elam, and S. M. George, ―Low-temperature Al2O3 atomic layer deposition,‖ Chem. Mater. vol. 16, p. 639, 2004.

[3] C. O. Chui, H. Kim, D. Chi, P. C. McIntyre, and K. C. Saraswat, ―Nanoscale germanium MOS dielectrics—Part II: high-k gate dielectrics,‖ IEEE Trans. Electron Devices, vol. 53, p. 1509, 2006.

[4] W. P. Bai, N. Lu, and D.-L. Kwong, ―Si interlayer passivation on germanium MOS capacitors with high-k dielectric and metal gate,‖ IEEE Electron Device Lett. vol. 26, p.378, 2005.

[5] F. Gao, S. J. Lee, J. S. Pan, L. J. Tang, and D.-L. Kwong, ―Surface passivation using ultrathin AlNx film for Ge–metal–oxide–semiconductor devices with hafnium oxide gate dielectric,‖ Appl. Phys. Lett. vol. 86, p. 113501, 2005.

[6] W. Bai, N. Lu, P. Ritenour, M. L. Lee, D. A. Antoniadis, and D.-L. Kwong, ―The electrical properties of HfO2 dielectric on germanium and the substrate doping effect,‖

IEEE Trans. Electron Devices, vol. 53, p. 2551, 2006.

[7] C.-C. Cheng, C. H. Chien, G.-L. Luo, C.-H. Yang, M.-L. Kuo, J.-H. Lin, C.-K. Tseng, and C.-Y. Chang, ―Study of thermal stability of HfOxNy/Ge capacitors using postdeposition annealing and NH3 plasma pretreatment,‖ J. Electrochem. Soc. vol. 154, p.

G155, 2007.

[8] S. J. Whang, S. J. Lee, F. Gao, N. Wu, C. X. Zhu, J. S. Pan, L. J. Tang, and D. L. Kwong,

―Germanium p- and n-MOSFETs fabricated with novel surface passivation (plasma PH3

and thin AlN) and TaN/HfO2 gate stack,‖ Tech. Dig. Int. Electron Devices Meet. p. 307, 2004.

[9] H.Matsubara, T. Sasada, M. Takenaka, and S. Takagi, "Evidence of low interface trap density in GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation", Appl. Phys. Lett., vol. 93, p. 032104, 2008.

[10] A. Dimoulas, G. Vellianitis, G. Mavrou, E. K. Evangelou, and A. Sotiropoulos, ―Intrinsic carrier effects in HfO2-Ge metal–insulator–semiconductor capacitors,‖ Appl. Phys. Lett., vol. 86, p. 223507, 2005.

[11] D. K. Schroder, Semiconductor Material and Device Characterization, Wiley, New York, 2006.

[13] R. Xie, N. Wu, C. Shen, and C. Zhu, "Energy distribution of interface traps in germanium metal-oxide semiconductor field effect transistors with HfO2 gate dielectric and its impact on mobility", Appl. Phys. Lett., vol. 93, p. 083510, 2008.

[14] K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. Heyns,

23

T. Krishnamohan, K. Saraswat, H. E. Maes, G. Groeseneken, ―On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates‖,

IEEE Trans. Elec. Dev.,55, pp. 547-555, Feb. 2008.

[15] A. J. Hong, M. Ogawa, K. L. Wang, Y. Wang, J. Zou, Z. Xu, and Y. Yang, "Room temperature Si δ-growth on Ge incorporating high-K dielectric for metal oxide semiconductor applications", Appl. Phys. Lett., vol. 93, p. 023501, 2008.

[16] H. C. Lin, G. Brammertz, K. Martens, G. d. Valicourt, L. Negre,W.E. Wang, W. Tsai, M.

Meuris, and M. Heyns, "The Fermi-level efficiency method and its applications on high interface trap density oxide-semiconductor interfaces", Appl. Phys. Lett., vol. 94, p.

153508, 2009.

[17] Nicollian and Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley

& Sons, New York, 1982.

24

Fig. 2.1 Process flow of Ge MOSCAPs and their device structure.

25

(a) (b)

(c) (d)

Fig. 2.2 Multi frequency and quasi-static CV of Ge MOSCAPs before FGA are depicted. (a) p-Ge, RTO 500°C 10s. (b) p-Ge, RTO 550°C 10s. (c) n-Ge, RTO 500°C 10s. (d)

26

(e)

Fig 2.3 Equivalent circuit models for conductance measurements; (a) MOS capacitor with single level interface traps, (b) simplified circuit of (a), (c) measured circuit, (d) including series resistance and tunnel conductance due to gate leakage. (e) The band diagram of a typical MOS structure is illustrated, with surface potential in the semiconductor to periodically move up and down because of a small sinusoidal voltage on top of the static gate bias.

27

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 10

^-1

10

¹

10

³

10

⁵

10

⁷

10

⁹

p-Ge n-Ge

Ec Ev

Assuming



=4.2E-16cm

²

77k 180k 120k

298k

250k

Responsefrequency fit (Hz)

Et-Ei (eV)

Fig 2.4 The behavior of the interface trap time constant as a function of temperature determines the part of interface traps in the bandgap observable in the MOS admittance characteristic.

28

29

(a)

(b)

Fig. 2.6 Relation between gate voltage and surface potential by integration of quasi-static CV before FGA are calculated. (a) p-Ge. (b) n-Ge.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

30

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 10

¹⁰

10

¹¹

10

¹²

10

¹³

10

¹⁴

P-Ge N-Ge

Dit(cm-2 eV -1 )

Et-Ei (eV)

w/o FGA

RTO 500^oC RTO 550^oC

D

it

distribution in Ge Band Gap

Fig. 2.7 Dit profile of each sample near midgap before FGA is demonstrated.

Fig. 2.8 A band diagram showing the weak inversion response (left) and the general equivalent circuits used to model the MOS capacitor C-V and G-V characteristics across the bandgap for an n-type capacitor. The first circuit (middle) models one trap only: Cox is the oxide capacitance, Cinv the inversion capacitance, Cs

the

depletion (and accumulation) capacitance, CT the trap capacitance, and Gn, Gp

electron and hole trap conductance, respectively. For distribution of interface states a series of Y-circuits is used (right).

31

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.83

2.26 6.14

500

^o

C GeO

₂

, w/o FGA

P-Ge,

_p

=7.8E-16cm

²

N-Ge,

_n

=2.7E-16cm

²

Time Constant e (

s

)

Et-Ei (eV)

(a)

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.83

2.26 6.14

550

^o

C GeO

₂

, w/o FGA

N-Ge,

_n

=4.2E-16cm

²

P-Ge,

_p

=9.6E-16cm

²

Time Constant e (

s

)

Et-Ei (eV)

(b)

Fig. 2.9 and are extracted from n-Ge and p-Ge respectively with the extrapolation of plot. (a) RTO 500°C 10s. (b) RTO 550°C 10s.

32

(a) (b)

(c) (d)

Fig. 2.10 Multi frequency and quasi-static CV of Ge MOSCAPs after FGA are depicted. (a) p-Ge, RTO 500°C 10s. (b) p-Ge, RTO 550°C 10s. (c) n-Ge, RTO 500°C 10s. (d)

33

34

(a)

(b)

Fig. 2.12 Relation between gate voltage and surface potential by integration of quasi-static CV after FGA are calculated. (a) p-Ge. (b) n-Ge.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

35

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 10

¹⁰

10

¹¹

10

¹²

10

¹³

10

¹⁴

with FGA w/o FGA

P-Ge N-Ge

RTO 500^oC ( ) RTO 550^oC ( ) Dit(cm-2 eV-1 )

Et-Ei (eV)

D

it

distribution in Ge Band Gap

Fig. 2.13 Comparison of Dit profile of each sample near midgap with and w/o FGA is demonstrated.

36

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 20

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 30

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 30 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15

20

37

(a) (b)

(c) (d)

Fig. 2.15 Multi frequency CV characteristics of 550°C GeO2 passivation PMOSCAP after FGA are measured at low temperature. (a) 77K (b) 120K (c) 180K (d) 250K

-2 -1 0 1 2

38

Fig. 2.16 Gp/ data of 550°C GeO2 passivation PMOSCAP after FGA are illustrated. (a) 77K (b) 250K

39

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 1E10

1E11 1E12 1E13 1E14

100K

200K

RTO 550  C 10s after FGA

250K

180K 120K

77K

N-Ge

D it

(

cm

-2

e V

-1 )

Et-Ei (eV) Our work

Toriumi, IEDM 2009

Fig. 2.17 Dit profile in the upper half bandgap for 550°C 10s GeO2 passivation after FGA is demonstrated.

40 peak-observable gate voltage range. (a) 77K (b) 120K

41

(a)

30 35 40 45 50 55 60 65

0.0001 0.0025 0.0498 1.0000

E

act

~0.66eV~E

g

G I/A (S/cm2 )

1/kT ( eV

^-1

)

f=100kHz APL, 2005 Our work 550

^o

C GeO

₂

Eact~0.32eV~Eg/2

(b)

Fig. 2.19 (a) Diffusion-induced and generation-recombination induced inversion response are modeled by inserting corresponding conductance in parallel when bias in inversion regime. (b) Arrhenius plot of the substrate conductance at 100 kHz and -1.2 V (180K, 250K, and 297K) of our 550°C GeO2 passivation MOSCAP is shown.

42

Chapter 3

Inversion-Mode Ge p-MOSFET with Atomic-Layer-Deposited Al 2 O 3 Gate Dielectrics

3.1 Introduction

When Si complementary metal-oxide-semiconductor (CMOS) technologies gradually scale to 22 nm node, the high mobility semiconductor materials receive renewed interest in MOSFET applications to pursue much higher device performance. In particular, Ge and III-V-based channels with various prevailing gate dielectrics are promising structures to replace the conventional Si MOSFETs. Nevertheless, several formidable challenges remain if we are to realize state-of-the-art Ge devices. Adequate surface passivation with a low D_it value and larger junction leakage due to lower band gap are essential to be solved, which make the high performance Ge devices feasible. The junction leakage should be overcome by alternative device geometries, such as thin epi-Ge on Si, Ge-on-insulator, or FinFETs. Much effort have been spent on the high quality epitaxial Ge [1]; however, difficulties still exist and this is beyond the scope of the thesis. We adopt the GeO2 layer experience from Chapter 2 to passivate the Ge surface.

In this chapter, effects of inserting a GeO2 layer and performing FGA on junction or device electrical characteristics are discussed, including series resistance, subthreshold swing, and mobility. Also, interface qualities for different samples are characterized by charge pumping and gated-diode measurement; reliability issues for GeO₂ are investigated through applying stress. Finally, the pros and cons of a GeO2 passivation layer before high-k deposition are summarized according to our experimental results.

43

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