The promising high-mobility substrate material, Ge, is investigated in this thesis since great progress in the deposition of high-k materials renews interest in high mobility substrates as a transport channel combined with various high-k dielectrics. One of the largest obstacles of Ge MOSFETs is the high defect density at the Ge dielectric interface, which degrades drive current, alters the threshold voltage, and increases the leakage currents. Therefore, surface passivation of Ge is a key challenge to achieve high performance Ge MOSFETs. The thesis is divided into five chapters and arranged as follows:
Chapter 1, a brief overview of the background and motivation is described. The
MOSFET scaling roadmap and the probable ways to boost device performance for next generation are mentioned. Next, one of the most promising alternative channel materials, Ge, is investigated through the SWOT analysis.Chapter 2, GeO
2 passivation Ge PMOS and NMOS capacitors with different GeO2growing temperature were fabricated, and emphasis was put on obtaining a high quality interface for later application in the MOSFET gate dielectric. Theory of the conductance method was discussed in detail, and utilizing it to extract the interface state density for different passivation sample. Then, the effect of FGA on the admittance behavior of Ge MOS capacitors was investigated. With the help of low temperature measurement, Dit distribution in the upper half band gap was illustrated.
Chapters 3, Ge PMOSFETs with and without GeO
2 surface passivation were fabricated.Effect of FGA on the Ge p+/n junction and device electrical characteristic was studied. Also, Dit of the two samples was examined by gated-diode and charge pumping measurement, to reconfirm the value of Dit extracted by the conductance method reasonable. Then, mobility
6
extracted from split-CV of our samples was compared with other published data. Finally, CVS was done to test reliability of the two samples.
Chapter 4, Ge NMOSFETs with different thickness GeO
2 surface passivation were fabricated, and we showed that SiO2/GeO2 isolation layer was essential to reduce junction leakage current. Then, mobility extracted from split-CV of our samples was compared with other published data. Again, charge pumping and gated diode measurement were done to attain the interface information while CVS was done to observe different trapping behaviors of Ge NMOSFETs with different GeO2 thickness.Chapter 5, we summarized the experimental results in the thesis, gave the conclusions
and suggestions for future work.7
References (Chapter 1)
[1] M. Levinshtein, S. Rumyantsev, and M. Shur, Handbook Series on Semiconductor
Parameters Volume 1: Si, Ge, C (diamond), GaAs, GaP, GaSb, InAs, InP, InSb, World
Scientific, Singapore, 1996.[2] M. Lundstrom, ―Elementary scattering theory of the Si MOSFET.‖ IEEE Electron
Device Letters, 18:361-363, 1997.
[3] R. Xie, T. H. Phung, W. He, Z. Sun, M. Yu, Z. Cheng and C. Zhu, ―High Mobility High-k/Ge pMOSFETs with 1 nm EOT -New Concept on Interface Engineering and Interface Characterization‖, IEDM Tech. Dig, pp. 393-396, 2008.
[4] M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie, G. Wang, R. Loo, E.
Simoen, J. Mitard, B. De Jaeger, G.Hellings, K. De Meyer, M. Meuris, M. Heyns,
―Germanium for advanced CMOS anno 2009: a SWOT analysis‖, IEDM Tech. Dig, pp.
461-464, 2009.
[5] T. Krishnamohan, D. Kim, T. V. Dinh, A. t. Pham, B. Meinerzhagen, C. Jungemann, K.
Saraswat, ―Comparison of (001), (110) and (111) uniaxial- and biaxial- strained-Ge and strained-Si PMOS DGFETs for all channel orientations: mobility enhancement, drive current, delay and off-state leakage‖, IEDM Tech. Dig, 2008.
[6] G. Wang, R. Loo, E. Simoen, L. Souriau, M. Caymax, M. M. Heyns, and B. Blanpain,
"A model of threading dislocation density in strain-relaxed Ge and GaAs epitaxial films on Si(100)", Appl. Phys. Lett., vol. 94, p. 102115, 2009.
[7] J.H. Park, M. Tada, D. Kuzum, P. Kapur, H. Y. Yu, P. Wong, K. Saraswat, ―Low Temperature (≤ 380ºC) and High Performance Ge CMOS Technology with Novel Source/Drain by Metal-Induced Dopants Activation and High-K/Metal Gate Stack for Monolithic 3D Integration‖, IEDM Tech. Dig, pp.389-392, 2008.
8
Fig. 1.1 Transistor scaling and research roadmap is demonstrated by R. Chau, Intel Corp.
Fig. 1.2 Illustration of the performance gap between projected performance and actual performance for CMOS circuit downscaling.
9
Fig. 1.3 Carrier velocities as a function of electric field for Ge, Si and GaAs are shown. The mobility is the slope of drift velocity and the electric field.
Table 1.1 Material properties of bulk Ge, Si, GaAs, and InAs at 300 K are compared.
10
Chapter 2
Atomic-Layer-Deposited Al 2 O 3 Dielectric Films on the Bulk GeO 2 Passivation Germanium Substrates
2.1 Introduction
High-k Al2O3 is considered a potential alternative gate dielectric material on Si substrates for application to metal oxide semiconductor field effect transistors (MOSFETs) because of its wide band gap energy (ca. 8.8eV), large conduction/valance band offsets, and high thermodynamic stability. Several reports have described the characteristics of ALD-Al2O3
dielectric films grown on Si using trimethylaluminum [TMA, Al (CH3)3] as the precursor and H2O as the oxidant because of the excellent ALD mechanism and broad process window [1], [2].In recent years, many investigators have studied the deposition of ALD-HfO2 high-k layers on high-mobility Ge substrates [3] using a variety of oxidants in efforts aimed at enhancing the driving current in MOSFETs. However, the primary obstacle affecting the characteristics of high-k/Ge structures is the presence of GeOx native oxides which degrades the Ge device performance, leading to higher value of Dit and thus lower mobility. Therefore, many efforts have been devoted to surface passivation of the non Si/SiO2 interface, including incorporation of ultra-thin Si [4], AlNx [5] and GeON [6]dielectric interlayers, plasma treatment with NH3
or PH3 [7][8], and more recently, GeO2 passivation[9]. In this thesis, GeO2 passivation is adopted to passivate the Ge surface.
Interface passivation is a key challenge for realizing Ge/III-V CMOS, and how to evaluate the interface quality correctly is of great importance. The bandgap of Ge and III-V substrates also affects the admittance characteristics in many aspects which are obviously different from the Si-based devices. For that reason, correct interpretation of the routinely used admittance characteristics becomes of paramount importance in Ge/III-V technology.
11
The admittance of an MOS structure is measured as a function of DC gate voltage and frequency by applying a small AC signal and DC bias voltage on the MOS capacitor.
Admittance characteristics (C-V and conductance characteristics) are frequently used to characterize crucial parameters of Si MOS capacitors such as the flatband voltage, fixed charge, effective oxide thickness, doping level, and most importantly, the semiconductor dielectric interface quality.
In this chapter, low-frequency C-V curves for high frequency measurement of Ge MOSCAPs are first shown, followed by the conductance method to extract Dit and the estimation of capture cross section based on the Shockley-Reed-Hall theory. Next, the admittance behaviors affected by FGA are discussed through the slope of the C-V curve, Gp/ data, and more intuitionally, the Fermi level movement efficiency. Finally, Dit distribution across the bandgap is illustrated with the help of low temperature measurement.