Bandgap voltage reference (BGR) circuit have been widely used in analog mixed-mode circuits such as ADC，portable equipments and battery-powered devices. In order to increase battery efficiency and extend battery life time, low voltage BGR circuit is the trend in the near future.
Besides, PSRR is another important issue in BGR design , especially for power management system. Because the power supply noise have a serious impact on BGR circuits performance.
For low voltage requirement, many solutions have been proposed, for example, using Bi-CMOS process [1], biasing the MOSFET in the sub- threshold region [2], or forward biasing the source-bulk junctions of the MOSFET [3], etc.
Some of the solutions can be implemented by using the CMOS process, but some others cannot.
As for the high PSRR issue, some useful solutions have been proposed. For example, we can increase the impedance to power supply noise by using cascoded-MOS pair circuits [4]. However it is hard to satisfy the low voltage requirement by using the cascoded-MOS pair circuit topology.
In this thesis, we try to reach the high PSRR requirement based on the low voltage circuit topology implemented by standard CMOS process.
1.2 Review on CMOS Bandgap Reference Circuits (I)
1.2.1 What is The “Bandgap”
The bandgap circuits operates based on the principle of compensating the negative temperature coefficient of VBE (Base-to-Emitter junction voltage) with the positive temperature coefficient of ΦT (thermal voltage), where ΦT = kT/q is proportional to the absolute temperature and is often referred it by using the acronym PTAT.
We can create a full temperature compensation voltage at room temperature by combining the terms of positive temperature coefficient with another negative temperature coefficient by the formula given described below：
VBG = VBE + MΦT = VBE + M (kT / q)
Since the temperature coefficient of VBE, at room temperature, is around -2.2 mV/°C；while the positive coefficient of the thermal voltage, ΦT, is 0.086 mV/°C. The constant coefficient M must be around to 25.6 (=2.2/0.086) in order to make the temperature coefficient of VBG equal to zero at room temperature.
As we know that the value of VBE at low currents is close to 0.60V, and ΦT
at room temperature is 25.8 mV, the voltage of VBG achieved by a bandgap circuit is typically equal to 1.26 V.
VBG= VBE + MΦT = 0.60V +25.6 × 25.8 mV = 1.26 V
Such a value is just slightly more than the silicon energy gap (expressed in volts is 1.21 V). Therefore, we normally call this voltage as bandgap reference voltage.
1.2.2 Conceptual Implementation
1.2.2.1 Conventional Bandgap Circuit
Fig.1-1 shows a conventional bandgap circuit. Two components build up the bandgap reference voltage, VREF. One is the voltage across a directly BJT- connected diode (VBE), and the other is ΦT, a term proportional to the absolute temperature (PTAT).
`
VREF R2
R1
RX
IR1 IR2
Q1 Q2
Case 1
Fig. 1-1 Conventional bandgap circuit VREF = VR2 + VRX + VBE2
∵ VR2 / VRX = R2 / RX
VR2 = (R2 / RX ) × VRX
∴ VREF = VRX( RX
R2
+ 1) + VBE2 (1.1) Besides，VRX = VBE1 － VBE2 =ΦT ㏑
2 1 R R
I I
∴ VREF = MΦT + VBE2 (1.2) where, M＝㏑
1 2 R × (R
RX
R2
+ 1) is a temperature-independent constant NOTE_1
Secondly, Known : VREF ＝ MΦT + VBE2
We hope the temperature coefficient of VREF ＝ 0 ( i.e. VREF
∂T
∂ ＝ M
∂T
∂ ΦT T0 +
∂T
∂ VBE2 T0 ＝ 0 ) So, we should adjust M, such that
M ∂T B is a temperature-independent constant
AE is the base-emitter junction area Eg(Si) is the band gap energy of Silicon
Step 3 Substituting (1.4) and (1.8) into (1.3) gives VREF
∂T
∂ ＝ M
∂T
∂ ΦT T0 +
∂T
∂ VBE2 T0
＝ M
0
1
T ΦT0 +
0
1
T VBE2 － ΦT ×
0
3 T －
0 0
T VG
＝ 0 (1.9)
We derive MΦT0 ＝ 3ΦT0 + VG0 － VBE2 (1.10) So, M ＝ 3 + ( VG0 － VBE2 T0 ) ∕ΦT0 (1.11)
Step 4 Substituting M into (1.2) gives VREF ＝ MΦT0 + VBE2
＝ (3ΦT0 + VG0 － VBE2) + VBE2
＝ 3ΦT0 + VG0 (1.12)
Finally, The bandgap voltage of silicon VGO ＝ q Eg(Si)
＝ 1.205 V
So that, VREF ＝ 3 × (25.6 mV) + 1.205 V = 1.282V (1.13)
Note_1:
+ 1) which is temperature – independent.
In fact, the individual resistances (R1, R2, RX) will vary its value with temperature.
But the ratio can keep nearly constant, that is,
R independent of temperature R
Proof：
Note_2:
IS ＝
B
n i E
Q
D n A
q× × 2×
＝
B ' × n
i2× D
n (1.18)Where
n
i : intrinsic minority – carrier concentration QB : the total base doping density per unit area AE : emitter – base junction area
B '
: temperature – independent constantBy Einstein equation :
μ
n =KTq ×
D
n ,D
n ＝ ΦT ×μ
n (1.19)∴ IS ＝
B ' × n
i2× ( μ
nφ
T)
＝n
iT
nq
B ' × K ×
2× × μ
(1.20)Set IS ＝ B ''×ni2 ×T ×
μ
nKnown
μ
n ＝CT
−n , C is a temperature – independent constantn
i2 ＝ DT exp (3T
VG
φ 0
− ) , D is a temp. – independent constant
Finally, we assume n = 1 and get
IS ＝ B ''× DT exp (3
T
VG
φ 0
− ) × T ×
CT
−1＝ B× AE ×T3× exp (
T
VG
φ 0
− ) (1.21)
1.2.2.2 Recently Proposed Bandgap Circuit
According to the previous analysis, If the power supply voltage is lower than 1.28V, the conventional bandgap reference circuit cannot be used.
In order to meet the demand that power supply voltage is lower than 1.3V, one solution was proposed by using current-mode structures and low operating voltage of OP-Amplifiers to achieve the low voltage (VDD ≤ 1.0V) bandgap reference circuit as shown in Fig. 1-2 and described below [8].
VDD
Fig. 1-2 Typical current-mode bandgap circuit
EB
Fig. 1-2 shows a typical current-mode BGR circuit topology. First, we set Vd1=Vd2 by utilizing the OPA negative feedback characteristic. Second, according to the BJT device physics, the circuit will create two currents, which are IR1 and IR2A. The current IR1 will increase as the temperature increase, which is called the positive temperature coefficient. And the current IR2A will decrease as the temperature increase, which is called the negative temperature coefficient.
Theoretically, these two currents (IR1 and IR2A) will compensate to each other. So we can get a new stable current which is independent of temperature by adding these two currents (IR1 and IR2A). Finally, making the new stable current (I3) pass through a resistor can produce the so-called reference voltage.
According to the theory, it is possible to achieve 0.7V reference with 1.0V power supply voltage and a well-controlled temperature behavior.
However, the OP-Amplifier is the most critical block. The supply voltage used must ensure correct operation of the operational amplifier and, indeed, it is the true limit of the circuit.
So, how to design a good OP-Amplifier is an important issue and the detail will be presented in chapter 2 and chapter 4.
1.3 Review on CMOS Bandgap Reference Circuits (II)
There are several kinds of bandgap reference circuits. In this section, we will introduce and discuss the most representative circuits from the conventional one to the recently proposed ones. We can roughly classify the BGR circuits into two categories, the sum of voltage ( Class-A ) ; the sum of currents ( Class-B ).
1.3.1 The Class-A of Bandgap Circuit (The Sum of Voltage)
Case1: [5]
Case2 : [6]
1.3.2 The Class-B of Bandgap Circuit (The Sum of Current)
Case5 : [3]
Table-1 Classification of bandgap reference circuits Class A
(the sum of voltages)
Class B (the sum of currents) VDD > 1.0V case-1, case-2,
1.4 Organization of This Thesis
This thesis is divided into six chapters. In Chapter 1, the background and motivation are presented and the representative bandgap circuits are classified and introduced. Furthermore, we construct a complete classification as shown in Table-1.
In Chapter 2, Type A and Type B bandgap circuits based on the class B topology implemented by TSMC 0.18μm CMOS process was proposed. The design consideration is discussed in section 2.1. Then the design concepts including VREF and PSRR are presented in sections 2.2 and 2.3. The circuit realization is described in section 2.4.
In chapter 3, the circuits layout based on TSMC 0.18μm CMOS process is presented. The chip testing result and comparison with simulation are shown in the following subsections.
In Chapter 4, we improve the circuits topology proposed on chapter 2, to create two new types of bandgap circuits, which are named as Type C and Type D. The new topology ensures that the circuits can meet all process corners. The organization of chapter 4 is the same as chapter 2. The design consideration is discussed in section 4.1. Then the design concept is presented in section 4.2. The circuit realization is detailed in section 4.3.
In chapter 5, the circuits’ layout based on TSMC 0.35μm CMOS process is presented. The chip testing result and comparison with simulation are shown in the following subsections.
In chap 6, conclusion and future work are given.
Chapter 2 DESIGN OF LOW VOLTAGE HIGH PSRR BANDGAP REFERENCE CIRCUIT WITH TSMC 0.18μm CMOS PROCESS
2.1 Design Motivation
Until now, most OPAs in the bandgap circuits use pMOS as the differential pair because the conventional bandgap circuit topology limit the common mode voltage of OPA. For example, if we use nMOS as the OPA’s input stage then the input common-mode voltage of the OP-Amplifier must meet the following condition, as shown in Fig. 2-1 [3]：
VCOMM = Vthn + 2VDS(sat) < VEB(ON)≒ 650mV
The above condition implies that Vthn < 550mV is required (assuming VDS(sat) = 50mV). This requirement can be satisfied in many technologies, but it is only for TT (Typical – Typical) process. However, considering the other process corner (e.g. SS and SF), the above requirement cannot be easily satisfied. Take TSMC 0.18μm 1P6M CMOS technology as an example:
Vthn = 440mV at Typical case, but Vthn = 540mV at slow corner (S).
R2B R1
Q1 Q2
m=8 VREF
R2A R3
M3
M2 M1
VB VDD
Fig. 2-1 Bandgap circuit that uses nMOS as input stage
Because of the circuit structure limitation as mentioned above, most bandgap circuits were implemented by using pMOS as the OPA’s differential pair.
But there are two disadvantages when using pMOS as the differential pair. One is the smaller voltage gain due to the smaller gm for pMOS.
The other disadvantage is that the OPA’s offset voltage will be multiplied by )
1 (
1 2 1
3
A A
R R R
R + when using pMOS as the differential pair. By contrast, the OPA’s
offset voltage will only be multiplied by (
1 3
R
R ) if we use nMOS as the differential pairs NOTE_3.
NOTE_3
Discuss the impact of the OPA’s offset voltage on different bandgap circuit topology where Fig. 2-2 shows the pMOS as the OPA’s input differential pair while Fig. 2-3 shows the nMOS as the OPA’s input differential pair.
(A) Bandgap circuit that use pMOS as differential pair VDD
RB1 R1 IR1
IRA
Q1 Q2
m=8 VREF
RA2
IRB R3
I2 I3
M3 M2 M1
RB2 RA1
Vos
VA VB
Fig. 2-2 Bandgap circuit that uses pMOS as differential pair
(5) Unfortunately, Vos is not independent of temperature. Even worse, it will be multiplied by (1 )
R + , when using pMOS as differential pair.
(B) Bandgap circuit that use nMOS as differential pair
Fig. 2-3 Bandgap circuit that uses nMOS as differential pair
(2.5)
(4) Substituting m = 8
(2.8)
) ( )
8 ln (
2 3 2 1
3 1
3
B EB os T
REF R
V R R V
R R
V = R
φ
+ +(5) Unfortunately, Vos is not independent of temperature. But, it will only be amplified by (
1 3
R
R ), when using nMOS as differential pair.
So, in this chapter, we modify the bandgap core circuit to break through the limitation on OPA when using nMOS as the differential pair. Hope to create a new kind of bandgap circuit in which the OPA’s differential pair is composed of nMOS. In this way, the new topology of bandgap circuit will occupy less layout area but provide better performance than the existing topology using pMOS as the OPA’s differential pair.
2.2 Bandgap Reference Circuit Design Concepts (I)
R2B R1
Q1 Q2
m=8 VREF
R2A R3
M3
M2 M1
VB VDD
RX RY
I
Fig. 2-4 Bandgap circuit inserting RX, RY to upgrade common-mode voltage As shown in Fig. 2-4, after inserting another resistor pair, RX and RY, (as marked by red circle), the “the input common-mode voltage of the OP-Amplifier”
is no longer restricted to the VEB(ON), That is Vthn + 2VDS < VEB(ON) + I × RY ≒ 750 mV
So the bandgap core circuit will provide a common-mod voltage that is large enough to drive OPA’s nMOS differential pair and keep it working in the saturation region. Finally the OPA will provide large voltage gain to drive the bandgap core circuit,
It is another feature in this thesis that the output reference voltage can reach 760 ~ 800 mV, which is higher than the others proposed by existing papers, as
Table-2 Comparison of low-voltage bandgap reference test chip Technology 0.18-μm
CMOS Threshold Voltage Vthp = -0.44V
Vthn = +0.44V
Power Supply Range (工作電壓)
1.1 ~ 3.0V 1.1 ~ 3.0V 1.3 ~ 4.5V 1.1 ~ 4.5V
Max. Supply currets 38.1μA 34.4μA 54μA 41μA
Vref (參考電壓) 772mV 737mV 766mV 829mV
PSRR for 100KHz -15.2dB -26dB -0.1dB -0.42dB Size 0.192 mm2 0.145 mm2 0.294 mm2 0.238 mm2
Ka Nang Leung [3]
J. Doyle et al.
[2]
Neuteboom et.al [19]
Malcovati et al.
[1]
Technology AMS 0.6-μm CMOS
Power Supply Range (工作電壓)
0.98 ~ 1.5V 0.95 ~ 6.0V N / A 0.95 ~ 2.0V
Max. Supply currets 18uA 10.0uA N / A < 92.0uA
Vref (參考電壓) 603mV 626mV 670mV 536mV
TCF(eff) 15 ppm /℃
From Table-2, the output reference voltage proposed in this thesis is 760
~ 800mV, while the others is about 600 ~ 670mV. The reason is that HSPICE simulation suggests the best PSRR corresponding to Vref = Vd1 = Vd2 as shown in Fig. 2-5. Taking Fig. 2-5 with TSMC 0.18μm CMOS process as an example, the best PSRR performance occur at Vref = 675mV, marked by the red circle in the Table-3.
Table-3 Simulation result of PSRR at Vd1 = Vd2 = 670mV based on TSMC 0.18μm CMOS process
R3 70k 80k 90k 100k 110k 120k 130k
Vref 473mV 540mV 607mV 675mV 742mV 808mV 874mV PSRR(DC) -60dB -61dB -64dB -84dB -56dB -45.8dB -36.2dB PSRR(10kHz) -60dB -61dB -64dB -84dB -56dB -45.8dB -36.2dB
Note：PSRR = 20 log ( Vdd Vref Δ
Δ )
20/20 M=12
670 mV
20/20 M=12
Vdd 1.2Vdc
Vref
M1
0
Q1 Q2
R2A 185k
Vd1 Vd2
20/20 M=12
M3
1
3 2
4 OUT 11
+
-V+
V-m=24
670 mV M2
0 675 mV
R1
26k R2B
R3 185k 100k
Fig. 2-5 Conventional BGR circuit topology
However, Vref = 675mV cannot meet the industrial requirement. For IC design industry, the Vref should be 750mV ~ 800mV. But, if we increase the
Now, by inserting resistor pairs, RX and RY, we get another advantage：
increase Vd1 and Vd2 voltage to 760mV. In this manner, the PSRR is optimal corresponding to Vref = Vd1 = Vd2 = 760mV, as shown in Fig. 2-6 and Table-4.
0 R1 27k
m=24
LM324
1
3 2
4 OUT 11
+
-V+
V-760 mV
R2B 163k
Q1
20/20, M=12
Vd2 Rx
30k Ry
30k 20/20,
M=12 20/20,
M=12 M3
0 M1
760 mV
R3 100k Vref
M2 Vdd
1.2Vdc
767 mV
R2A
163k Q2
Vd1
Fig. 2-6 Modified BGR circuit topology proposed in this thesis
Table-4 Simulation result of PSRR at Vd1 = Vd2 = 760mV based on TSMC 0.18μm CMOS process, known Vd1 = Vd2 = 760mV
R3 80k 90k 100k 110k 120k 130k
Vref 540mV 607mV 767mV 742mV 808mV 874mV
PSRR(DC) -61dB -64dB -69dB -56dB -45.8dB -36.2dB PSRR(10kHz) -61dB -64dB -69dB -56dB -45.8dB -36.2dB
In this thesis，we provide Vref ≒ 735 ~ 800 mV, which is higher than the output reference voltages provided by other papers, i.e. around 600mV, and much more meet the industrial requirement. Besides, we can keep the PSRR at the optimal state and maintain a well-controlled temperature compensation performance as shown in the Table-2.
2.3 Bandgap Reference Circuit Design Concepts (II)
The preceding description is based on the simulation result. In order to get more conviction, we try to formulate the simulation result by using MOS small signal model and equivalent circuit to analyze.
(1) For simplification, we only analyze the mechanism of the PSRR of M3, as marked by the circle shown in the Fig. 2-6.
0 R1 27k
m=24
LM324
1
3 2
4 OUT 11
+
-V+
V-760 mV
R2B 163k
Q1
20/20, 20/20, M=12
M=12 20/20,
M=12
Vd2 Rx
30k Ry
30k M3
0 M1
760 mV
R3 100k Vref
M2 Vdd 1.2Vdc
767 mV
R2A
163k Q2
Vd1
Fig. 2-6 Modified BGR circuit topology proposed in this thesis
(2) Set up the equivalent circuit of pMOS M3 for analyzing the mechanism of the PSRR as shown in Fig. 2-7.
R3 1.00093Vac Vg
1.5Vdc
Vdd 1Vac Vdd
3Vdc
0 20/20
Vo M=12
M3 Vref
The small signal model as shown in Fig. 2-8：
Fig. 2-8 Small signal model analysis of pMOS device (M3) for PSRR study
The PSRR formula can be derived as follow：
Vdd
From Table-4, we know that PSRR will be at the optimal state when Vd1 = Vd2 = 760mV.
We now analyze the device parameter based on different bandgap reference voltage (Vref) as shown in Table-5.
Table-5 Simulation result of the different bandgap reference voltage based on TSMC 0.18μm CMOS process
R3 70k 80k 100k 110k 130k
Vref 538mV 540mV 767mV 742mV 874mV
Id 7.68uA 6.75uA 7.67uA 6.74uA 6.72uA
gm 92.9u 85.6u 92.7u 85.5u 85.2u
Vds 661mV 659mV 432m 458mV 325mV
gds 61.6n 55.48n 103n 81.0n 187n
ro 16.2M 18.02M 9.70M 12.3M 5.34M
ΔVref / ΔVdd -2.69m -873.5u 334u 1.60m 15.4m Vo / Vdd 1.0010799 1.0007751 1.0010799 1.0007751 1.0007751 PSRR (DC) -51.3dB -61dB -69.5dB -55.9dB -36.2dB
Cdtot 295f 295.8f 309f 308f 317f
Cgtot 27.3p 26.9p 27.3p 26.9p 26.9p
Cstot 31.8p 31.08p 31.8p 31.08p 31.08p
Cbtot 11.1p 11.12p 11.1p 11.12p 11.12p
Cgs 23.5p 22.95p 23.5p 22.95p 22.95p
Cgd 78.6f 78.60f 78.6f 78.60f 78.60f
Wp(rad/sec) -48.5M -42.44M -32.6M -29.7M -24.7M Wz(rad/sec) -2.69M -1.37M -6.35M -3.00M -7.88M For hand calculation：
R3 = 70k Vdd
Vref = gm R3 (
Vdd
− Vo
1 )＋( )
3 3
R r
R
o + =92.9u * 70k(1-1.0010799) +
K M
k 70 2
. 16
70 +
= - 0.0070225 + 0.0043023
= - 0.00272 = - 2.72m
PSRR for DC = |
Vref | Vdd dB ＝ 20 log (2.72m) = - 51.3dB ( S：- 51.4dB ) And the frequency of dominant pole
(1) R3 = 100k
Vref = gVdd m R3 (
Vdd
− Vo
1 )＋( )
3 3
R r
R
o +
= 92.7u * 100k(1-1.0010799) +
K M
k 100 7
. 9
100 +
= - 0.0100106 + 0.010204
= 0.0001934
= 193.4u
PSRR for DC = |
Vref | Vdd dB ＝20 log (193.4u) = - 74.26dB ( S：- 69.5dB ) Good match with the simulation , PSRR = - 69.5 dB
(3) R3 = 130k
Vref = 85.2u × 130k (1-1.0007751) + Vdd
K M
k 130 34
. 5
130 +
= - 0.008585 + 0.0237659
= 0.0151809
= 15.18m
PSRR for DC = |
Vref | Vdd dB ＝20 log (15.18m) = - 36.37dB ( S：- 36.2dB) Good match with the simulation , PSRR = - 36.2 dB
Conclusion：
From the derived formulas, we see that PSRR is composed of two terms.
The first term is always a negative value, while the second term is always a positive value. When Vd1 = Vd2, the first term and the second term cancel each other. That behavior makes the PSRR approach to minimum value, that is, best performance. So, the theoretical analysis of MOS small signal equivalent circuit can prove the simulation result.
2.4 Circuit Implementation
In chapter two, there are two types of BGR circuits. The bandgap core circuits are the same, as shown previously, but the OP-Amplifiers are different.
The first circuit (a conventional one) named as Type A uses pMOS as the input stage, as shown in Fig. 2-9, while the second circuit celled as Type B uses nMOS as the input stage, as shown in Fig. 2-10.
Here, one important thing we want to mention is that in conventional BGR circuits, the emitter area ratio of BJT Q1 and Q2 is usually 8：1. So, the △VBE is about 50mV in the conventional BGR circuits.
Note：△VBE ＝ ΦT * ln(m) ＝ 26mV * ln (8) ＝ 54.06mV But, According to reference paper [2]：
“ A large△VBE can reduces the effect of amplifier input offset ”。
And this conclusion can be verified by the formulas (2.3) or (2.7).
So, in this thesis, we put the emitter area ratio of BJT Q1 and Q2 to 24：1. In this way, the △VBE is increased to around 80mV。
Finally, the simulated features of the two types of OP-Amplifier are summarized in Table-6.
Table-6 Operational Amplifier features of Type A and Type B
Type A
pMOS as the input stage
Type B
nMOS as the input stage
DC Loop gain 65 dB 70 dB
Gain-Bandwidth product
6.5 MHz 10.5 MHz
Phase Margin 51.8° 80.1°
Supply Voltage 1.10 V 1.10 V
Here below is the complete circuit topology of Type A and Type B
diff 70kR2A2
MA08 MA09
R2B1diff 105k R2A1
Fig. 2-9 The complete bandgap circuit topology of Type A (bandgap core + start-Up + OP-Amplifier with pMOS input stage)
Bandgap core start-Up OP-Amplifier Rs1diff 1000k
Vnon
R2Bdiff 175k m=12 Rs2diff 300k
20/20
20/10
diff 175kR2A
MA03 MS1
Rypo 14k m=12
MA02
Fig. 2-10 The complete bandgap circuit topology of Type B (bandgap core + start-Up + OP-Amplifier with nMOS input stage)
Chapter 3 CHIP LAYOUT DESCRIPTION AND EXPERIMENTAL RESULTS WITH
TSMC 0.18μm CMOS PROCESS
3.1 Chip Layout Descriptions
The test chip is designed and fabricated by TSMC 0.18μm single-poly-six- metal (1P6M ) CMOS technology. Fig. 3-1 shows the overall die photo of the Type A and Type B, which include the bandgap core circuit and OP-Amplifier.
The chip area is 0.192 mm2 for Type A and 0.145 mm2 for Type B. The transistors used are totally 21 for Type A, 15 for Type B.
The bandgap core circuit in Fig. 3-1 consists of the startup circuits, bipolar transistors, bias resistors, and the MOS transistors that provide the current through the bias resistors and the BJT group (Q1 & Q2), respectively. Since the mismatching of the MOS transistors in the differential pair will make the current different, the same size MOS transistors are placed as close as possible to minimize this kind of mismatching.
The most important devices in the bandgap circuit are the bipolar transistors with large thermal coefficient. The parasitic vertical PNP BJTs are used in this test chip. The layout should be arranged carefully to ensure matching and accurate ratio of these BJTs. Thus, we choose the ratio of the emitter area of Q1 and that of Q2 to be 24, and arrange the 24 Q1s to circulate the single Q2. The reason why we choose the ratio to be 24 has been explained in the section 2.4. The total emitter area of Q1 is 2400um2 and that of Q2 is 100 um2 in this layout. This arrangement not only reduces the mismatching of these bipolar transistors, but also makes the temperature coefficient of these bipolar transistors as close as possible
.
The accuracy of the resistance value on the chip is the most difficult job to realize in the process. Hence, the output reference voltage is designed to be dependent on the ratio instead of absolute value. Besides, a unit dimension of the resistors is defined, and all the resistors are series-connected by the unit resistors in order to reduce the mismatching of the resistors arising process
Type A(pMOS as OPA input stage) Type B(nMOS as OPA input stage)
Fig. 3-1 The overall die photo of the Type A and Type B
Note：In this test chip, a set of I/O PAD library developed by ITRI (Industrial Technology Research Institute) was chosen to use. The detailed library name is “STC Pure 1.8V Linear I/O Library in 0.18μm CMOS process, version 1.0”
3.2 Measurement Setup
(1) The set up required to measure “Vref (Reference Voltage) vs. Vdd ” are power supply and voltage meter.
(2) The set up required to measure “Transient Response curve” are power supply, function generator, and Oscilloscope。Fig. 3-2 shows an example of measured transient response for Type B (nMOS as OPA’s input stage) where the output voltage of the function generator is set up from 1.3V to 2.3V。
(2) The set up required to measure “Transient Response curve” are power supply, function generator, and Oscilloscope。Fig. 3-2 shows an example of measured transient response for Type B (nMOS as OPA’s input stage) where the output voltage of the function generator is set up from 1.3V to 2.3V。