Chapter 2 DESIGN OF LOW VOLTAGE HIGH PSRR BANDGAP
4.2 Design Concepts and Circuit Implementation
4.2.1 Design Concepts and Circuit Implementation of Type D
Fig. 4-2 shows a complete circuit topology of Type D in which bandgap core, start up, and OP-Amplifier circuits are incorporated.
bandgap core start-Up OP-Amplifier
5k Rx
5/1m=30 20/20
10/5m=2 10/10 m=3
Fig. 4-2 The complete bandgap circuit topology of Type D ( bandgap core + start-up + OP-Amplifier with nMOS input stage )
The idea of Type D circuit comes from the previous work done by P.
Malcovati et al. [1] as shown in Fig. 4-3 and Fig. 4-4. We modify the circuit presented in the referred work to create the Type D circuit.
R2
Q1 Q2
1
VREF
R2
R3 M3 M2
M1
VA
R1
N
VB VC
I1 I2 I3
Fig. 4-3 Schematic of bandgap circuit proposed by the previous work done by P. Malcovati et al. [1]
Fig. 4-4 Schematic of the two-stage operational amplifier
In Fig. 4-4, M1 and M2 are current sources; Q1 and Q2 are differential amplifiers.
We created a similar topology as shown in Fig. 4-5. The difference is that we use nMOS (MB02, MB03) as the differential pair to replace the BJT Q1, Q2
Q2 Q1
Vd2
MB03
MA15 MA09
Vo
0
m=24 Ry
MA10
Vref Vd1
MA04
0 R1
MA01
MA12 R3
M3
R2A
MA11 Rx
MB02
MA02
MA14
R2B
Vdd 1.2Vdc
Vo
MA13 MA03
M2
MA08 M1
Fig. 4-5 Prototype-1 circuit topology of Type D
But this kind of circuit reveals a serious disadvantage in that it can only pass TT, but fails at all other corners FF, SS, FS, SF.
We analyze the cause of failure and find that at the different process corners, the gate voltages of the OPA’s differential pair, which is provided by the bandgap core circuit, keep the same, but the Vthn of the nMOS of the differential pair are different. This physical phenomenon will make the biased current change at the different process corners.
To speak clearly, we want to keep the bias point the same at the different process corners, but in fact the bias point will shift at various process corners.
This is why this kind of OPA can only work at TT, but fails at the other corners.
Taking TSMC 0.35μm CMOS process and model as an example, we can see the relationship between Vthn and temperature at various corners as shown in Fig. 4-6.
141℃ 25℃ －45℃
Fig. 4-6 Vthn vs. temperature at various corners
In order to solve the corner failure issue mentioned for prototype-1 circuit of Type D in Fig.4-5, we add a current source below the differential pair. That result in the prototype-2 circuit of Type D as shown in Fig. 4-7.
R2B
0
MB03
Vo Vd1
MA10 Vd2
M3
R2A
MB02
MA15
MA08 MA09
Vref
0
MA04
MA11 Ry
MA02 R3
Q2
Vdd 1.2Vdc
R1
Vo
M2
MA14 M1
MA01
MA03 MA13
Q1 Rx
m=24
MA12 Imb23
432 mV 536 mV 600 mV
141℃ 25℃ －45℃
332 mV 436 mV 500 mV
141℃ 25℃ －45℃
332 mV 436 mV 500 mV
141℃ 25℃ －45℃
532 mV 636 mV 700 mV
141℃ 25℃ －45℃
532 mV 636 mV 700 mV TT
FF
FS
SS
SF
Fig. 4 -7 Prototype-2 circuit topology of Type D
However, the temperature effect on the VBE and Vthn should be considered.
We find that the node voltage Vd1 & Vd2 can not drive the OPA at high temperature even though the nMOS threshold voltage (Vthn) degrade as the ambient temperature rise. In other words, the down slope of the node voltage Vd1 & Vd2 vs. temperature curve is falling sharply than the slope of the nMOS threshold voltage (Vthn) vs. temperature as shown in Fig. 4-8, Table-12 and Table-13.
Fig. 4-8 Node voltage Vd1 vs. temp. of the prototype-2 circuit of Type D Table-12 Node voltage Vd1 vs. temp. of the prototype-2 circuit of Type D
-45℃ -20℃ 25℃ 125℃ 140℃
Vd1(mV) 885 840 756 563 533
Table-13 The Vthn of TSMC 0.35μm CMOS process
-45℃ -20℃ 25℃ 125℃ 140℃
Vthn (mV) at S 700 676 636 545 532
Vthn (mV) at Typical 600 577 536 445 432
Comparing node voltage Vd1 in the Table-12 with the Vthn at slow corner (S) in Table-13, we find that:
1. The worst case does not occur at the low temperature but at the high temperature. From Table-12 and 13, we see that the Vd1 is almost equal to Vthn at corner S and T = 140℃. So this circuit topology is still not useful for all process
2. The temperature coefficient of the base-emitter voltage is approximately -1.85mV/K while that of the threshold voltage of the nMOS transistor is around -1.0mV/K in TSMC 0.35μm CMOS technology. That is, at high temperatures, VEB(on) may be less than Vthn + 2VDS(sat), and the bandgap reference circuit will not function properly.
To fix this problem, we insert another resistor pairs, RA & RB, as shown in Fig.4-9. The purpose is to change the down slope of “Vd1 vs. temperature” curve as shown in Fig.4-10.
Ry
MA15
0 MA02 RA Vd1 Rx
MA08
Q1
MA11 Vref
MA01
Q2
Vo
R1
m=24
Vdd 1.2Vdc
MB23 MB02
R2B
MB03
MA12 R3
MA09
MA10 Vo
MA04
Vd2
MA03 MA13
M2
RB M3
R2A
0 M1
MA14
Fig. 4-9 The final circuit topology of Type D
Fig. 4-10 Node voltage Vd1 vs. temperature curve of the Type D
Fig. 4-10 and Table-14 show the relationship of node voltage Vd1 and temperature for the Type D final circuit.
Table-14 Node voltage Vd1 vs. temperature curve of the Type D -45℃ -20℃ 25℃ 125℃ 140℃
Vd1(mV) 904 868 801 645 621
After comparing Table-13 and 14, we can make a conclusion：after inserting resistors RA & RB, the down slope of the “Vd1 vs. Temperature“ curve has changed. That will make the node voltage, Vd1, large enough to drive the nMOS (of the OPA’s differential pair) at all process corners with temperature range from - 40℃ to 140℃
What reason makes the slope of “Vd1 vs. Temperature” curve change after inserting RA & RB? The answer can be found by the node voltage analysis as shown in Fig. 4-11:
Fig. 4-11 The simplified bandgap circuit topology of Type D
1. We want to change the slope, ξ, of the curve of the “Vd1 vs. Temperature”, which can be expressed as Vd2 = ξ × T ＋ K
2. Vd2 = VY + ( IR1 ＋ IR2A ) Ry = VY ＋ K
3. VY = IR1 RB ＋ VEB2 = ΦT ln24 (RB / R1) ＋ VEB2
4. We can get that Vd2 = ΦT ln24 (RB / R1) ＋ VEB2 ＋ ( IR1 ＋ IR2A )Ry
= ξ × T ＋ K