Chapter 2 DESIGN OF LOW VOLTAGE HIGH PSRR BANDGAP
3.3 Experimental Results
3.3.2 Experimental Results of Type B
PART (I) Vref (Reference Voltage) vs. Vdd (1) Measured Result of Type B
n-Vref vs. Vdd
400 450 500 550 600 650 700 750 800
0 0.5 1 1.5 2 2.5 3 3.5
Vdd (V) n-Vref (mV)
IC No.1 IC No.2 IC No.3 IC No.4 IC No.5 IC No.6
Fig. 3-14 Measured n-Vref vs. Vdd of Type B
Average of n-Vref
400.0 450.0 500.0 550.0 600.0 650.0 700.0 750.0 800.0
0 0.5 1 1.5 2 2.5 3
Vdd (V)
n-Vref (mV)
n-Vref_mean
Fig. 3-15 Average of measured n-Vref vs. Vdd of Type B Note : mean value = 737.0 mV STD value = 7.3mV
PART (II) Temperature Compensation Curve
(1) Simulation Result of Type B at TT
Fig. 3-16 Simulated TC curve of Type B under typical condition axis X : temperature (℃) ; axis Y : n-Vref (mV)
(2) Measured Result of Type B
TC curve of n-Vref_ N0.7 at Vdd=1.2v
735.0 740.0 745.0 750.0 755.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 140 temprature (℃)
n-Vref (mV)
Fig. 3-17 Measured temperature compensation curve of Type B
TCF(eff) = 745mv
1 (
) 40 ( 140
735 755
−
−
− mV )＝ 149 ppm/℃
Why does this IC chip fail to show the correct function of the temperature compensation? The process variation suffered by diffusion resistor and poly resistor is the root cause. We will have a detailed explanation on next paragraph.
(3) Experimental Result Discussion
Take Type B (nMOS as OPA’s input stage ) circuit as an example：
At first, we make sure the OPA can work normally, that is, the inverter port and non-inverter port keep at the virtual short condition, as shown in Table-8.
Table-8 Measured input port and output port voltage of OPA of Type B circuit at different power supply voltage
OPA Port Vnon (mV) Vinv (mV) Vref (mV) Vo (OPA) Vdd - Vo Vdd =3.0 764 767 754 2.44V 0.560V Vdd =1.5 762 761 740 0.941V 0.559V Vdd =1.2 761.1 761 738.4 0.640V 0.560V Vdd =1.0 751.5 751.1 748.5 0.360V 0.640V
Next, we use voltage meter to measure each resistor value of the bandgap circuit in the IC chip, as shown in Table-9.
Table-9 Comparison of the design target and measured data of resistors of Type B circuit
Element name design target measured data Difference RX + R1 PP+ Poly w/i silicide 29k 29.1k + 0.3 % R2A PP+ Diff w/o silicide 175k 153.9k - 12.0 % R2B PP+ Diff w/o silicide 175k 154.1k - 11.9 % R3 PP+ Diff w/o silicide 80k 70.5k - 11.8 % RS1 + RS2 PP+ Diff w/o silicide 1300k 1147k - 11.7 % Note：We use voltage meter via I/O pad of the IC chip to measure the
OPA port voltage and calculate the actual resistor values.
From Table-9, we see that during the manufacture the poly resistance deviation due to process variation keep below 0.3%; however, the diffusion resistance reveals the deviation as high as 12% due to process variation. That is the reason why the circuits failed to meet TC (temperature compensation) target.
For getting more persuasive data, we put the measured resistor values into HSPICE to get the updated simulation result of Vref vs. Vdd.
After putting the updated simulation result and the measurement data together for comparison, we can see that two curves match to each other shown in Fig. 3-18.
Comparison between simulation and measurement
400.0 450.0 500.0 550.0 600.0 650.0 700.0 750.0 800.0
0 0.5 1 1.5 2 2.5 3
Vdd (V)
n-Vref (mV)
n-Vref_mean Simulation
Fig. 3-18 Comparison of n-Vref vs. Vdd of new Type B-1 between simulation and measurement
This experiment gives us strong evidence to believe that the measured resistor values of the IC chip via the I/O pad are reasonable.
Using the same way, we can get the updated simulation result of temperature compensation curve.
After that, we put the updated simulation result and the measurement data together for comparison. We can see that two curves better match to each other as shown in Fig. 3-19.
Comparison between simulation and measurement
725 730 735 740 745
-40 -20 0 20 40 60 80 100 120 140
Temperature (C)
n-Vref (mV)
Simulation IC No.7
Fig. 3-19 Comparison of TC curve of new Type B-1 for simulation and measurement
Currently, we can confirm the reason responsible for the failure of the circuit in TC target. The reason comes from the different process variation between the diffusion resistor and poly resistor. If all the resistors in circuit adopted the same material, either diffusion or poly, during the layout drawing, then we can get a reasonably good measured TC curve for the bandgap circuit.
PART (III) Transient Response：
(1) Simulation Result of Type B at TT
Fig. 3-20 Simulated transient response of Type B under typical condition upper axis X : time (sec) ; axis Y : Vdd (V)
lower axis X : time (sec) ; axis Y : n-Vref (mV)
(2) Measured Result of Type B
Fig. 3-21 Measured transient response of Type B at AC mode upper axis X : time (sec) ; axis Y : Vdd (V)
lower axis X : time (sec) ; axis Y : n-Vref (mV)
PART (IV) PSRR (Power Supply Rejection Ratio)
(1) Simulation Result of Type B under typical condition and Vdd = 1,15V
Fig. 3-22 Simulated PSRR of Type B under typical condition axis X : frequency (Hz) ; axis Y : PSRR of n-Vref (dB)
(2) Measured Result of Type B by using network analyzer and oscilloscope Following the same way, we put the measured data and the simulated data together for comparison, as shown in Fig. 3-23.
1 0 0 1 k 1 0 k 1 0 0 k 1 M 1 0 M
- 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0
PSRR(dB)
F r e q ( H z )
M e a s u r m e n t S i m u l a t i o n
P S R R ( n M O S d i f f - p a i r ) a t V d d = 1 . 1 5 v
S i m .
M e a .
Fig. 3-23 Comparison of the measured and simulated PSRR for Type B under Vdd = 1.15V
Table-10 Summary table of PSRR for Type B at Vdd = 1.15V
PSRR at 1.15V DC dB 10K dB 50K dB 114K dB 500K dB 1M dB simulation -50.4 -37.4 -23.2 -15.0 -10.2 -9.9 measurement -51.5 -33.8 -28.4 -26.7 -14.8 -13.9
Spec. <-60 <-30 N/A N/A N/A N/A
And Fig. 3-24 shows the PSRR performance of Type B under various Vdd, 1.0V, 1.1V, 1.2V, 2.5V
1 0 0 1 k 1 0 k 1 0 0 k
- 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5
1 .2 V
V d d = 2 .5 V 1 .1 V
PSRR (dB)
F r e q .( H z ) V d d = 1 .0 V
V d d = 1 .1 V V d d = 1 .2 V V d d = 2 .5 V
P S R R ( n M O S d if f- p a ir ) f o r v a r io u s V d d
V d d = 1 .0 V
Fig. 3-24 Measured PSRR vs. frequency of Type B under various Vdd, 1.0V, 1.1V, 1.2V, 2.5V
(3)Experimental Result Discussion
1. Both simulated and measured results suggest that the higher power supply voltage, the better PSRR.
2. Fig. 3-25 shows the comparison of the pre-layout simulation and the post-layout simulation.
1 0 0 1 k 1 0 k 1 0 0 k 1 M
Fig. 3-25 Comparison of the pre-layout simulation and the post-layout simulation
3. From Fig. 3-25, we see that the post-layout simulation deviated from the pre-layout simulation since frequency above 1KHz. What factor causes the PSRR to become worse with increasing frequency above 1KHz ? The root cause maybe come from layout symmetry of pMOS M1, M2, M3 as shown in Fig. 3-26.
R2Bdiff 175k R1po 15k
R3diff 80k
20/10
Rs1diff 1000k
diff 175kR2A
20/10
Fig. 3-26 pMOS M1, M2, M3 in the bandgap type B circuit
The verification was done by skipping the layout drawing of the pMOS M1, M2, M3 and supporting them as ideal devices .The results shown in Fig. 3-27 indicates better match between pre-layout and post layout simulation.
1 0 0 1 k 1 0 k 1 0 0 k 1 M
-6 0 -5 0 -4 0 -3 0 -2 0 -1 0 0
p o s t w /o M 1 , M 2 , M 3 p r e
PSRR (dB)
F re q . (H z ) p r e -la y o u t S im u la tio n p o s -la y o u t S im u la tio n p o s -S im . w /o M 1 ,M 2 ,M 3
P S R R c o m p a ris o n (n M O S ) b e tw e e n p o s -S im . a n d p o s - S im . w /o M 1 ,M 2 ,M 3
p o s t w /i M 1 , M 2 , M 3
Fig. 3-27 The post-layout simulation of the PSRR of the experiment
Chapter 4 DESIGN OF LOW VOLTAGE HIGH PSRR BANDGAP REFERENCE CIRCUIT WITH TSMC 0.35μm CMOS PROCESS
4.1 Design Motivation
In chapter 2, we demonstrated two kinds of bandgap reference voltage circuits by using TSMC 0.18μm CMOS process as shown in Fig. 2-9.
5/10
diff 70kR2A2
MA08 MA09
R2B1diff 105k R2A1
However, using this circuit topology, the differential pair MOSFET in OPA cannot work in saturation region for all process corners if we use low-end and low cost process, e.g. TSMC 0.35μm CMOS process.
For example：The pMOS differential pair, MA08 & MA09, will be forced into triode region at the process corner SF and 125℃. The cause comes from the MOS-connected diode as shown in Table-11 and circuit schematic in Fig. 4-1.
Table-11 Threshold voltage of nMOS & pMOS at different corners
-469
570 mV
0 Vds= 545 MA08
Vcm=100mV
MA11
Vds= 545
0
MA09
MA10
Vds 25mV
Vsg= 470 Vsg= 470
Vds25mV Vcm=100mV
Fig. 4-1 Detailed analysis of the OPA’s differential pair
For T=125℃, the nMOS threshold voltage, Vthn, at slow corner (S), is 545mV, and the pMOS threshold voltage, Vthp, at fast corner (F), is about -470mV. This implies that the pMOS differential pairs (MA08, MA09) will be forced into triode region if we assume the common mode voltage is 100mV.
So, in chapter 4 we evaluate other kinds of OPA architectures, aiming to find others of OPA architectures that can work at low voltage and all process corners if a low-end and low cost process is used, e.g. TSMC 0.35μm CMOS process.
The same as chapter 2, there are two kinds of bandgap circuits in this chapter. The purpose is to verify technology-scaling effect on BGR circuit performance.
The first circuit (Type D) use nMOS as its OPA’s differential pairs. The main difference (compared with the previous circuit – Type B in chapter 2) is that we use current source instead of current mirror.
Besides, the temperature effect on the base-emitter voltage and threshold voltage should be considered. So we modify the bandgap core circuits by inserting resistors. The reason is that we want to change the slope of OPA’s common mode voltage vs. temperature. To speak clearly, the OPA’s common mode voltage provided by the bandgap core circuit will degrade as the ambient temperature is rising.
For example, the temperature coefficient of the base-emitter voltage is approximately -1.85mV/K while that of the threshold voltage of the nMOS transistor is around -1.0mV/K in TSMC 0.35μm CMOS technology. That is, at high temperatures, VEB(on) may be less than Vthn + 2VDS(sat) , and the bandgap reference circuit will not function properly.
But after modifying the bandgap core circuit, the OPA’s differential pair can work in the saturation region even at the worst case (e.g. corner SS, SF, and T = 125℃).
The second circuit (Type C) use pMOS as its OPA’s differential pair. The main difference (compared with the corresponding circuit – Type A in chapter 2) is that we use current sources instead of the MOS-connected diodes. Besides, we put two CG (common gate) nMOS as the current followers at the output stage in order to get a stable biased voltage and biased current. This kind of topology is different from that of Type A (pMOS as OPA’s differential pair). The reasons will be presented in the following sections.