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CONCLUSIONS AND FUTURE WORKS

6.1 Conclusions

According to the theory and simulated data, we think if the OP-Amplifier’s input stage can be implemented by using nMOS, the bandgap circuit performance will be better. Now this assumption has been verified by the measurement result. It is clear that bandgap circuit with nMOS differential pairs will have better performance and enable lower cost due to reduced chip area no matter TSMC 0.18μm process or TSMC 0.35μm process.

(1) Output Reference Voltage vs. Vdd:

For TSMC 0.18μm, the STD value of Type A (pMOS as OPA input stage ) is 42.6 mV as shown in Fig. 3-6;however, The STD value of Type B(nMOS as OPA input stage ) is only 7.3mV as shown in Fig. 3-15. So, Type B circuit is superior to the Type A.

For TSMC 0.35μm, the STD value of Type C (pMOS as OPA input stage ) is 53.6 mV as shown in Fig. 5-17;however, The STD value of Type D (nMOS as OPA input stage ) is only 12.8mV as shown in Fig. 5-4. So, Type D circuit is superior to the Type C.

(2) Temperature Compensation Curve:

For TSMC 0.35μm, the TCF(eff) of Type D is only 34.1 ppm/℃ as shown in Fig. 5-6;however, That of Type Cis 90.2 ppm/℃ as shown in Fig. 5-19. So, Type D circuit is superior to the Type C.

(3) Transient Response:

For TSMC 0.18μm, after comparing Fig. 3-10 and 3-21, we can see that Type B is obviously superior to the Type A.

For TSMC 0.35μm, after comparing the measured waveform of Type D as shown in Fig. 5-12 with the correspondent waveform of Type C as shown in Fig. 5-21, we see that at the same test environment the peak to peak voltage of Type D is equal to 159mV ; the peak to peak voltage of Type C is

(4) PSRR (Power Supply Rejection Ratio):

For TSMC 0.18μm, by comparing Fig. 3-13 and 3-24, we can see that Type B circuit is superior to the Type A.

For TSMC 0.35μm, by comparing Fig. 5-14 and 5-23, we can see that Type D circuit is superior to the Type C.

6.2 Future Works

Nowadays, the bandgap reference circuits have been widely used in battery-operated portable application. As the coming of deep-submicron technology and the low supply voltage, the demand for the low voltage and low power of bandgap reference circuits have been on the increase.

The minimum supply voltage of the conventional BGR circuits is constrained by two factors. One is the output reference voltage that is around 1.25V, equal to the silicon energy gap measured in electron volts. The other is the low operating voltage of operational amplifier. The first constrain have been solved by the resistive subdivision methods. As for the second constrain, we use low threshold voltage devices to lower the OPA’s operating voltage. But, the input common-mode voltage of the OP-Amplifier is still an issue when we try to design the low-voltage bandgap core circuit. In other words, the input common-mode voltage of the amplifier limits the low-voltage design of the bandgap core circuits. In the future, the proposed circuits can be modified and improved in these directions.

Besides, the PSRR (Power Supply Rejection Ratio) is another important factor to evaluate the performance of the bandgap reference circuit. In this paper, the effort that we put to study the impact of device parameters on the performance of PSRR is not enough. In the future, this can be another study topic.

Finally, the chip size is another concern in IC design industry. In this thesis, the layout area of the all the proposed circuits is a little bigger than expected, although not bigger than those proposed by the other papers. In the future, the proposed circuits can be improved in these directions.

REFERENCES

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簡 歷

姓 名: 王冀康

學 歷:

國立新竹高級中學 (73 年 9 月~76 年 6 月)

國立交通大學機械工程學系 (76 年 9 月~80 年 6 月)

國立交通大學電子工程研究所碩士班 (92 年 9 月~95 年 6 月)

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