Conclusions

Ge PMOS capacitors using post deposition oxidation method to form a thin GeOx IL by oxidizing Ge surface beneath an ALD Al2O3 layer using high-k RTO was fabricated, the dependence of the GeO_x/Ge interface qualities on the post deposition oxidation conditions such as post deposition oxidation temperature and post

deposition annealing ambient was investigated. Theory of the conductance method was discussed in detail, including weak inversion response. The Ge 3d XPS spectra of Al₂O_3/GeO_x/p-Ge with PDO 520 °C 30sec, PDO 520 °C 3min, PDO 550 °C 3min and RTO thermal GeO2 520 °C 30sec is shown, the increase of post deposition oxidation time or temperature will larger the Ge³⁺peak. The Ge³⁺ peak shows better interface quality than Ge⁴⁺ peak in our studies.

The EOT value was scaled down to 1.41 nm and a lower D_it value was obtained by PDO. The larger EOT but lower Dit value was obtained by using O2 annealing. The positive V_FB shift and lower C-V hysteresis is shown in the samples after FGA, and the Dit value has been reduced 16% ~ 44% after FGA. Finally, the HfO2/Al2O3 gate stack with PDO 520°C 3min, PDA 500°C 60sec N₂ was choose to be the best condition to fabricate Ge MOSFETs.

References (Chapter 2)

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Li, and D. L. Kwong, “ ery low defects and high performance

Ge-on-insulator p-MOSFETs with Al2O3 gate dielectrics,” in Symp. VLSI Tech. Dig., pp. 119–120, 2003.

[2] W. P. Bai, N. Lu, J. Liu, A. Ramirez, D. L. Kwong, D. Wristers, A.Ritenour, L. Lee, and D. Antoniadis, “Ge MOS characteristics with CVD HfO gate dielectrics and Ta gate electrode,” in Symp. VLSI Tech. Dig., pp. 121–122, 2003.

[3] Y. Nakakita, R. Nakane, T. Sasada, H. Matsubara, M. Takenaka, and S.

Takagi, “Interface-controlled self-align source/drain Ge pMOSFETs using thermally-oxidized GeO2 interfacial layers,” in IEDM Tech. Dig., pp.

877–880, 2008.

[4] R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, S. Takagi, “High-Mobility Ge pMOSFET With 1-nm EOT Al2O3/GeOx/Ge Gate Stack Fabricated by Plasma Post Oxidation,” IEEE Trans Electron Devices, vol 59 , pp.335, 2012.

[5] R. Zhang, T. Iwasaki, N. Taoka,M. Takenaka, and S. Takagi, “Suppression of ALD-induced degradation of Ge MOS interface properties by low power plasma nitridation of GeO2,” in Proc. Ext. Abstr. SSDM, pp. 33–34, 2010.

[6] R. Zhang, T. Iwasaki, . Taoka, M. Takenaka, and S. Takagi, “Impact of GeOx interfacial layer thickness on Al2O3/Ge MOS interface properties,”

Microelectron. Eng., vol. 88, no. 7, pp. 1533–1536, Jul. 2011.

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[8] T. Hosoi, K. Kutsuki, G. Okamoto, M. Saito, T. Shimura, and H.Watanabe,

“Origin of flat band voltage shift and unusual minority carrier generation in thermally grown GeO2/Ge metal-oxide-semiconductor devices,” Appl Phys Lett, vol 94, 2009.

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Delabie, S. Van den Berghe, X. Qu, and C. Detavernier, "Effective reduction of fixed charge densities in germanium based metal-oxide-semiconductor devices," Appl. Phys. Lett., vol.99, pp. 052906, 2011.

[10] A. Delabie, F. Bellenger, M. Houssa, T. Conard, S. V. Elshocht, M. Caymax, M. Heyns, and M. Meuris, “Effective electrical passivation of Ge(100) for high-K gate dielectric layers using germanium oxide,” App. Phys. Lett., vol.

91, pp. 082 904, 2007.

[11] E.H. icollian and A. Goetzberger, “The Si–SiO2 Interface—Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique,” Bell Syst. Tech. J., vol 46, pp. 1055–1133, 1967.

[12] K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. Heyns,T. Krishnamohan, K. Saraswat, H. E. Maes, G. Groeseneken,

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547-555, Feb. 2008.

Fig. 0.1 The process flow and device structure with different PDA condition.

Fig. 0.2The process flow and device structure with different post deposition oxidation condition.

Table 0.1 The overview of a-d samples with different PDA condition.

Table 0.2 The overview of A-D samples with different RTO condition.

No. Thermal

(a) (b)

(c) (d)

Fig. 0.3 The multi frequency C-V of Ge MOSCAPs with different PDA condition. (a) RTO thermal GeO2 520°C 30sec with PDA 500°C 60sec N2 (b) RTO thermal GeO2

520°C 30sec with PDA 500°C 60sec O₂ (c) post deposition oxidation 520°C 3min with PDA 500°C 60sec N2 (d) post deposition oxidation 520°C 3min with PDA 500°C 60sec O_2.

(a) (b)

(c) (d)

Fig. 0.4The multi frequency C-V of Ge MOSCAPs with different post deposition oxidation condition. (a) Al2O3/Al2O3 with post deposition oxidation GeO2 520°C 3min (b) Al₂O₃/Al₂O₃ with post deposition oxidation GeO₂ 550°C 3min (c) HfO₂/Al₂O₃ with post deposition oxidation GeO2 520°C 3min (d) HfO2/Al2O3 with post deposition oxidation GeO₂ 550°C 3min_.

Table 0.3 The C-V hysteresis with different PDA condition.

Table 0.4 The C-V hysteresis with different post deposition oxidation condition.

No. C

OX

(µF/cm

²

) EOT (nm) V

FB

(V) Hysteresis (V)

a 1.34 2.58 -2.37 0.73

b 1.16 2.97 -2.26 0.7

c 1.63 2.12 -1.69 0.69

d 1.34 2.57 -1.74 0.7

No. C

_OX

(µF/cm

²

) EOT (nm) V

_FB

(V) Hysteresis (V)

A 1.21 2.85 -1.75 0.34

B 1.09 3.16 -1.66 0.36

C 2.45 1.41 -1.35 0.52

D 1.71 2.01 -1.38 0.49

(a)

(b)

Fig. 0.5 The XPS spectra of Al2O3/GeOx/p-Ge with different PDO and thermal grown GeOx condition.

36 34 32 30 28

Ge⁰ Ge¹⁺

Ge²⁺

Ge³⁺ _{PDO 520}^o_{C 30sec}

In te n s it y ( a .u .)

Ge⁴⁺

PDO 520^oC 3min

PDO 550^oC 3min

Thermal 520^oC 30sec

Binding Energy (eV)

36 34 32 30 28

GeO

x

Ge

⁴⁺

Ge

⁰

Ge 3d

Binding Energy (eV)

In te n s it y ( a .u .)

PDO 520^oC 30sec PDO 520^oC 3min PDO 550^oC 3min Thermal 520^oC 30sec

Fig. 0.6 Equivalent circuits for conductance measurements; (a) MOSCAP with interface trap time constant τit = RitCit , (b) simplified circuit of (a), (c) measured circuit, (d) including series r_s resistance and tunnel conductance G_t .

Fig. 0.7 The behavior of the interface trap time constant at room temperature as a function of capture cross section determines the part of interface traps in the bandgap observable in the MOS admittance characteristic.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

10

⁹

10

¹⁰

10

¹¹

10

¹²

=1E-15cm²

=1E-16cm²

=1E-17cm²

p-Ge n-Ge

In te rf a c e T ra p F re q u e n c y ( H z )

Valance Band Offset E-E

_v

(eV)

At room temperature

(a) (b)

(c) (d)

Fig. 0.8 2.5G_P/ωq versus frequency of Ge MOSCAPs with different PDA condition.

(a) RTO thermal GeO₂ 520°C 30sec with PDA 500°C 60sec N₂ (b) RTO thermal GeO₂ 520°C 30sec with PDA 500°C 60sec O2 (c) post deposition oxidation 520°C 3min with PDA 500°C 60sec N₂ (d) post deposition oxidation 520°C 3min with PDA 500°C 60sec O2.

(A) (B)

(C) (D) Fig. 0.9 2.5GP/ωq versus frequency of Ge MOSCAPs with different post deposition oxidation condition. (A) Al2O3/Al2O3 with post deposition oxidation GeO2 520°C 3min (B) Al₂O₃/Al₂O₃ with post deposition oxidation GeO₂ 550°C 3min (C)

HfO2/Al2O3 with post deposition oxidation GeO2 520°C 3min (D) HfO2/Al2O3 with post deposition oxidation GeO₂ 550°C 3min_.

1k 10k 100k 1M

(a)

(b)

Fig. 0.10 D_it profiles of each samples near midgap (a) samples a b c d and (b) samples A B C D.

D

it

distribution in Ge Band Gap

RTO GeO

(a) (b)

(c)

Fig. 0.11 A band diagram showing the weak inversion response (a) and the general equivalent circuits used to model the MOS capacitor C-V and G-V characteristics across the bandgap for an n-type capacitor. The first circuit (b) models one trap only:

C_ox is the oxide capacitance, C_inv the inversion capacitance, C_dep the depletion (and accumulation) capacitance, CT the trap capacitance and Gn and Gp electron and hole trap conductances. For a distribution a series of Y-circuits is used (c).

(a) (b)

(c) (d)

Fig. 0.12 The multi frequency C-V of Ge MOSCAPs with different post deposition oxidation condition after FGA. (a) Al2O3/Al2O3 with post deposition oxidation GeO2

520°C 3min (b) Al₂O₃/Al₂O₃ with post deposition oxidation GeO₂ 550°C 3min (c) HfO2/Al2O3 with post deposition oxidation GeO2 520°C 3min (d) HfO2/Al2O3 with post deposition oxidation GeO₂ 550°C 3min_.

-2 -1 0 1 2

Table 0.5 The C-V hysteresis with different post deposition oxidation condition before FGA.

Table 0.6 The C-V hysteresis with different post deposition oxidation condition after FGA.

No. C

_OX

(µF/cm

²

) EOT (nm) V

_FB

(V) Hysteresis (V)

A 1.21 2.85 -1.75 0.34

B 1.09 3.16 -1.66 0.36

C 2.45 1.41 -1.35 0.52

D 1.71 2.01 -1.38 0.49

No. C

_OX

(µF/cm

²

) EOT (nm) V

_FB

(V) Hysteresis (V)

A 1.09 3.17 -0.62 0.19

B 1.04 3.32 -0.51 0.18

C 2.13 1.62 -0.58 0.48

D 1.56 2.22 -0.56 0.43

(a) (b)

(c) (d)

Fig. 0.13 2.5GP/ωq versus frequency of Ge MOSCAPs with different post deposition oxidation condition after FGA. (a) Al2O3/Al2O3 with post deposition oxidation GeO2

520°C 3min (b) Al₂O₃/Al₂O₃ with post deposition oxidation GeO₂ 550°C 3min (c) HfO2/Al2O3 with post deposition oxidation GeO2 520°C 3min (d) HfO2/Al2O3 with post deposition oxidation GeO₂ 550°C 3min_.

1k 10k 100k 1M

(a)

(b)

Fig. 0.14 D_it profiles of each samples near midgap (a) samples A B C D without FGA (b) samples A B C D with FGA.

Chapter 3

Germanium MOSFET with

Atomic-Layer-Deposited HfO

₂

/Al

₂

O

₃

/GeO

_x

/Ge Gate Stack Fabricated by Post deposition

oxidation

3.1 Introduction

Recently, it has been increasingly difficult to further improve the performances of Si complementary metal–oxide–semiconductor (CMOS) devices through the conventional device scaling [1]. To keep up with the performance growth which indicated by the ITRS roadmap[2], device engineers need to introduce more and more new materials [3], the high mobility semiconductor materials received interest in MOSFET applications to pursue much higher device performance. Germanium is an attractive candidate for channel material due to its high electron/hole mobility and the compatibility with the conventional Si integration technologies.

However, a major problem which has retarded scaling of Ge devices is interface passivation,unlike SiO₂ with a highly thermal stability, Ge native oxides are water soluble and thermal instable, it is difficult to achieve a high-quality oxide/Ge interface due to the bad surface properties of Ge. Another problem is Ge has a smaller bandgap than conventional Si substrate, which resulting in higher junction leakage currents.

Although Ge PMOSFETs with mobilities above 300 cm²V^-1s^-1 have been reported recently [4], Ge NMOSFETs have exhibited poor drive currents and inversion mobilities lower than universal Si mobility. The two main mechanisms of NMOSFETs mobility and current drive degradation are the high interface state density D_it near the conduction band edge and the high source/drain parasitic

resistance [5]. Moreover, the significant electron trapping due to the interfacial band alignment between the native oxide of Ge and the high-k dielectrics has been

suggested as a factor limiting the performance and the reliability for Ge NMOSFETs [6]. Therefore, the passivation of the gate oxide/channel interface is needed to address the Ge NMOSFETs performance problem.

In this chapter, both germanium NMOSFET and PMOSFET were fabricated.

Effects of forming gas annealing (FGA) on junction or device characteristics are discussed, including series resistance, subthreshold swing and mobility.

在文檔中 在鍺通道金氧半場效電晶體上使用後沉積氧化製造二氧化鉿/三氧化二鋁/氧化鍺/鍺之閘極介電層堆疊結構的研究 (頁 30-52)