3.3 Effect of FGA on Ge MOSFET Electrical Characteristics
3.3.2 Device Characteristic
The effects of FGA at 300 oC on the PMOSFET and NMOSFET are shown in Fig. 3.3 and Fig. 3.4, where the ID-VG and IS-VG plots are displayed. For both PMOSFET and NMOSFET, the better subthreshold swing (165mV/dec for
PMOSFET and 151mV/dec for NMOSFET) after FGA are observed, and the on/off ratio about 1.4×103 for PMOSFET and 2.3×103 for NMOSFET are obtained. We believe that the better subthreshold swing after FGA is due to the improved high-k/Ge interfaces, the lower Dit caused the smaller subthreshold swing. And the higher on currents are observed for both samples after FGA, which may due to the better interface quality and less coulomb scattering. The ID-VG plots of both PMOSFET and NMOSFET have higher off current compared with Is-VG plots, which because of the junction leakage. We can see a positive shift of VFB after FGA, which may due to the reduction of oxide trap and fix charge.
Fig. 3.5 shows the effects of FGA at 300 oC on the ID-VD characteristics on both PMOSFET and NMOSFET. The PMOSFET has larger drive current after FGA, which exhibit higher performance. The NMOSFET has lower drive current after FGA at small drain voltage, but the drive current will become larger when drain voltage grows higher. We think the reason of lower drive current after FGA at small drain
voltage is the dopant diffusion causing lower dopant concentration, and the effective tunneling barrier becomes large, which the drain voltage need become higher to lower the effective tunneling barrier, shown in Fig. 3.6 (a). Fig. 3.6 (b) shows measured resistance versus channel length on mask for PMOSFETs, we extract the source/drain series resistance (RSD) by the Terada and Muta method:
-
- (3.1) Where Rch is channel resistance and RSD is source/drain series resistance.
For both PMOSFET and NMOSFET, RSD is increased after FGA, we think it due to the more dopant diffusion and thus lower source/drain doping concentration.
To extract the effective mobility, the effective mobility gives
(3.2) Where the drain conductance is defined as
(3.3) And the measure of Qinv from capacitance measurement
(3.4) The mobile channel charge density is determined from the gate to channel
capacitance, CGC. Then CGC is measured using the connection of Fig. 3.7, the capacitance meter is connected between the gate and the source/drain connected together with the substrate grounded. For VGS < VT (Fig. 3.7 (a)), the channel region is accumulated and the overlap capacitances 2Cov are measured. For VGS > VT (Fig.
3.7 (b)), the surface is inverted and all three capacitances, 2Cov + Cch, are measured.
Fig. 3.8 shows the effect of FGA at 300 oC on Qinv and gd for PMOSFET, we can see a positive shift of Qinv and gd curve after FGA, which may due to the reduction of oxide trap and fix charge.
Effective hole mobility versus inversion charge is plotted in Fig. 3.9, with and without FGA at 300 oC. The higher effective hole mobility is observed after FGA, which may due to the better interface quality and less coulomb scattering. We didn’t show electron mobility, because the huge resistance causing large errors on I-V and C-V measurement, which lead the measured electron mobility much lower than real value.
The NMOSFET has shown poor drive current, there are a few mechanisms behind poor NMOS performance. High source/drain parasitic resistance, inversion charge loss due to trapping in the high-k gate dielectric and high interface trap density are identified as the mechanisms for Ge NMOS performance degradation [7].
Since p-type dopants in Ge could be activated at lower temperature with small redistribution, Ge PMOSFET demonstrations with metal gate electrode and high-k dielectric have not been an issue, but the relatively higher thermal budget required to n-type dope Ge causes significant junction diffusion, which lead to high
source/drain parasitic resistance [8]. The voltage drop across the high source/drain parasitic resistance causes a huge reduction in the drain current, and the measured mobility by the split C-V appears to be lower than the real value.
The GeO2 bandgap was found to be ~5.1eV, the valance band offset was ∼3.8 eV, and the conduction band offset was ∼0.6 eV. The low conduction band offset of GeO2
is a potential problem, which can cause severe charge trapping in the bulk traps of Al2O3 and the slow traps at the GeO2/Al2O3 interface. The low conduction band offset of GeO2 and the band alignment is shown in Fig. 3.10, the electron trapping by the slow traps and the bulk traps in the NMOS inversion regime. The carriers trapped in the slow traps in the Ge NMOS inversion regime can cause a threshold-voltage shift.
Depending on the energy levels of the slow traps, the reemission of carriers
may take longer than the gate voltage sweep speed, which will result in a flatband voltage VFB shift in the C–V characteristics. Furthermore, the electron trapping takes place in the inversion regime of the NMOS retarding the formation of the inversion layer. The loss of inversion charge can cause lower Ion and a lower extracted mobility.
The charge neutrality level CNL close to the valence band edge and the acceptor type traps in the Ge bandgap have been proposed as intrinsic problems for Ge
N-MOSFETs [9]. The CNL in Ge is estimated to be only 0.09–0.08 eV above the valance band maximum. As shown in Fig. 3.11, the charged acceptor and donor dangling bond states are both located in the lower part of the Ge gap at energies Eacc=Ev+0.11 eV and Edon=Ev+0.05 eV. In most cases, the Fermi level is above the acceptor and donor levels, which means that most of the acceptors are filled, building a large negative charge at the surface. This may cause excess Coulomb
scattering thus degrading the channel mobility of Ge NMOSFET, it can be a
significant problem for Ge NMOS if the interface trap density is above 1012 cm−2 eV−1 levels.
3.4 Conclusions
In Chapter 3, we investigated the effect of FGA on Ge junction and device characteristics. On/off ratio of our p+n junction and PMOSFET reached 4 orders and 1.4×103 respectively (500°C 10 sec dopant activation, W/L = 100µm/5µm), with better subthreshold swing (165mV/dec) obtained after FGA. And on/off ratio of our n+p junction and NMOSFET reached 3.5 orders and 2.3×103 respectively (600°C 10
sec dopant activation, W/L = 100µm/5µm), with better subthreshold swing (151mV/dec) obtained after FGA. For both PMOSFETs and NMOSFETs, RSD is increased after FGA, The higher hole mobility is observed after FGA, a peak hole mobility of 375 cm2/Vs after FGA is obtained.
Pros and cons of FGA at 300°C 30 min on both PMOSFET and NMOSFET were summarized according to our experimental data. Positive VFB shift, better drive current, subthreshold swing and hole mobility is obtained after FGA, while series resistanceis increased after FGA.
References (Chapter 3)
[1] H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Ieong, “Germanium channel MOSFETs: Opportunities and challenges,”
IBM J. Res. Develop., vol. 50, no. 4/5, pp. 377–386, Sep. 2006.
[2] “International technology roadmap for semiconductors,” 2003–2007.
[3] M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie, G. Wang, R.
Loo, E. Simoen, J. Mitard, B. De Jaeger, G. Hellings, K. De Meyer, M. Meuris, and M. Heyns, “Germanium for advanced CMOS anno 2009: A SWOT analysis,”
in IEDM Tech. Dig., pp. 461–464 , 2009.
[4] D. Kuzum, A. J. Pethe, T. Krishnamohan, and K. C. Saraswat, “Ge ( 00) and (111) N- and P-FETs with high mobility and low-T mobility characterization,”
IEEE Trans. Electron Devices, vol. 56, pp. 648–655, 2009.
[5] D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Panetta, H.-S. P. Wong, and K. C. Saraswat, “High-mobility Ge N-MOSFETs and mobility degradation mechanisms,” IEEE Trans. Electron Devices, vol. 59, pp. 59–66, 2011.
[6] G. Lucovsky, S. Lee, J. P. Long, H. Seo, and J. Luning, “Elimination of GeO2
and Ge3N4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates,” Appl. Surf. Sci., vol.
254, pp. 7933–7937, 2008.
[7] D. Kuzum, T. Krishnamohan, A. Nainani, S. Yun, P. A. Pianetta, H. S. P. Wong, and K. C. Saraswat, “High-mobility Ge N-MOSFETs and mobility degradation mechanisms,” IEEE Trans. Electron Devices, vol. 58, pp. 59–66, 2011.
[8] C. O. Chui, L. Kulig, J.Moran,W. Tsai, and K. C. Saraswat, “Germanium n-type shallow junction dependences,” Appl. Phys. Lett., vol. 87,, pp. 091 909, 2005.
[9] P. Tsipas and A. Dimoulas, “Modeling of negatively charged states at the Ge surface and interfaces,” Appl. Phys. Lett., vol. 94, pp. 012 114, 2009.
Cyclic DHF clean of Ge
4200 Å SiO
2isolation layer
1
stlitho. and B/P imp. (20keV, 1E15cm
-2)
Dopant activation (500
oC 10s, 600
oC 10s)
2
ndlitho. : define AA
10 cycles ALD Al
2O
3 PDO 520
oC 3min GeO
xpassivation
50 cycles ALD HfO
2 PDA 500
oC 60sec N
2 3
rdlitho. : define contact hole
Al deposition
4
thlitho. : define metal pad
Backside contact (Al)
FGA (300
oC 30min)
Fig. 0.1The process flow and device structure of Ge MOSFET
(a)
(b)
Fig. 0.2 I–V characteristics of p+n and n+p junctions, before and after performing FGA. (a) p+n junction (b) n+p junction
-2.5 -2.0 -1.5 -1.0 -0.5 0.0
(a)
(a)
(a)
(b)
Fig. 0.6 (a)The schottky junction tunneling. (b)Series resistance from Terada and Muta method.
0 10 20 30 40 50
0 1000 2000 3000 4000 5000
M e a s u re d R e s is ta n c e , R
m(
)channel length on mask
( m
)w/o FGA VG-V
th= -1V VG-V
th= -1.5V VG-V
th= -2V
RSD=164
Φ
BN
+-Ge
Al
N
D1> N
D2(a)
(b)
Fig. 0.7 Schematic for gate-to-channel capacitance measurements for (a) VGS < VT,(b) VGS > VT
(a)
Fig. 0.9 Effective mobility versus inversion charge is plotted with and without FGA at 300 oC.
0.5 1.0 1.5 2.0 2.5 3.0 3.5
150 200 250 300 350 400
H o le M o b il it y ( cm
2/V s )
Inversion Charge, Q
inv
(x10
12cm
-2)
w/o FGA with FGA
(a)
(b)
Fig. 0.10 (a) Schematics of the effect of the low conductance-band offset on the electron trapping by the slow traps and the bulk traps in the NMOS inversion regime.
(b) Dit energy distribution of acceptor and donor DB surface states and surface band diagram of n-Ge.
Chapter 4
Epi-Ge on SOI MOSFET with
Atomic-Layer-Deposited HfO
2/Al
2O
3/GeO
x/Ge Gate Stack Fabricated by Post Deposition
Oxidation
4.1 Introduction
Silicon-on-insulator (SOI), means place a thin layer of silicon on top of the insulator such as SiO2. SOI CMOS process can be readily developed due to the compatibility with established bulk processing technology. The main advantage of SOI devices over bulk CMOS is the very low junction capacitance, the source and drain junction capacitance is almost entirely eliminated in SOI MOSFETs, hence SOI devices have faster switching speed which improve devices performance. When the silicon film is thicker than the maximum gate depletion width, it’s called partially depleted SOI (PDSOI), the floating body effect in PDSOI reduced threshold voltage at high drain voltage [1]. When the silicon film is thin enough that the entire film is depleted before the threshold condition is reached, it’s called fully depleted SOI (FDSOI). Floating body effect can be largely avoided in FDSOI devices, and the sub threshold slope of FDSOI MOSFETs can be near the ideal 60mV per decade at 300K.
For the small bandgap material Ge, the Ge MOSFET junction leakage is a real concern, thin body Ge-on-insulator (GOI) is one of the solution. The advantages of thin body GOI are low parasitic capacitance, immunity for short channel effects, and low junction leakage current [2].
In this chapter, both germanium NMOSFET and PMOSFET were fabricated on epitaxial Ge on thin SOI substrates with two different structures, respectively. Effect of forming gas annealing (FGA) on device characteristics is discussed, including series resistance, subthreshold swing and mobility.