Characteristics
The effects of FGA at 300 oC on the PMOSFETs with epi-60nm Ge on SOI and epi-30nm Ge on SOI are shown in Fig. 4.6, where the ID-VG and IS-VG plots are displayed. For both epi-60nm Ge on SOI and epi-30nm Ge on SOI, the better
subthreshold swing and positive Vth shift after FGA are observed. We believe that the better subthreshold swing is due to the improved high-k/Ge interfaces, the lower Dit caused the smaller subthreshold swing, and the positive Vth shift is because forming gas annealing lowering both fix charge and oxide trap charge. The higher on currents are observed for both samples after FGA, which may due to the less coulomb
scattering. The ID-VG and IS-VG plots have same off current, which means that epi-Ge on SOI has no substrate leakage. The lower off current after FGA is observed, it is because of the effective reduction of defects such as the bulk defects in epi-Ge on SOI substrate.
Fig. 4.7 shows the effects of FGA at 300 oC on the ID-VG characteristics of PMOSFETs for both epi-60nm Ge on SOI and epi-30nm Ge on SOI. Both of them have larger drive current after FGA, which exhibit higher performance. Series resistanceis increased after FGA, we think it due to the more dopant diffusion and thus lower source/drain doping concentration.
Effective hole mobility versus inversion charge is plotted in Fig. 4.8, with and without FGA at 300 oC. The higher effective hole mobility is observed after FGA, which may due to the better interface quality and less coulomb scattering.
The effects of FGA at 300 oC on the NMOSFETs with epi-60nm Ge on SOI and epi-30nm Ge on SOI are shown in Fig. 4.9, where the ID-VG and IS-VG plots are displayed. As the result in PMOSFETs, both epi-60nm Ge on SOI and epi-30nm Ge on SOI have better subthreshold swing, higher on currents, positive Vth shift and lower off current after FGA. The NMOSFET has lower drive current after FGA at small drain voltage, but the drive current will become larger when drain voltage grows higher. We think the reason of lower drive current after FGA at small drain voltage is the dopant diffusion causing lower dopant concentration, and the effective tunneling barrier becomes large, which the drain voltage need become higher to lower the effective tunneling barrier.
Fig. 4.10 shows the effects of FGA at 300 oC on the ID-VD characteristics of NMOSFETs for both epi-60nm Ge on SOI and epi-30nm Ge on SOI. Both of them have larger drive current after FGA as in PMOSFETs.
To compare the epi-60nm Ge on SOI and epi-30nm Ge on SOI MOSFETs in our experiment data, we found that epi-30nm Ge on SOI MOSFETs have better
subthreshold swing because of the better gate control ability of thinner body, while epi-60nm Ge on SOI MOSFETs have larger on current and higher mobility due to the lower dislocation density.
4.4 Conclusions
In Chapter 4, we investigated the effect of FGA on epi-Ge on SOI MOSFETs characteristics. The positive Vth shift, better subthreshold swing (464mV/dec for epi-60nm PMOSFET, 307mV/dec for epi-30nm PMOSFET, 256mV/dec for epi-60nm
NMOSFET and 252mV/dec for epi-30nm NMOSFET) are obtained after FGA. The on/off ratio is about 7.2×101 for epi-60nm PMOSFET, 3.3×102 for epi-30nm
PMOSFET, 3.4×102 for epi-60nm NMOSFET and 3.7×102 for epi-30nm NMOSFET.
For both PMOSFETs and NMOSFETs, RSD is increased after FGA, The higher hole mobility is observed after FGA, a peak hole mobility of 313 cm2/Vs for epi-60nm PMOSFET and 194 cm2/Vs for epi-30nm NMOSFET after FGA are obtained.
Epi-30nm Ge on SOI MOSFETs have better subthreshold swing because of the better gate control ability of thinner body, while epi-60nm Ge on SOI MOSFETs have larger on current and higher mobility due to the lower dislocation density.
References (Chapter 4)
[1] Y. Taur, T. H. ing, “Fundamentals of Modern LSI Devices, Cambridge University Press,” Cambridge, pp. 11,1998.
[2] T. Maeda, K. Ikeda, S. Nakaharai, T. Tezuka, N. Sugiyama, Y. Moriyama, and S. Takagi, “High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain,” IEEE Electron Device Lett., vol. 26, pp. 102–104, 2005.
Fig. 0.1XRD data of epitaxial Ge on SOI. Higher Ge (004) peak indicates 60nm Ge has higher quality on SOI.
(a)
(b)
Fig. 0.2 (a) (b) TEM image of epi-60nm Ge on SOI. Lower dislocation density with smooth surface is observed.
(a)
(b)
Fig. 0.3 (a) (b) TEM image of epi-30nm Ge on SOI. High dislocation density exists in Ge film accompanying with high roughness.
(a)
(b)
Fig. 0.4 The two epi-Ge on SOI substrate structures. (a) epi-60nm Ge on SOI. (b) epi-30nm Ge on SOI.
Cyclic DHF clean of GSOI
4200 Å SiO
2isolation layer
1
stlitho. and B/P imp. (20keV, 1E15cm
-2)
Dopant activation (500
oC 10s, 600
oC 10s)
2
ndlitho. : define AA
10 cycles ALD Al
2O
3 PDO 520
oC 3min GeO
xpassivation
50 cycles ALD HfO
2 PDA 500
oC 60sec N
2 3
rdlitho. : define contact hole
Al deposition
4
thlitho. : define metal pad
FGA (300
oC 30min)
Fig. 0.5The process flow and device structure of epi-Ge on SOI MOSFET
(a) (b)
(c) (d)
Fig. 0.6 Effects of FGA at 300 oC on the PMOSFET. (a) Epi-60nm Ge on SOI ID-VG
characteristic. (b) Epi-60nm Ge on SOI IS-VG characteristic. (c) Epi-30nm Ge on SOI ID-VG characteristic. (d) Epi-30nm Ge on SOI IS-VG characteristic.
(a)
(a)
(b)
Fig. 0.8 Effective mobility versus inversion charge is plotted with and without FGA at 300 oC on PMOSFET. (a) Epi-60nm Ge on SOI. (b) Epi-30nm Ge on SOI.
1.5 2.0 2.5 3.0 3.5 4.0
200 250 300 350
H o le M o b il it y ( cm
2/V s )
Inversion Charge, Q
inv( x10
12cm
-2)
w/o FGA with FGA
1.0 1.5 2.0 2.5 3.0 3.5
50 100 150 200 250
H o le M o b il it y ( cm
2/V s )
Inversion Charge, Q
inv
( x10
12cm
-2)
w/o FGA with FGA
(a) (b)
(c) (d)
Fig. 0.9 Effects of FGA at 300 oC on the NMOSFET. (a) Epi-60nm Ge on SOI ID-VG
characteristic. (b) Epi-60nm Ge on SOI IS-VG characteristic. (c) Epi-30nm Ge on SOI ID-VG characteristic. (d) Epi-30nm Ge on SOI IS-VG characteristic.
(a)
Chapter 5
Conclusions
In this thesis, we had shown Ge PMOS capacitors using post deposition oxidation method to form a thin GeOx IL by oxidizing Ge surface beneath an ALD Al2O3 layer using high-k RTO, the dependence of the GeOx/Ge interface qualities on the post deposition oxidation conditions such as post deposition oxidation temperature and post deposition annealing ambient was investigated. The Ge 3d XPS spectra of Al2O3/GeOx/p-Ge with PDO 520 °C 30sec, PDO 520 °C 3min, PDO 550 °C 3min and RTO thermal GeO2 520 °C 30sec is shown, the increase of post deposition oxidation time or temperature will larger the Ge3+peak, and the large Ge3+ peak could improve high-k/Ge interface, the Ge3+ peak shows better interface quality than Ge4+ peak in our studies. The EOT value was scaled down to 1.41 nm and a lower Dit value was obtained by PDO. The larger EOT but lower Dit value was obtained by using O2
annealing. The positive VFB shift and lower C-V hysteresis is shown in the samples after FGA, and the Dit value has been reduced 16% ~ 44% after FGA. Then, the HfO2/Al2O3 gate stack with PDO 520°C 3min was selected to be the best condition to fabricate Ge MOSFETs.
We have investigated the effect of FGA on Ge MOSFETs and epi-Ge on SOI MOSFETs. On/off ratio of our p+n junction and Ge PMOSFET reached 4 orders and 1.4×103 respectively (500°C 10 sec dopant activation, W/L = 100µm/5µm), with better subthreshold swing (165mV/dec) obtained after FGA. And On/off ratio of our
n+p junction and Ge NMOSFET reached 3.5 orders and 2.3×103 respectively (600°C 10 sec dopant activation, W/L = 100µm/5µm), with better subthreshold swing
(151mV/dec) obtained after FGA. Also, the better subthreshold swing (464mV/dec for epi-60nm PMOSFET, 307mV/dec for epi-30nm PMOSFET, 256mV/dec for epi-60nm NMOSFET and 252mV/dec for epi-30nm NMOSFET) obtained after FGA. The on/off ratio is about 7.2×101 for epi-60nm PMOSFET, 3.3×102 for epi-30nm
PMOSFET, 3.4×102 for epi-60nm NMOSFET and 3.7×102 for epi-30nm NMOSFET.
For both Ge MOSFETs and epi-Ge on SOI MOSFETs, RSD and hole mobility are increased after FGA, a peak hole mobility of 375 cm2/Vs for bulk Ge PMOSFET, 313 cm2/Vs for epi-60nm PMOSFET and 194 cm2/Vs for epi-30nm PMOSFET after FGA are obtained. Epi-30nm Ge on SOI MOSFETs have better subthreshold swing because of the better gate control ability of thinner body, while epi-60nm Ge on SOI
MOSFETs have larger on current and higher mobility due to the lower dislocation density.
Finally, pros and cons of FGA at 300°C 30 min on both PMOSFET and
NMOSFET were summarized according to our experimental data. Positive Vth shift, higher on current, better subthreshold swing and higher hole mobility are obtained after FGA, while series resistanceis increased after FGA.